Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/09/2025 and 12/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of the Claims
Claims 1-15 filed 12/26/2024 form the basis of the present examination.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because:
The opening sentence “The present disclosure relates to an apparatus..” is improper.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a signal superposition unit” and “a signal power detection unit” and “a differential signal detection unit” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
In this application in claim 1 the recited “a signal superposition unit” coupled with the functional language “to receive and switch a first input signal and a second input signal”.
In this application in claim 1 the recited “a signal power detection unit” coupled with the functional language “to detect power of the signal output from the signal superposition unit”.
In this application in claim 1 the recited “a differential signal detection unit” coupled with the functional language “to generate a differential signal for the power of the signal output”.
All these limitations in claim 1 have no structural meaning and are considered a generic placeholder.
In the present application (PGPUB NO: US 20250216429 A1) discloses:
In Paragraph 46, “[0046] Referring to FIG. 3, the signal superposition unit 110 in the apparatus for detecting a relative phase according to an embodiment of the present disclosure includes a switch network 111 that switches and outputs the first input signal and the second input signal, a sensing resistor 112 connected to one of the output signals of the switch network 111, and a sensing capacitor 113 having one terminal connected to one of the output signals of the switch network 111 and the other terminal connected to the sensing resistor 112.”
[0100] For reference, the components according to an embodiment of the present disclosure may be implemented in the form of software or hardware such as a digital signal processor (DSP), a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC), and may perform predetermined roles.
35 USC § 112(b) Rejections
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites, “a signal superposition unit configured to receive and switch a first input signal and a second input signal…”. It is not clear what a signal superposition unit is and what element or structure is used for signal superposition unit. Then claim recites switch a first input signal and a second input signal. However, it is not clear how the first input signal and second input signal is switched. Because claim does not recite any switching element and therefore it is not clear how the signal superposition unit works.
Claim recites a differential signal detection unit configured to generate a differential signal for the power of the signal output according to the switching of the first input signal and the second input signal in the signal superposition unit. It is not clear what structure or element is used for differential signal detection unit or what step is used to generate differential signal and how the signal is switched. Therefore, the claim language is not clear.
Clarification is required so that the claim language is clear.
Similarly independent claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, because of the same reason as stated above for independent claim 1 because of the same limitation recited in independent claim 12.
Claims 2-11 and 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of their dependence from claims 1 and 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 12-13 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Bao in the US patent Application Publication Number US 20130009627 A1.
Regarding claim 1, Bao teaches an apparatus for detecting a relative phase (a phase detector which can work over an extended frequency range and in an extended phase interval; Paragraph [0001] Line 1-3; FIG. 1 shows a first embodiment 100 of phase detector of the invention. The phase detector 100 comprises a first 116 and a second 117 input port, one for each of two signals, V.sub.in1, V.sub.in2, between which a phase difference .phi. can be measured; Paragraph [0029] Line 1-5), comprising:
a signal superposition unit [150] (balun 150 is considered as the signal superposition unit as the claim does not recite any structure of signal superposition unit) (In addition, the .PI.-network is connected to the balanced ports of a balun 150 by means of one of the balanced ports of the balun being connected to a point in the .PI.-network between the first capacitor 140 and the first inductor 120, which here corresponds to the first input port 116, and the other of the balanced ports being connect to a point in the .PI.-network between the second capacitor 145 and the second inductor 125, which here corresponds to the second input port 117. This can also be seen as one of the balanced ports being connected to each of the input ports 116, 117 of the phase detector 100; Paragraph [0031] Line 1-11) configured to receive and switch a first input signal [V1] and a second input signal [V2] having a phase delay θ.sub.d with respect to the first input signal (A first sinusoid signal A*sin(.omega.t) from a first signal source 120 is shown as being connected at the input port 116, and a second sinusoid signal A*sin(.omega.t+.phi.) from a second signal source 125 is shown as being connected to the other of the input ports, 117. There is a phase difference of .phi. between the two input signals.; Paragraph [0032] line 4-9) so that the first input signal [120] and the second input signal [125] pass through a sensing resistor [130, 135] (Also shown in FIG. 1 is one resistor 130, 135, from each of the input signal sources, in this case via respective resistors 130, 135, which represent a resistance in the signal sources 120, 125; Paragraph [0032] Line 9-13) or a sensing capacitor [140, 145] (As is also shown in FIG. 1, the intermediate point is connected to ground via a passive component of a second kind, in this example the capacitors 140, 145; Paragraph [0038] Line 1-3), respectively, and to superpose and output the passed signals;
a signal power detection unit [155] configured to detect power of the signal output from the signal superposition unit [150] ([0033] As shown in FIG. 1, the power detectors are connected to enable measuring the signal amplitude at the following points in the phase detector 100: [0034] a first power detector 105 at one of the balun's balanced ports for measuring an amplitude v.sub.1, [0035] a second power detector 115 at the other of the balun's balanced ports for measuring an amplitude v.sub.2, [0036] a third power detector 110 device at an intermediate point between the balun's balanced ports, connected to each of the first and second input ports 116, 117, via a passive component of a first kind, in this example inductors 120, 125. This power detector measures an amplitude v.sub.3 [0037] a fourth power detector 155 at the unbalanced port of the balun for measuring an amplitude v.sub.4); and
a differential signal detection unit configured to generate a differential signal for the power of the signal output according to the switching of the first input signal and the second input signal in the signal superposition unit, and to detect the differential signal that changes according to the phase delay θ.sub.d (the difference between |v.sub.3| and |v.sub.4|, or rather, between |v.sub.3| and |v.sub.4| indicates the value of the phase difference .phi. between the two input signals; Paragraph [0040] Line 1-3).
Regarding claim 2, Bao teaches an apparatus for detecting a relative phase,
wherein the signal superposition unit [150] comprises: a switch network configured to switch and output the first input signal [116] and the second input signal [117] (The phase detector 100 comprises a so called .PI.-network consisting of a first and a second capacitor 140, 145 i.e. two passive components of a second kind and a first and a second inductor 120, 125, i.e. two passive components of a first kind. Each of the capacitors 140, 145 is connected from one of the input ports 116, 117 to ground, and the two inductors 120, 125 are connected in series to each other between the two input ports 116, 117; Paragraph [0030] Line 1-8; In addition, the .PI.-network is connected to the balanced ports of a balun 150 by means of one of the balanced ports of the balun being connected to a point in the .PI.-network between the first capacitor 140 and the first inductor 120, which here corresponds to the first input port 116, and the other of the balanced ports being connect to a point in the .PI.-network between the second capacitor 145 and the second inductor 125, which here corresponds to the second input port 117. This can also be seen as one of the balanced ports being connected to each of the input ports 116, 117 of the phase detector 100; Paragraph [0031] Line 1-10; Balun here function as a switching network);
a sensing resistor [130, 135] (Also shown in FIG. 1 is one resistor 130, 135, from each of the input signal sources, in this case via respective resistors 130, 135, which represent a resistance in the signal sources 120, 125; Paragraph [0032] Line 9-13) connected to one of output signals of the switch network (Figure 1 shows that the resistor connected with balun 150); and
a sensing capacitor [140, 145] (As is also shown in FIG. 1, the intermediate point is connected to ground via a passive component of a second kind, in this example the capacitors 140, 145; Paragraph [0038] Line 1-3) having one terminal connected to one of the output signals of the switch network and the other terminal connected to the sensing resistor [130, 135] (Figure 1 shows that a sensing capacitor [140, 145] having one terminal connected to one of the output signals of the switch network and the other terminal connected to the sensing resistor; Returning now to the embodiments 100 and 400 shown in FIGS. 1 and 6, the following can be said: these embodiments comprise a .pi.-network or a T-network, which in turn comprises a number of passive components, such as, for example, the inductors 120 and 125, and the capacitors 140, 145, in FIG. 1 and the capacitors 120', 125' and the inductor 405 of FIG. 6. These components are all passive components, and in a phase detector of the invention, the type of passive component can be changed with retained function. In other words, the inductors 120 and 125, as well as the capacitors 140, 145, can be replaced "pair-wise" with passive components of other kinds, and the inductor 405 can be replaced with another passive component. Well known examples of passive components are capacitors, resistors and inductors. As an example of the "replacement principle", the inductors 120, 125 can be replaced with capacitors, or the capacitors 140, 145 can be replaced with resistors; Paragraph [0056] Line 1-17).
Regarding claim 3, Bao teaches an apparatus for detecting a relative phase,
wherein the signal power detection unit detects the power (This configuration of the power detectors enables the following measurements to be made: [0040] the difference between |v.sub.3| and |v.sub.4|, or rather, between |v.sub.3| and |v.sub.4| indicates the value of the phase difference .phi. between the two input signals; Paragraph [0040] Line 1-3), by receiving an output signal at a connection node of the sensing resistor and the sensing capacitor [140, 145] ([0033] As shown in FIG. 1, the power detectors are connected to enable measuring the signal amplitude at the following points in the phase detector 100: [0034] a first power detector 105 at one of the balun's balanced ports for measuring an amplitude v.sub.1, [0035] a second power detector 115 at the other of the balun's balanced ports for measuring an amplitude v.sub.2, [0036] a third power detector 110 device at an intermediate point between the balun's balanced ports, connected to each of the first and second input ports 116, 117, via a passive component of a first kind, in this example inductors 120, 125. This power detector measures an amplitude v.sub.3 [0037] a fourth power detector 155 at the unbalanced port of the balun for measuring an amplitude v.sub.4; [0038] As is also shown in FIG. 1, the intermediate point is connected to ground via a passive component of a second kind, in this example the capacitors 140, 145).
Regarding claim 12, Bao teaches a method for detecting a relative phase (a phase detector which can work over an extended frequency range and in an extended phase interval; Paragraph [0001] Line 1-3; FIG. 1 shows a first embodiment 100 of phase detector of the invention. The phase detector 100 comprises a first 116 and a second 117 input port, one for each of two signals, V.sub.in1, V.sub.in2, between which a phase difference .phi. can be measured; Paragraph [0029] Line 1-5), comprising:
receiving and switching, by a signal superposition unit [150] (balun 150 is considered as the signal superposition unit as the claim does not recite any structure of signal superposition unit) (In addition, the .PI.-network is connected to the balanced ports of a balun 150 by means of one of the balanced ports of the balun being connected to a point in the .PI.-network between the first capacitor 140 and the first inductor 120, which here corresponds to the first input port 116, and the other of the balanced ports being connect to a point in the .PI.-network between the second capacitor 145 and the second inductor 125, which here corresponds to the second input port 117. This can also be seen as one of the balanced ports being connected to each of the input ports 116, 117 of the phase detector 100; Paragraph [0031] Line 1-11) a first input signal [V1] and a second input signal [V2] having a phase delay θ.sub.d with respect to (A first sinusoid signal A*sin(.omega.t) from a first signal source 120 is shown as being connected at the input port 116, and a second sinusoid signal A*sin(.omega.t+.phi.) from a second signal source 125 is shown as being connected to the other of the input ports, 117. There is a phase difference of .phi. between the two input signals.; Paragraph [0032] line 4-9) the first input signal [120] and the second input signal [125] pass through a sensing resistor [130, 135] (Also shown in FIG. 1 is one resistor 130, 135, from each of the input signal sources, in this case via respective resistors 130, 135, which represent a resistance in the signal sources 120, 125; Paragraph [0032] Line 9-13) or a sensing capacitor [140, 145] (As is also shown in FIG. 1, the intermediate point is connected to ground via a passive component of a second kind, in this example the capacitors 140, 145; Paragraph [0038] Line 1-3), respectively, and to superpose and output the passed signals;
detecting, by a signal power detection unit [155], power of the signal output from the signal superposition unit [150] ([0033] As shown in FIG. 1, the power detectors are connected to enable measuring the signal amplitude at the following points in the phase detector 100: [0034] a first power detector 105 at one of the balun's balanced ports for measuring an amplitude v.sub.1, [0035] a second power detector 115 at the other of the balun's balanced ports for measuring an amplitude v.sub.2, [0036] a third power detector 110 device at an intermediate point between the balun's balanced ports, connected to each of the first and second input ports 116, 117, via a passive component of a first kind, in this example inductors 120, 125. This power detector measures an amplitude v.sub.3 [0037] a fourth power detector 155 at the unbalanced port of the balun for measuring an amplitude v.sub.4); and
generating, by a differential signal detection unit a differential signal for the power of the signal output according to the switching of the first input signal and the second input signal in the signal superposition unit, and to detect the differential signal that changes according to the phase delay θ.sub.d (the difference between |v.sub.3| and |v.sub.4|, or rather, between |v.sub.3| and |v.sub.4| indicates the value of the phase difference .phi. between the two input signals; Paragraph [0040] Line 1-3).
Regarding claim 13, Bao teaches a method for detecting a relative phase,
the detecting of the power of the output signal (This configuration of the power detectors enables the following measurements to be made: [0040] the difference between |v.sub.3| and |v.sub.4|, or rather, between |v.sub.3| and |v.sub.4| indicates the value of the phase difference .phi. between the two input signals; Paragraph [0040] Line 1-3), comprises:
detecting the power by receiving an output signal at a connection node of the sensing resistor [120, 125] and the sensing capacitor [140, 145] ([0033] As shown in FIG. 1, the power detectors are connected to enable measuring the signal amplitude at the following points in the phase detector 100: [0034] a first power detector 105 at one of the balun's balanced ports for measuring an amplitude v.sub.1, [0035] a second power detector 115 at the other of the balun's balanced ports for measuring an amplitude v.sub.2, [0036] a third power detector 110 device at an intermediate point between the balun's balanced ports, connected to each of the first and second input ports 116, 117, via a passive component of a first kind, in this example inductors 120, 125. This power detector measures an amplitude v.sub.3 [0037] a fourth power detector 155 at the unbalanced port of the balun for measuring an amplitude v.sub.4; [0038] As is also shown in FIG. 1, the intermediate point is connected to ground via a passive component of a second kind, in this example the capacitors 140, 145).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bao in the US patent Application Publication Number US 20130009627 A1 in view of Zerbe et al. (Hereinafter, “Zerbe”) in the US patent Application Publication Number US 20170222845 A1.
Regarding claim 4, Bao fails to teach an apparatus for detecting a relative phase, further comprising: a signal sampler configured to set, as a first sampling interval, an interval in which the first input signal passes through the sensing resistor and the second input signal passes through the sensing capacitor, to set, as a second sampling interval, an interval in which the first input signal passes through the sensing capacitor and the second input signal passes through the sensing resistor, as the switch network switches the signals, and to store the power of the output signal at the connection node in each of the first and second sampling intervals.
Zerbe teaches a high frequency digital signal bus, and more particularly to a digital signal output driver that uses multi-level signaling to increase the data rate of the bus (Paragraph [0002] Line 1-3),
further comprising: a signal sampler [184] configured to set, as a first sampling interval (In FIG. 3A, an integrating receiver 180 improves performance in a noisy environment. The integrating receiver 180 is a type of matched filter. In the integrating receiver 180, an integrator 182, a sample and hold (S/H) circuit 184, an amplifier 186 and a latch 188 are connected in series and receive and output differential signals. The integrating receiver 180 integrates a bias current I.sub.BIAS1 based on the difference between the differential input signals V.sub.IN+ and V.sub.IN− over a given period of time, called the integration interval. Prior to the start of the integration interval, the output value of the integrator 182 is initially set equal to zero volts. After integration is complete and additional processing, the latch 188 stores the result of the integration; Paragraph [0014] Line 1-12), an interval in which the first input signal passes through the sensing resistor and the second input signal passes through the sensing capacitor (in view of Bao), to set, as a second sampling interval, an interval in which the first input signal passes through the sensing capacitor and the second input signal passes through the sensing resistor, as the switch network switches the signals, and to store the power of the output signal at the connection node in each of the first and second sampling intervals (Referring also to FIG. 3B, the integrating receiver 180 operates according to three phases—an integration phase (Phase I), a hold phase (Phase II) and a latch phase (Phase III). A first timing signal φ 192 and a second timing signal Ψ_b 194 define the phases and control the operation of the integrating receiver 180. The first timing signal φ defines the integration interval or phase and is a clock that operates at the system clock frequency. The second timing signal Ψ_b defines the hold and latch phases when the first timing signal φ is no longer in the integration phase. In some implementations, the first timing signal φ is phase shifted with respect to the system clock; Paragraph [0015] Line 1-12). The purpose of doing so is to provide an efficient high speed signaling system and to reduce the probability of errors caused by noise.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Bao in view of Zerbe, because Zerbe teaches to include a signal sampler provides an efficient high speed signaling system (Paragraph [0003]) and reduces the probability of errors caused by noise (Paragraph [0012]).
Regarding claim 14, Bao fails to teach a method for detecting a relative phase, further comprising: setting, by a signal sampler, as a first sampling interval, an interval in which the first input signal passes through the sensing resistor and the second input signal passes through the sensing capacitor, to set, as a second sampling interval, an interval in which the first input signal passes through the sensing capacitor and the second input signal passes through the sensing resistor, as the switch network switches the signals, and to store the power of the output signal at the connection node in each of the first and second sampling intervals.
Zerbe teaches a high frequency digital signal bus, and more particularly to a digital signal output driver that uses multi-level signaling to increase the data rate of the bus (Paragraph [0002] Line 1-3),
setting, by a signal sampler [184], as a first sampling interval (In FIG. 3A, an integrating receiver 180 improves performance in a noisy environment. The integrating receiver 180 is a type of matched filter. In the integrating receiver 180, an integrator 182, a sample and hold (S/H) circuit 184, an amplifier 186 and a latch 188 are connected in series and receive and output differential signals. The integrating receiver 180 integrates a bias current I.sub.BIAS1 based on the difference between the differential input signals V.sub.IN+ and V.sub.IN− over a given period of time, called the integration interval. Prior to the start of the integration interval, the output value of the integrator 182 is initially set equal to zero volts. After integration is complete and additional processing, the latch 188 stores the result of the integration; Paragraph [0014] Line 1-12), an interval in which the first input signal passes through the sensing resistor and the second input signal passes through the sensing capacitor (in view of Bao), to set, as a second sampling interval, an interval in which the first input signal passes through the sensing capacitor and the second input signal passes through the sensing resistor, as the switch network switches the signals, and to store the power of the output signal at the connection node in each of the first and second sampling intervals (Referring also to FIG. 3B, the integrating receiver 180 operates according to three phases—an integration phase (Phase I), a hold phase (Phase II) and a latch phase (Phase III). A first timing signal φ 192 and a second timing signal Ψ_b 194 define the phases and control the operation of the integrating receiver 180. The first timing signal φ defines the integration interval or phase and is a clock that operates at the system clock frequency. The second timing signal Ψ_b defines the hold and latch phases when the first timing signal φ is no longer in the integration phase. In some implementations, the first timing signal φ is phase shifted with respect to the system clock; Paragraph [0015] Line 1-12). The purpose of doing so is to provide an efficient high speed signaling system and to reduce the probability of errors caused by noise.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Bao in view of Zerbe, because Zerbe teaches to include a signal sampler provides an efficient high speed signaling system (Paragraph [0003]) and reduces the probability of errors caused by noise (Paragraph [0012]).
Allowable Subject Matter
Claims 5-11 and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Schmid (US 20210143918 A1) discloses, “METHOD AND SYSTEM FOR DETERMINING AND/OR ADJUSTING PHASES OF AT LEAST TWO ELECTRICAL SIGNALS- [0001] The present disclosure relates to a method for determining and/or adjusting phases of at least two electrical signals. The present disclosure further relates to a signal generator system for determining and/or adjusting phases of at least two electrical signals. [0040] FIG. 1 shows a block diagram of a signal generator system 10. The signal generator system comprises a first signal generator 12, a second signal generator 14, a first splitter unit 16, a second splitter unit 18, a first phase measurement block 20 and a control module 21. [0042] In the embodiment shown in FIG. 1, the first phase measurement block 20 comprises a combiner unit 22 and a power measurement unit 24. [0043] The signal generator system 10 further comprises a second phase measurement block 26, as shown in FIG. 1. The second phase measurement block 26 comprises another combiner unit 22 and another power measurement unit 24. The second phase measurement block 26 is built up similar to the first phase measurement block 20, for example identical to the first phase measurement block 20. As such, the second phase measurement block 26 may comprise one or more circuits for carrying out its respective functionality, which will be described in more detail below. [0044] The first splitter unit 16 and the second splitter unit 18 each comprise an input channel 28, a first output channel 30 and a second output channel 32. The combiner units 22 each comprise a first input channel 34, a second input channel 36, and an output channel 38. [0045] In the embodiment of FIG. 1, the input channel 28 of the first splitter unit 16 is connected to the first signal generator 12. The input channel 28 of the second splitter unit 18 is connected to the second signal generator 14. The first output channel 30 of the first splitter unit 16 is connected to the first input channel 34 of the combiner unit 22 of the first phase measurement block 20. The first output channel 30 of the second splitter unit 18 is connected to the second input channel 36 of the combiner unit 22 of the first phase measurement block 20. The second output channel 32 of the first splitter unit 16 is connected to the first input channel 34 of the combiner unit 22 of the second phase measurement block 26. The second output channel 32 of the second splitter unit 18 is connected to the second input channel 36 of the combiner unit 22 of the second phase measurement block 26-However Schmid does not disclose a differential signal detection unit configured to generate a differential signal for the power of the signal output according to the switching of the first input signal and the second input signal in the signal superposition unit, and to detect the differential signal that changes according to the phase delay θ.sub.d.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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