DETAILED ACTION
1. This Office Action is responsive to claims filed for No. 19/001,917 on February 4, 2026. Please note Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al.
( US 2015/0310824 A1 ) in view of Hong et al. ( US 2010/0156879 A1 ).
Yang teaches in Claim 1:
A display apparatus ( [0003] disclose a display device ), comprising:
a display panel including a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines ( Figure 1, [0035] discloses a display panel 10 with a plurality of data lines DL and cells disposed in a matrix (read as a plurality of pixels) );
a first data driving portion including a plurality of first data integrated circuits (ICs) connected to one ends of the plurality of data lines ( Figure 1, [0034] disclose a first set of data drivers 31 comprising source drive ICs, connected to one end of data lines DL );
a second data driving portion including a plurality of second data ICs connected to other ends of the plurality of data lines ( Figure 1, [0034] disclose a second set of data drivers 32 comprising source drive ICs, connected to the other end of data lines DL );
a timing control portion providing input first and second lock signals to the first data driving portion and the second data driving portion, respectively ( Figure 1, [0039] discloses a timing controller 20 which can output a plurality of signals, including a clock training pattern signal or preamble signal (read as lock signals) to both the first and second set of drivers 31 and 32. Please see [0056] for more details as well ); and
a comparison circuit receiving an output first lock signal, which is generated by the first data driving portion according to the input first lock signal, [directly] from the first data driving portion, and receiving an output second lock signal, which is generated by the second data driving portion according to the input second lock signal, [directly] from the second data driving portion, the comparison circuit comparing and synchronizing the output first and second lock signals to generate a synchronous lock signal, the comparison circuit providing the synchronous lock signal to the timing control portion ( Figure 1, [0041] discloses a synchronization unit 50 (read as a comparison unit) which receives LOCK_UP and LOCK_DN from drivers 31 and 32, respectively. Figure 1 shows the input preamble signals to 31 and 32 and the output LOCK_UP and LOCK_DN signals from 31 and 32. [0075]-[0076] discloses analyzing the input signals and if having a high logic level, the synchronization unit 50 outputs a DPM signal onwards (read this process as comparing and synchronizing). As for directly receiving from the first data and second data driving portions (to the comparison/synchronization circuit), please note the combination below ),
wherein in a lock state of the synchronous lock signal, the timing control portion transmits image data to the first data driving portion and the second data driving portion, and the first data driving portion and the second data driving portion output respective data voltages ( [0077], [0081] discloses in response to the DPM signal from the synchronization unit 50, the power module 60 supplies VDD and HVDD to the source drives. [0081] discloses the generating of gamma voltages GMA to provide data voltages to the data lines ); but
Yang does not explicitly teach of the comparison circuit receiving “directly” from the first and second data driving portion”.
To clarify, Yang teaches of the timing controller 20 which outputs the preamble signals to the data drivers and receives the LOCK_UP and LOCK_DN signals from the data drivers, and the comparison circuit does not directly receive these signals from the data drivers; rather it receives LOCK_UP and LOCK_DN from the timing controller. However, Yang teaches in [0073] and [0075] that the timing controller merely relays these two signals to the synchronization unit 50 to perform the comparison steps. It is simply a design choice for the layout of parts.
To emphasize, in the same field of endeavor, display systems, Hong teaches of a locking check process on source drive ICs, ( Hong, Figures 23-24, [0149] ), similar in nature to Yang. Furthermore, Yang teaches in Figure 23 and 24 of using comparators 231 and 241 which can compare the first and second feedback lock signals, received from PCB1 and PCB2 (each comprising source drive ICs). These comparators directly receive the lock signals from the source drive ICs. To expand on the design choice argument, Hong teaches in Figure 2 of the akin feedback lock checks LCS1 and LCS2 being directly received by the timing controller from the source drive ICs and the comparison is done at the timing controller itself. In the various embodiments, there is a different layout of elements and specifically, Figures 23 and 24 teach of the comparator directly receiving the lock signals. As combined with Yang, who again, teaches of a synchronization unit (akin to the comparator), this can be relayed the lock signals instead of the timing controller. Again, as mentioned above, the timing controller of Yang simply relays the lock signals to the synchronization unit anyway.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the comparator directly to the source drive ICs, as taught by Hong, with the motivation that it is a design choice to do so in light of Hong’s own Figure 2 (versus Figures 23 and 24) which show alternate designs as well as the comparators can reduce the time required to perform the locking check process, ( Hong, [0149] ).
Yang teaches in Claim 2:
The display apparatus of claim 1, wherein during a section when lock states of the output first and second lock signals are asynchronized with each other, the synchronous lock signal has an unlock state, and wherein in the unlock state of the synchronous lock signal, the timing control portion turns off transmission of the image data, and outputs of the first data driving portion and the second data driving portion are turned off. ( [0079]-[0080] disclose details on the DPM signal. If the data drivers are not ready/stabilized, etc, there is NO generation of VDD and HVDD, which reduces or prevents the drivers 31 and 32 from supplying a data voltage, i.e. the portions are turned off )
Yang teaches in Claim 3:
The display apparatus of claim 1, wherein during a section when at least one of the output first and second lock signals is in a lock failure state, the synchronous lock signal has an unlock state, and wherein in the unlock state of the synchronous lock signal, the timing control portion turns off transmission of the image data, and outputs of the first data driving portion and the second data driving portion are turned off. ( [0079]-[0080] disclose details on the DPM signal. If the data drivers are not ready/stabilized, etc (read as a lock failure state), there is NO generation of VDD and HVDD, which reduces or prevents the drivers 31 and 32 from supplying a data voltage, i.e. the portions are turned off )
Yang teaches in Claim 4:
The display apparatus of claim 2, wherein in the section when the lock states of the output first and second lock signals are asynchronized with each other, one of the output first and second lock signals is in the lock state and another of the output first and second lock signals is in an unlock state. ( Figure 1, [0041] discloses a synchronization unit 50 which receives LOCK_UP and LOCK_DN from drivers 31 and 32, respectively. [0075]-[0076] discloses analyzing the input signals and if having a high logic level, the synchronization unit 50 outputs a DPM signal onwards. However, if one does not have a high logic level, then the DPM signal is not sent, i.e. unlock state as at least one of the drivers is not ready )
Yang teaches in Claim 5:
The display apparatus of claim 3, wherein the at least one of the output first and second lock signals has an abnormal waveform in the lock failure state. ( [0079]-[0080] discloses a high logic level for the DPM signal to be generated, so if not a high logic level, then the DPM signal is not generated (read as an abnormal waveform and in this case, not a high logic level) )
Yang teaches in Claim 6:
The display apparatus of claim 1, wherein when the input first lock signal is input, the plurality of first data ICs operate sequentially to output corresponding lock signals, and the lock signal output from one of the plurality of first data ICs is input to its next first data IC from the plurality of first data ICs, and the lock signal output from a last first data IC of the plurality of first data ICs is the output first lock signal ( Figure 1, [0044] shows each SIC communicates with the next one and communicates a high logic level to the next one, such as from SIC#1 to SIC#2. SIC#4 generates the LOCK_UP signal to be sent to the timing controller 20 ), and
when the input second lock signal is input, the plurality of second data ICs operate sequentially to output corresponding lock signals, and the lock signal output from one of the plurality of second data ICs is input to its next second data IC from the plurality of second data ICs, and the lock signal output from a last second data IC of the plurality of second data ICs is the output second lock signal. ( Figure 1, [0045] shows each SIC communicates with the next one and communicates a high logic level to the next one, such as from SIC#5 to SIC#6. SIC#8 generates the LOCK_DN signal to be sent to the timing controller 20 )
Yang teaches in Claim 7:
The display apparatus of claim 6, wherein the first data driving portion includes a first source board to which the plurality of first data ICs are connected, wherein the second data driving portion includes a second source board to which the plurality of second data ICs are connected ( Figure 2, [0051] discloses a source drive IC SIC (read SIC as a source board) and there are clearly a plurality of these SICs, which make up each data driver 31 and 32 ),
wherein the first source board includes a first lock signal line that transmits the lock signals inputted and outputted to the plurality of first data ICs ( Figures 1 and 4, [0056] shows the clock training pattern signal (or preamble) which is input to the plurality of SICs in data driver 31 ), and
wherein the second source board includes a second lock signal line that transmits the lock signals inputted and outputted to the plurality of second data ICs. ( Figures 1 and 4, [0056] shows the clock training pattern signal (or preamble) which is input to the plurality of SICs in data driver 32 )
Yang teaches in Claim 8:
The display apparatus of claim 1, wherein one of the plurality of pixels includes a light emitting diode. ( [0033] discloses an organic light emitting diode display (OLED) in addition to the shown embodiment of an LCD. Respectfully, examiner interprets this as an express teaching )
Yang teaches in Claim 9:
The display apparatus of claim 1, wherein in the lock state of the synchronous lock signal, outputs of the data voltages of the first data driving portion and the second data driving portion are synchronized. ( Figure 1, [0053] discloses the synchronization unit 50 analyzes the LOCK_UP and LOCK_DN signals and if they are both of a high logic level, i.e. synchronized, then a DPM signal is generated to the power IC 60 )
Yang teaches in Claim 10:
A display apparatus ( [0003] disclose a display device ), comprising:
a display panel including a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines ( Figure 1, [0035] discloses a display panel 10 with a plurality of data lines DL and cells disposed in a matrix (read as a plurality of pixels) );
a first data driving portion including a plurality of first data integrated circuits (ICs) connected to one ends of the plurality of data lines ( Figure 1, [0034] disclose a first set of data drivers 31 comprising source drive ICs, connected to one end of data lines DL );
a second data driving portion including a plurality of second data ICs connected to other ends of the plurality of data lines ( Figure 1, [0034] disclose a second set of data drivers 32 comprising source drive ICs, connected to the other end of data lines DL );
a timing control portion providing input first and second lock signals to the first data driving portion and the second data driving portion, respectively ( Figure 1, [0039] discloses a timing controller 20 which can output a plurality of signals, including a clock training pattern signal or preamble signal (read as lock signals) to both the first and second set of drivers 31 and 32. Please see [0056] for more details as well ); and
a comparison circuit receiving an output first lock signal, which is generated by the first data driving portion according to the input first lock signal, [directly] from the first data driving portion, and receiving an output second lock signal, which is generated by the second data driving portion according to the input second lock signal, [directly] form the second data driving portion, the comparison circuit comparing and synchronizing the output first and second lock signals to generate a synchronous lock signal, the comparison circuit providing the synchronous lock signal to the timing control portion ( Figure 1, [0041] discloses a synchronization unit 50 (read as a comparison unit) which receives LOCK_UP and LOCK_DN from drivers 31 and 32, respectively. Figure 1 shows the input preamble signals to 31 and 32 and the output LOCK_UP and LOCK_DN signals from 31 and 32. [0075]-[0076] discloses analyzing the input signals and if having a high logic level, the synchronization unit 50 outputs a DPM signal onwards (read this process as comparing and synchronizing). As for directly receiving from the first data and second data driving portions (to the comparison/synchronization circuit), please note the combination below ),
wherein outputs of data voltages of the first data driving portion and the second data driving portion are adjusted according to the synchronous lock signal ( [0077], [0081] discloses in response to the DPM signal from the synchronization unit 50, the power module 60 supplies VDD and HVDD to the source drives. [0081] discloses the generating of gamma voltages GMA to provide data voltages to the data lines ); but
Yang does not explicitly teach of the comparison circuit receiving “directly” from the first and second data driving portion”.
To clarify, Yang teaches of the timing controller 20 which outputs the preamble signals to the data drivers and receives the LOCK_UP and LOCK_DN signals from the data drivers, and the comparison circuit does not directly receive these signals from the data drivers; rather it receives LOCK_UP and LOCK_DN from the timing controller. However, Yang teaches in [0073] and [0075] that the timing controller merely relays these two signals to the synchronization unit 50 to perform the comparison steps. It is simply a design choice for the layout of parts.
To emphasize, in the same field of endeavor, display systems, Hong teaches of a locking check process on source drive ICs, ( Hong, Figures 23-24, [0149] ), similar in nature to Yang. Furthermore, Yang teaches in Figure 23 and 24 of using comparators 231 and 241 which can compare the first and second feedback lock signals, received from PCB1 and PCB2 (each comprising source drive ICs). These comparators directly receive the lock signals from the source drive ICs. To expand on the design choice argument, Hong teaches in Figure 2 of the akin feedback lock checks LCS1 and LCS2 being directly received by the timing controller from the source drive ICs and the comparison is done at the timing controller itself. In the various embodiments, there is a different layout of elements and specifically, Figures 23 and 24 teach of the comparator directly receiving the lock signals. As combined with Yang, who again, teaches of a synchronization unit (akin to the comparator), this can be relayed the lock signals instead of the timing controller. Again, as mentioned above, the timing controller of Yang simply relays the lock signals to the synchronization unit anyway.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the comparator directly to the source drive ICs, as taught by Hong, with the motivation that it is a design choice to do so in light of Hong’s own Figure 2 (versus Figures 23 and 24) which show alternate designs as well as the comparators can reduce the time required to perform the locking check process, ( Hong, [0149] ).
Yang teaches in Claim 11:
The display apparatus of claim 10, wherein in a lock state of the synchronous lock signal, the outputs of the data voltages of the first data driving portion and the second data driving portion are synchronized. ( Figure 1, [0053] discloses the synchronization unit 50 analyzes the LOCK_UP and LOCK_DN signals and if they are both of a high logic level, i.e. synchronized, then a DPM signal is generated to the power IC 60 )
Yang teaches in Claim 12:
The display apparatus of claim 10, wherein during a section when lock states of the output first and second lock signals are asynchronized with each other, the synchronous lock signal has an unlock state, and wherein in the unlock state of the synchronous lock signal, the outputs of the first data driving portion and the second data driving portion are turned off. ( [0079]-[0080] disclose details on the DPM signal. If the data drivers are not ready/stabilized, etc, there is NO generation of VDD and HVDD, which reduces or prevents the drivers 31 and 32 from supplying a data voltage, i.e. the portions are turned off )
Yang teaches in Claim 13:
The display apparatus of claim 10, wherein during a section when at least one of the output first and second lock signals is in a lock failure state, the synchronous lock signal has an unlock state, and wherein in the unlock state of the synchronous lock signal, the outputs of the first data driving portion and the second data driving portion are turned off. ( [0079]-[0080] disclose details on the DPM signal. If the data drivers are not ready/stabilized, etc (read as a lock failure state), there is NO generation of VDD and HVDD, which reduces or prevents the drivers 31 and 32 from supplying a data voltage, i.e. the portions are turned off )
Yang teaches in Claim 14:
The display apparatus of claim 12, wherein in the section when the lock states of the output first and second lock signals are asynchronized with each other, one of the output first and second lock signals is in the lock state and another of the output first and second lock signals is in an unlock state. ( Figure 1, [0041] discloses a synchronization unit 50 which receives LOCK_UP and LOCK_DN from drivers 31 and 32, respectively. [0075]-[0076] discloses analyzing the input signals and if having a high logic level, the synchronization unit 50 outputs a DPM signal onwards. However, if one does not have a high logic level, then the DPM signal is not sent, i.e. unlock state as at least one of the drivers is not ready )
Yang teaches in Claim 15:
The display apparatus of claim 13, wherein the at least one of the output first and second lock signals has an abnormal waveform in the lock failure state. ( [0079]-[0080] discloses a high logic level for the DPM signal to be generated, so if not a high logic level, then the DPM signal is not generated (read as an abnormal waveform and in this case, not a high logic level) )
Yang teaches in Claim 16:
The display apparatus of claim 10, wherein the first data driving portion includes a first source board to which the plurality of first data ICs are connected, wherein the second data driving portion includes a second source board to which the plurality of second data ICs are connected ( Figure 2, [0051] discloses a source drive IC SIC (read SIC as a source board) and there are clearly a plurality of these SICs, which make up each data driver 31 and 32 ),
wherein the first source board includes a first lock signal line that transmits the lock signals inputted and outputted to the plurality of first data ICs ( Figures 1 and 4, [0056] shows the clock training pattern signal (or preamble) which is input to the plurality of SICs in data driver 31 ), and
wherein the second source board includes a second lock signal line that transmits the lock signals inputted and outputted to the plurality of second data ICs. ( Figures 1 and 4, [0056] shows the clock training pattern signal (or preamble) which is input to the plurality of SICs in data driver 32 )
Yang teaches in Claim 17:
The display apparatus of claim 10, wherein one of the plurality of pixels includes a light emitting diode. ( [0033] discloses an organic light emitting diode display (OLED) in addition to the shown embodiment of an LCD. Respectfully, examiner interprets this as an express teaching )
Yang teaches in Claim 18:
The display apparatus of claim 10, wherein the data voltages output from the first data driving portion and the second data driving portion are equal to each other. ( Claim 18, detailed on Column 6, notes the analog video voltage is transmitted to a same data voltage, of which both ICs on top and bottom are connected to. Furthermore, the same VDD/HVDD are transmitted to both the top and bottom parts, meaning the data voltages are equal )
Yang teaches in Claim 19:
The display apparatus of claim 1, wherein during a section when lock states of the output first and second lock signals are asynchronized with each other or during a section when at least one of the output first and second lock signals is in a lock failure state, a power supply portion supplies a source driving voltage to the first data driving portion and the second data driving portion. ( Please note the alternative claim language. [0082] discloses an operational failure can be addressed by the power module after each set of data drivers are analyzed. Respectfully, based on the LOCK_UP and LOCK_DOWN signals, the synchronization unit 50 can make adjusts to the power management IC 60, including aspects to deal with failure. Furthermore, PWM IC outputs VDD/HVDD, as detailed in [0081], to the drivers 31 and 32, as shown in Figure 1 )
Yang teaches in Claim 20:
The display apparatus of claim 10, wherein during a section when lock states of the output first and second lock signals are asynchronized with each other or during a section when at least one of the output first and second lock signals is in a lock failure state, a power supply portion supplies a source driving voltage to the first data driving portion and the second data driving portion. ( Please note the alternative claim language. [0082] discloses an operational failure can be addressed by the power module after each set of data drivers are analyzed. Respectfully, based on the LOCK_UP and LOCK_DOWN signals, the synchronization unit 50 can make adjusts to the power management IC 60, including aspects to deal with failure. Furthermore, PWM IC outputs VDD/HVDD, as detailed in [0081], to the drivers 31 and 32, as shown in Figure 1 )
Response to Arguments
6. Applicant’s arguments considered, but are respectfully moot in view of new grounds of rejection(s).
Please note the claim amendments and in response, a newly cited reference, Hong, has been cited. As a result, Applicant’s arguments are moot at this time.
Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621