Prosecution Insights
Last updated: August 18, 2026
Application No. 19/001,950

LOAD POWER BASED DC-DC CONVERTER

Non-Final OA §103
Filed
Dec 26, 2024
Priority
Feb 16, 2024 — RE 10-2024-0022651
Examiner
FINCH III, FRED E
Art Unit
Tech Center
Assignee
Korea Electronics Technology Institute
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
736 granted / 917 resolved
+20.3% vs TC avg
Strong +18% interview lift
Without
With
+17.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
38 currently pending
Career history
946
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
47.0%
+7.0% vs TC avg
§102
28.2%
-11.8% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 917 resolved cases

Office Action

§103
DETAILED ACTION This Office action is in response to the application filed on 26 December 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 16 February 2024. It is noted, however, that applicant has not filed a certified copy of the KR10-2024-0022651 application as required by 37 CFR 1.55. Applicant requested in the Application Data Sheet (ADS) that the certified copy be retrieved through the Priority Document Exchange (PDX), however a notice was issued on 16 July 2025 that such retrieval was unsuccessful. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Implementation of High-Efficiency Battery Charger with a Zero-Voltage-Transition Pulse-Width-Modulated Boost Converter” by Ke et al. (hereinafter “Ke”) in view of JP 2010-124612 to DAIHEN CORP1 (hereinafter “Daihen”). In re claim 1, Ke discloses a load power based DC-DC converter (Fig. 3), comprising: an input circuit (Lf, S) connected to an input terminal (terminal of power source Vin) and including a main switch (S); a resonant circuit (Cr, Lr, S1, D1) connected to the input circuit and including an auxiliary switch (S1) configured to perform zero-voltage switching on the main switch (see Abstract and paragraph directly above Fig. 3); an output circuit (D, Cf) connected to the resonant circuit and configured to output a voltage to an output terminal (Vo); and a controller configured to control the main switch and the auxiliary switch (Triggering signal controller). Ke does not disclose the controller being further configured to: calculate a load power, which is power output through the output terminal, and control the auxiliary switch so that on duty of the auxiliary switch increases or decreases based on the load power. Whereas Daihen discloses a a DC-DC converter (Fig. 1) with an auxiliary resonant ZVT circuit (Lrs1, Lrs2, Crs, Qs) and a controller (15) that is configured to calculate load/outpout power of the converter and control the auxiliary switch so that on duty of the auxiliary switch increases or decreases based on the load/output power (see [0006]: “the gist of the invention is that the control circuit calculates the ... output power of the power conversion device and adjusts the on period length of the auxiliary switch based on the calculated ... output power”). This is done to reduce the switching losses of both the auxiliary and main switches while also optimizing the commutation of the resonant current to improve efficiency and suppress surge voltages on the main switch ([0007]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have configured the controller of Ke to calculate a load power, which is power output through the output terminal and control the auxiliary switch so that on duty of the auxiliary switch increases or decreases based on the load power as taught by Daihen for the purpose of reducing switching losses, increasing efficiency and suppressing surge voltages. In re claim 2, Ke as modified discloses (Ke, Fig. 3) wherein the resonant circuit includes: a resonant capacitor (Cr) connected in parallel with the main switch (Cr is in parallel with main switch S); a resonant inductor (Lr) comprising a first terminal connected to the resonant capacitor (upper terminal of Lr is connected to Cr); and an auxiliary diode (D1) comprising an anode connected to a second terminal of the resonant inductor (anode of D1 is connected to lower terminal of Lr) and a cathode connected to the output circuit (cathod of D1 is connected to D and Cf of the output circuit), and a first terminal of the auxiliary switch (S1) connected to the second terminal of the resonant inductor (drain of S1 is connected to lower terminal of Lr), and a second terminal of the auxiliary switch connected to the other terminal of the resonant capacitor (source of S1 is connected to lower terminal of Cr) In re claim 3, the combination of Ke and Daihen necessarily further provides that the controller is configured to: control the auxiliary switch so that the on duty of the auxiliary switch increases in response to the load power increasing (see Daihen, Fig. 6 and [0043]: on-time or on duty of aux switch Qs increases with increasing output power up to around 1.7-1.8 kW), and control the auxiliary switch so that the on duty of the auxiliary switch decreases in response to the load power decreasing (id.: vice versa, as the output power decreases from 1.7-1.8 kW down to a minimum, so does the on-time or on duty of Qs). In re claim 4, the combination of Ke and Daihen necessarily further provides that the controller includes a load power based lookup table which is a lookup table in which the on duty of the auxiliary switch is stored for each predetermined margin of the load power (see Daihen, [0043]: the control circuit 15 uses a table of calculations to set the on-time or on duty of Qs according to the calculated output power at any given time), and wherein the controller is configured to control the auxiliary switch with the on duty of the auxiliary switch stored in the load-based lookup table in response to the load power varying (id.). In re claim 5, Ke as modified discloses (Ke, Fig. 3) wherein the output circuit further includes: a main diode (D) comprising an anode connected to the second terminal of the resonant inductor (anode of D is connected to lower terminal of Lr through the inductor Lr itself; it is noted that this is the apparent interpretation of the claim limitation based on Applicant’s disclosure, see Figs. 1 and 3) and a cathode connected to the cathode of the auxiliary diode (cathode of D is connected to cathode of D1); and a DC capacitor (Cf) comprising a first terminal connected to the cathode of the main diode (upper terminal of Cf is connected to cathode of D) and a second terminal connected to a negative electrode of the output terminal (lower terminal of Cf is connected to negative electrode of output terminal/load). In re claim 6, neither Ke nor Daihen explicitly disclose wherein, in response to the load power being PLoad, a voltage of the output terminal being Vout, and a current of the output terminal being Iout, the load power is configured to be calculated according to the following Equation 1: Equation 1 PLoad=Vout∙Iout. However, it is basic knowledge in the art that electric power is defined as the product of a voltage drop across a component (load) and the current flowing through said component (load), or in other words P=V*I. As such, it would have been an obvious matter of common sense for the person of ordinary skill in the art, before the effective filing date of the claimed invention, to have configured the controller to calculate the load power PLoad according to the Equation 1 PLoad=Vout∙Iout, as this would be the simplest manner of making such calculation for the purpose of adjusting the on-time or on duty of the auxiliary switch. In re claim 7, Ke as modified discloses (Ke, Fig. 3) wherein the input circuit includes a first inductor (Lf) comprising a first terminal connected to a positive electrode of the input terminal (left side terminal of Lf connected to positive electrode of Vin) and a second terminal connected to a first terminal of the main switch (right side terminal of Lf connected to upper terminal of S), and wherein a second terminal of the main switch is connected to a negative electrode of the input terminal (source of S connected to negative electrode of Vin). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2008/0278130 discloses a RESONANCE TYPE ELECTRIC POWER CONVERSION APPARATUS AND METHOD in which the on-time of an auxiliary resonant switch is adjusted based on factors including output current. US 2010/0246231 discloses a process for ACHIEVING ZVS IN A TWO QUADRANT CONVERTER USING A SIMPLIFIED AUXILIARY CIRCUIT in which on-time of auxiliary switches are adjusted based on load current. US 2018/0019676 discloses a power converter with auxiliary ZVR circuit having a topology similar to that disclosed by Applicant. The NPL IEEE article by Park et al. discloses a boost converter with auxiliary resonant ZVT circuit having a topology similar to that disclosed by Applicant. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRED E FINCH III/Primary Examiner, Art Unit 2838 1 An English machine translation of the Daihen document is being furnished with this Office action.
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Prosecution Timeline

Dec 26, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
98%
With Interview (+17.9%)
2y 5m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 917 resolved cases by this examiner. Grant probability derived from career allowance rate.

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