Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 12/26/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Appropriate correction is required.
Claim Objections
Claims 4 and 6 are objected to because of the following informalities: Regarding Claim 4, in line 25, “a first high potential terminal” appears that it should read as “a first high-potential terminal”;in line 34, “a second high potential terminal” appears that it should read as “a second high-potential terminal”. Regarding Claim 6, all instances of “n-well” should read as “N-well”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jang et al. (US Patent Application Publication US 2023/0085770 A1, hereinafter “Jang”) Regarding claim 1, Jang discloses (see Fig. 3) a semiconductor device (door driver 210, which is a half-bridge integrated circuit, see [0039]) configured to be controlled by a control unit (door controller 206), the semiconductor device comprising: an upper arm switching element (high-side switch 358); a lower arm switching element (low-side switch 360) serially connected to the upper arm switching element (high-side switch 358 and low-side switch 360 are connected in series, with their common node coupled to OUT pin 334; see Fig. 3); an upper arm control circuit (digital logic 340 and gate driver HS 354) that executes drive control on the upper arm switching element based on an upper arm drive signal received from the control unit (digital logic 340 controls gate driver HS 354 to drive high-side switch 358 in accordance with the signal received at IN pin 326 from door controller 206, which defines whether the high-side switch or the low-side switch is activated; see [0039]); an overvoltage detection circuit (door driver 210 is configured to detect a back EMF voltage, see [0040], by way of back EMF protection circuit 208 comprising comparator 322 and reference voltage VREF 310, see [0042]) that detects an overvoltage state of the upper arm control circuit (comparator 322 detects when a back EMF voltage present on the VBATT node, to which high-side switch 358 and gate driver HS 354 are referenced via VS pin 332, exceeds an overvoltage threshold; see [0039] and [0042]) and outputs an overvoltage detection signal (VTR 309 applied to INH pin 328, see [0042]); and a lower arm control circuit (digital logic 340 and gate driver LS 356) that executes drive control on the lower arm switching element, based on a lower arm drive signal received from the control unit (the signal received at IN pin 326 from door controller 206) or based on the overvoltage detection signal (in response to the overvoltage detection signal enabling door driver 210 via INH pin 328, digital logic 340 controls gate driver LS 356 to turn on low-side switch 360, thereby shorting the back EMF voltage to ground; see [0040] and [0042]).
Allowable Subject Matter
Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the overvoltage detection circuit detects the overvoltage state of the upper arm control circuit based on a leakage current that flows from a floating potential of the upper arm control circuit to a ground potential”, in combination with the remaining limitations of the claim. Claims 3-7 are objected due to their dependency on claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 7,671,638 B2 discloses a high-side driver that senses parasitic conduction current between an N-type epitaxial region and the substrate of the floating high-side region and provides a signal to the control circuit. US 6,597,550 B2 discloses a high voltage integrated circuit having a leakage current path between a high-voltage region and a P-type substrate.
US 2004/0120090 A1 discloses a half-bridge high voltage gate driver transistor overvoltage protection circuit. US 2024/0195287 A1 discloses an overvoltage protection mechanism for a power converter. US 11,152,857 B2 discloses a gate driver circuit for half bridge switches having overvoltage protection. US 10,236,874 B2 discloses an overvoltage protection circuit for a power semiconductor. US 6,987,378 B1 discloses an overvoltage protection circuit for a power semiconductor bridge.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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