DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masuda (JP 2010-124103 A).
Claim 1: Masuda discloses a circuit apparatus (Fig.1) comprising:
a first oscillation circuit (the oscillation circuit providing Fin, not shown but required for providing a clock signal) configured to generate a first clock signal (Fin);
a PLL circuit (1) including a second oscillation circuit (12) configured to generate a second clock signal (Fo) and a frequency control voltage generation circuit (11) configured to generate a frequency control voltage (Fvco/Vd1; see pg.8 of the attached machine translation) for controlling a frequency of the second clock signal (provided to VCO 12), the PLL circuit being configured to synchronize a phase of the second clock signal with a phase of the first clock signal (via the phase locked loop formed by 11 including phase detector 11a; see pg.2, 1st-3rd paragraphs); and
a failure detection circuit (14/151, shown in Fig.2) configured to monitor the frequency control voltage (shown in Fig.2) and detect whether there is a possibility that the frequency control voltage deviates from a predetermined voltage range in which the second oscillation circuit is capable of operating normally (when the oscillator is in an abnormal condition in which the control voltage is not between the normal operating range Vin1-Vin2, the abnormal state detection circuit provides Sod1 output; see pg.9, 3rd paragraph).
Claim 8: Masuda discloses an oscillator (e.g. Fig.1) comprising the circuit apparatus according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Masuda in view of Chern et al. (US 2013/0082754, hereinafter “Chern”).
Masuda discloses the limitations of claim 1, but does not disclose wherein the second oscillation circuit is coupled to a resonator and causes the resonator to oscillate to generate the second clock signal. Chern discloses that in a similar PLL with a lock detector (Fig.1), the corresponding VCO may be an LCVCO (112; see [0010]), thus being coupled to a resonator (an LC resonator) that causes the resonator to oscillate (according to 1/(2*pi*sqrt(LC); see also Fig.3). One known benefit of an LC VCO over a ring oscillator design is improved phase noise characteristics. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have provided an LC oscillator, as disclosed by Chern, as the VCO of Masuda, thus including a resonator in the form of an LC resonator, in order to have provided a VCO with improved phase noise characteristics.
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose within the context of the claims “based on an A/D conversion result of the frequency control voltage and an A/D conversion result of the temperature detection voltage, frequency control voltage data obtained by removing a voltage component that changes according to a temperature from the frequency control voltage, and predicts, based on the frequency control voltage data, a timing when the frequency control voltage deviates from the predetermined voltage range” of claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hamaguchi (JP 2006-180349 A), Bhagwan (US 5,864,572), and Seo (US 2023/0268883) disclose similar clock abnormality detection circuits.
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/RYAN JOHNSON/Primary Examiner, Art Unit 2849