CTNF 19/002,373 CTNF 91266 DETAILED ACTION This action is responsive to the following communications: the Application filed December 26, 2024, and Information Disclosure Statement filed on December 26, 2024. Claims 1-20 are pending. Claims 1 and 13 are independent. Information Disclosure Statement Acknowledged is made of Application’s Information Disclosure Statement (IDS) Form PTO-1449 filed on December 26, 2024. This IDS has been considered. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-3 and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 11,543,977 . Although the claims at issue are not identical, they are not patentably distinct from each other because, they claim the same coverage of invention by providing a seed generator circuit . Regarding independent claim 1, claim 12 of recited patent discloses the limitation of claim 1. A memory system comprising: a nonvolatile memory; a controller configured to store data into the nonvolatile memory; a seed generator circuit configured to: generate first random number sequence data by performing a first XorShift operation on inputted data; generate a seed by using the first random number sequence data, and a random number generator circuit configured to generate second random number sequence data by performing a second XorShift operation on the seed. Regarding claim 2, claim 12 of recited patent discloses the limitation of claim 2. The memory system according to claim 1, wherein the seed generator circuit includes a plurality of XorShift circuits, and a nonlinear transformation circuit configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits, and the first random number sequence data are generated by using the plurality of XorShift circuits and a nonlinear transformation circuit. Regarding claim 3, claim 12 of recited patent discloses the limitation of claim 3. The memory system according to claim 2, wherein the plurality of XorShift circuits include a first XorShift circuit and a second XorShift circuit, the first XorShift circuit is configured to perform the first XorShift operation on the inputted data, and the second XorShift circuit is configured to perform processing on output data from both the first XorShift circuit and the nonlinear transformation circuit to generate the seed. Regarding independent claim 13, claim 12 of recited disclose the limitation of claim 13. A memory system comprising: a nonvolatile memory; a memory controller configured to control storing of data into the nonvolatile memory; a seed generator circuit configured to: generate first random number sequence data by performing a first XorShift operation on storage location data indicating a storage location of the data in the nonvolatile memory; and generate a seed by using the first random number sequence data; and a random number generator circuit configured to generate second random number sequence data by performing a second XorShift operation on the seed . 08-36 AIA Claim s 4-12 and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-15 of U.S. Patent No. 11,543,977 in view of U.S Patent No. 11,875,041 Regarding claim 4, claim 12 of recited patent disclose the limitation of claim 2. However, Patent “977” is silent with respect to The memory system according to claim 2, wherein the random number generator circuit is configured to perform an XOR operation on an operation result of the second XorShift operation to generate the second random number sequence data. Claim 4 of Patent ‘041 discloses the limitation of claim 4. The memory system according to claim 2, wherein the random number generator circuit is configured to perform an XOR operation on an operation result of the second XorShift operation to generate the second random number sequence data. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 5, claim 12 of recited patent ‘977 discloses the limitation of claim 2. However, Patent ‘977 is silent with respect to The memory system according to claim 2, wherein the random number generator circuit is configured to: perform an XOR operation on an operation result from the second XorShift circuit; and perform the second XorShift operation on an operation result of the XOR operation to generate the second random number sequence data. Claim 5 of Patent ‘041 discloses the limitation of claim 5. The memory system according to claim 2, wherein the random number generator circuit is configured to: perform an XOR operation on an operation result from the second XorShift circuit; and perform the second XorShift operation on an operation result of the XOR operation to generate the second random number sequence data. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 6, claim 12 of recited patent ‘977 discloses the limitation of claim 2. However, Patent ‘977 is silent with respect to The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a nonlinear transformation of a same kind. Claim 6 of Patent ‘041 discloses the limitation of claim 6. The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a nonlinear transformation of a same kind. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 7, claim 12 of recited patent ‘977 discloses the limitation of claim 2. However, Patent ‘977 is silent with respect to The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a plurality of kinds of different nonlinear transformations. Claim 7 of patent ‘041 discloses the limitation of claim 7. The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a plurality of kinds of different nonlinear transformations. Regarding claim 8, claim 7 of patent ‘041 discloses the limitation of claim . Claim 8 of patent ‘041 further disclose limitation of claim 8 .The memory system according to claim 7, wherein the plurality of S-box circuits include at least two S-box circuits configured to output different numbers of bits. Regarding claim 9, claim 12 of recited patent ‘977 discloses the limitation of claim 1. However, Patent ‘977 is silent with respect to The memory system according to claim 1, further comprising an exchange circuit configured to exchange data positions in the second random number sequence data. Claim 9 of Patent ‘041 discloses the limitation of claim 9. The memory system according to claim 1, further comprising an exchange circuit configured to exchange data positions in the second random number sequence data. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 10, claim 12 of recited patent ‘977 discloses the limitation of claim 1. However, Patent ‘977 is silent with respect to The memory system according to claim 1, wherein the random number generator circuit includes an inversion circuit configured to perform bit inversion, byte inversion, or word inversion before or after performing the second XorShift operation. Claim 10 of Patent ‘041 discloses the limitation of claim 10. The memory system according to claim 1, wherein the random number generator circuit includes an inversion circuit configured to perform bit inversion, byte inversion, or word inversion before or after performing the second XorShift operation. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 11, claim 12 of recited patent ‘977 discloses the limitation of claim 1. However, Patent ‘977 is silent with The memory system according to claim 1, further comprising a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein: the first XorShift circuit includes a first input and a first output; the second XorShift circuit includes a second input and a second output; the first input is connected to an output of the first S-box circuit, and the first output is connected to an input the second S-box circuit; and the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit. Claim 11 of Patent ‘041 discloses the limitation of claim 11. The memory system according to claim 1, further comprising a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein: the first XorShift circuit includes a first input and a first output; the second XorShift circuit includes a second input and a second output; the first input is connected to an output of the first S-box circuit, and the first output is connected to an input the second S-box circuit; and the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit. Regarding claim 12, claim 12 of recited patent ‘977 discloses the limitation of claim 1. However, Patent ‘977 is silent with respect to The memory system according to claim 1, further comprising a plurality of units, each of which includes a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein in each of the plurality of units, the first XorShift circuit includes a first input and a first output, and the second XorShift circuit includes a second input and a second output, the first input is connected to an output of the first S-box circuit, and the first output is connected to an input of the second S-box circuit, the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit, and a bit shift amount used in the first and second XorShift circuits of each of the plurality of units differs among the plurality of units. Claim 12 of Patent ‘041 discloses the limitation of claim 12. The memory system according to claim 1, further comprising a plurality of units, each of which includes a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein in each of the plurality of units, the first XorShift circuit includes a first input and a first output, and the second XorShift circuit includes a second input and a second output, the first input is connected to an output of the first S-box circuit, and the first output is connected to an input of the second S-box circuit, the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit, and a bit shift amount used in the first and second XorShift circuits of each of the plurality of units differs among the plurality of units. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 14, claim 12 of recited patent disclose the limitation of claim 13. However, Patent ‘977 is silent with respect to The memory system according to claim 13, wherein the memory controller is configured to store the data at the storage location in the nonvolatile memory designated by a page number, and the storage location data contains the page number, or the page number and a frame number contained in the page number. Claim 14 of Patent ‘041 discloses the limitation of claim 14. The memory system according to claim 13, wherein the memory controller is configured to store the data at the storage location in the nonvolatile memory designated by a page number, and the storage location data contains the page number, or the page number and a frame number contained in the page number. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 15, claim 12 of recited patent disclose the limitation of claim 13. However, Patent ‘977 is silent with respect to The memory system according to claim 13, wherein the number generator circuit randomizes user data using the second random number sequence data, and the memory controller stores the randomized user data as the data at the storage location in the nonvolatile memory. Claim 15 of Patent ‘041 discloses the limitation of claim 15. The memory system according to claim 13, wherein the number generator circuit randomizes user data using the second random number sequence data, and the memory controller stores the randomized user data as the data at the storage location in the nonvolatile memory. Since Patent ‘977 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘977. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘977 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 16, claim 12 of recited patent discloses the limitation of claim 13. However, Patent ‘977 is silent with respect to The memory system according to claim 13, wherein the first random number sequence data are generated by using a plurality of XorShift circuits and a nonlinear transformation circuit, and the nonlinear transformation circuit is configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits. Claim 2 of recited patent disclose the limitation of claim 16. The memory system according to claim 13, wherein the first random number sequence data are generated by using a plurality of XorShift circuits and a nonlinear transformation circuit, and the nonlinear transformation circuit is configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits. Regarding claim 17, claim 2 of patent ‘041 disclose the limitation of claim 16. Claim 3 of patent ‘041 further discloses the limitation of claim 17. The memory system according to claim 16, wherein the plurality of XorShift circuits include a first XorShift circuit and a second XorShift circuit, the first XorShift circuit is configured to perform the first XorShift operation on the storage location data, and the second XorShift circuit is configured to perform processing on output data from both the first XorShift circuit and the nonlinear transformation circuit to generate the seed. Regarding claim 18, claim 2 of Patent ‘041 disclose the limitation of claim 16. Claim 6 of Patent ‘041 further discloses the limitation of claim 18.The memory system according to claim 16, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a nonlinear transformation of a same kind. Regarding claim 19, claim 2 of patent ‘041 discloses the limitation of claim 16. Claim 4 of patent ‘041 further disclose the limitation of claim 19.The memory system according to claim 17, wherein the random number generator circuit is configured to perform an XOR operation on an operation result of the second XorShift operation to generate the second random number sequence data. Regarding claim 20, claim 2 of patent ‘041 discloses the limitation of claim 17. Claim 5 of patent ‘041 discloses the limitation of claim 20. The memory system according to claim 17, wherein the random number generator circuit is configured to: perform an XOR operation on an operation result from the second XorShift circuit; and perform the second XorShift operation on an operation result of the XOR operation to generate the second random number sequence data . 08-34 AIA Claim s 1 and 13-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 13, 14 and 16 of U.S. Patent No. 11,875,041 . Although the claims at issue are not identical, they are not patentably distinct from each other because, they claim the same coverage of invention by providing a seed generator circuit . Regarding independent claim 1, claim 13 of recited patent discloses the limitation of claim 1. A memory system comprising: a nonvolatile memory; a controller configured to store data into the nonvolatile memory; a seed generator circuit configured to: generate first random number sequence data by performing a first XorShift operation on inputted data; generate a seed by using the first random number sequence data, and a random number generator circuit configured to generate second random number sequence data by performing a second XorShift operation on the seed. Regarding independent claim 13, claim 13 of recited patent discloses the limitation of claim 13. A memory system comprising: a nonvolatile memory; a memory controller configured to control storing of data into the nonvolatile memory; a seed generator circuit configured to: generate first random number sequence data by performing a first XorShift operation on storage location data indicating a storage location of the data in the nonvolatile memory; and generate a seed by using the first random number sequence data; and a random number generator circuit configured to generate second random number sequence data by performing a second XorShift operation on the seed. Regarding claim 14, claim 14 of recited patent discloses the limitation of claim 14. The memory system according to claim 13, wherein the memory controller is configured to store the data at the storage location in the nonvolatile memory designated by a page number, and the storage location data contains the page number, or the page number and a frame number contained in the page number. Regarding claim 15, claim 16 of recited patent disclose the limitation of claim 15. The memory system according to claim 13, wherein the number generator circuit randomizes user data using the second random number sequence data, and the memory controller stores the randomized user data as the data at the storage location in the nonvolatile memory . 08-36 AIA Claim s 2-12 and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-16 of U.S. Patent No. 11,875,041 in view of U.S Patent No. 11, 543,977 . Regarding claim 2, claim 13 of recited patent discloses the limitation of claim 1. However, Patent ‘041 is silent with respect to the memory system according to claim 1, wherein the seed generator circuit includes a plurality of XorShift circuits, and a nonlinear transformation circuit configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits, and the first random number sequence data are generated by using the plurality of XorShift circuits and a nonlinear transformation circuit. Claim 1 of patent ‘977 discloses the limitation of claim 2. the memory system according to claim 1, wherein the seed generator circuit includes a plurality of XorShift circuits, and a nonlinear transformation circuit configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits, and the first random number sequence data are generated by using the plurality of XorShift circuits and a nonlinear transformation circuit. Since Patent ‘041 and Patent ‘977. are both from the same field of endeavor, the purpose disclosed by Patent ‘977 would have been recognized in the pertinent art of Patent ‘041. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘041 to teaching of Patent ‘977 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 3, claim 1 of patent ‘977 discloses the limitation of claim 2. Claim 2 of patent ‘977 further discloses the limitation of claim 3. The memory system according to claim 2, wherein the plurality of XorShift circuits include a first XorShift circuit and a second XorShift circuit, the first XorShift circuit is configured to perform the first XorShift operation on the inputted data, and the second XorShift circuit is configured to perform processing on output data from both the first XorShift circuit and the nonlinear transformation circuit to generate the seed. Regarding claim 4, claim 1 of patent ‘977 disclose the limitation of claim 2. Claim 4 of patent ‘977 further discloses the limitation of claim 4. The memory system according to claim 2, wherein the random number generator circuit is configured to perform an XOR operation on an operation result of the second XorShift operation to generate the second random number sequence data. Regarding claim 5, claim 1 of patent ‘977 discloses the limitation of claim 2. Claim 5 of patent ‘977 further discloses the limitation of claim 5. The memory system according to claim 2, wherein the random number generator circuit is configured to: perform an XOR operation on an operation result from the second XorShift circuit; and perform the second XorShift operation on an operation result of the XOR operation to generate the second random number sequence data. Regarding claim 6, claim 1 of patent ‘977 discloses the limitation of claim 2. Claim 6 of patent ‘977 discloses the limitation of claim 6. The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a nonlinear transformation of a same kind. Regarding claim 7, claim 1 of patent ‘977 discloses the limitation of claim 2. Claim 7 of patent ‘977 discloses the limitation of claim 7. The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a plurality of kinds of different nonlinear transformations. Regarding claim 8, claim 7 of patent ‘977 discloses the limitation of claim 7. Claim 8 of patent further discloses the limitation of claim 8. The memory system according to claim 7, wherein the plurality of S-box circuits include at least two S-box circuits configured to output different numbers of bits. Regarding claim 9, claim 13 of recited patent ‘041 discloses the limitation of claim 1. However, patent ‘041 is silent with respect to The memory system according to claim 1, further comprising an exchange circuit configured to exchange data positions in the second random number sequence data. Claim 9 of patent ‘977 discloses the limitation of claim 9. The memory system according to claim 1, further comprising an exchange circuit configured to exchange data positions in the second random number sequence data. Since Patent ‘041 and Patent ‘977. are both from the same field of endeavor, the purpose disclosed by Patent ‘977 would have been recognized in the pertinent art of Patent ‘041. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘041 to teaching of Patent ‘977 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 10, claim 13 of recited patent discloses the limitation of claim 1. However, Patent ‘041 is silent with respect to The memory system according to claim 1, wherein the random number generator circuit includes an inversion circuit configured to perform bit inversion, byte inversion, or word inversion before or after performing the second XorShift operation. Claim 10 of patent ‘977 discloses the limitation of claim 10. The memory system according to claim 1, wherein the random number generator circuit includes an inversion circuit configured to perform bit inversion, byte inversion, or word inversion before or after performing the second XorShift operation. Since Patent ‘041 and Patent ‘977. are both from the same field of endeavor, the purpose disclosed by Patent ‘977 would have been recognized in the pertinent art of Patent ‘041. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘041 to teaching of Patent ‘977 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 11, claim 13 of recited patent discloses the limitation of claim 11. However, patent ‘041 is silent with respect to The memory system according to claim 1, further comprising a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein: the first XorShift circuit includes a first input and a first output; the second XorShift circuit includes a second input and a second output; the first input is connected to an output of the first S-box circuit, and the first output is connected to an input the second S-box circuit; and the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit. Claim 11 of patent ‘977 discloses the limitation of claim 11. The memory system according to claim 1, further comprising a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein: the first XorShift circuit includes a first input and a first output; the second XorShift circuit includes a second input and a second output; the first input is connected to an output of the first S-box circuit, and the first output is connected to an input the second S-box circuit; and the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit. Since Patent ‘041 and Patent ‘977. are both from the same field of endeavor, the purpose disclosed by Patent ‘977 would have been recognized in the pertinent art of Patent ‘041. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘041 to teaching of Patent ‘977 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 12, claim 13 of recited patent discloses the limitation of claim 1. However, patent ‘041 is silent with respect to The memory system according to claim 1, further comprising a plurality of units, each of which includes a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein in each of the plurality of units, the first XorShift circuit includes a first input and a first output, and the second XorShift circuit includes a second input and a second output, the first input is connected to an output of the first S-box circuit, and the first output is connected to an input of the second S-box circuit, the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit, and a bit shift amount used in the first and second XorShift circuits of each of the plurality of units differs among the plurality of units. Claim 12 of patent ‘977 discloses the limitation of claim 12. The memory system according to claim 1, further comprising a plurality of units, each of which includes a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein in each of the plurality of units, the first XorShift circuit includes a first input and a first output, and the second XorShift circuit includes a second input and a second output, the first input is connected to an output of the first S-box circuit, and the first output is connected to an input of the second S-box circuit, the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit, and a bit shift amount used in the first and second XorShift circuits of each of the plurality of units differs among the plurality of units. Regarding claim 16, claim 13 of recited patent discloses the limitation of claim 13. However, patent ‘041 is silent with respect to The memory system according to claim 13, wherein the first random number sequence data are generated by using a plurality of XorShift circuits and a nonlinear transformation circuit, and the nonlinear transformation circuit is configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits. Claim 1 of patent ‘977 discloses the limitation of claim 16. The memory system according to claim 13, wherein the first random number sequence data are generated by using a plurality of XorShift circuits and a nonlinear transformation circuit, and the nonlinear transformation circuit is configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits. Since Patent ‘041 and Patent ‘977. are both from the same field of endeavor, the purpose disclosed by Patent ‘977 would have been recognized in the pertinent art of Patent ‘041. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘041 to teaching of Patent ‘977 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 17, claim 1 of patent ‘977 disclose the limitation of claim 17. Claim 2 of patent ‘977 further disclose the limitation of claim 17.The memory system according to claim 16, wherein the plurality of XorShift circuits include a first XorShift circuit and a second XorShift circuit, the first XorShift circuit is configured to perform the first XorShift operation on the storage location data, and the second XorShift circuit is configured to perform processing on output data from both the first XorShift circuit and the nonlinear transformation circuit to generate the seed. Regarding claim 18, claim 1 of patent ‘977 discloses the limitation of claim 18. Claim 5 of patent ‘977 further discloses the limitation of claim 18. The memory system according to claim 16, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a nonlinear transformation of a same kind. Regarding claim 19, claim 2 of patent ‘977 discloses the limitation of claim 17. Claim 4 of patent ‘977 further discloses the limitation of claim 19. The memory system according to claim 17, wherein the random number generator circuit is configured to perform an XOR operation on an operation result of the second XorShift operation to generate the second random number sequence data. Regarding claim 20, claim 2 of patent ‘977 discloses the limitation of claim 17. Claim 4 of patent ‘977 further discloses the limitation of claim 20. The memory system according to claim 17, wherein the random number generator circuit is configured to: perform an XOR operation on an operation result from the second XorShift circuit; and perform the second XorShift operation on an operation result of the XOR operation to generate the second random number sequence data . 08-34 AIA Claim s 1 and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12216924 . Although the claims at issue are not identical, they are not patentably distinct from each other because, they claim the same coverage of invention by providing a seed generator circuit . Regarding independent claim 1, claim 12 of recited patent discloses the limitation of claim 1. A memory system comprising: a nonvolatile memory; a controller configured to store data into the nonvolatile memory; a seed generator circuit configured to: generate first random number sequence data by performing a first XorShift operation on inputted data; generate a seed by using the first random number sequence data, and a random number generator circuit configured to generate second random number sequence data by performing a second XorShift operation on the seed. Regarding independent claim 13, claim 12 of recited disclose the limitation of claim 13. A memory system comprising: a nonvolatile memory; a memory controller configured to control storing of data into the nonvolatile memory; a seed generator circuit configured to: generate first random number sequence data by performing a first XorShift operation on storage location data indicating a storage location of the data in the nonvolatile memory; and generate a seed by using the first random number sequence data; and a random number generator circuit configured to generate second random number sequence data by performing a second XorShift operation on the seed . 08-36 AIA Claim s 2-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-16 of U.S. Patent No. 12,216,924 in view of U.S Patent No. 11, 543,977 . Regarding claim 2, claim 12 of recited patent discloses the limitation of claim 1. However, Patent ‘924 is silent with respect to The memory system according to claim 1, wherein the seed generator circuit includes a plurality of XorShift circuits, and a nonlinear transformation circuit configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits, and the first random number sequence data are generated by using the plurality of XorShift circuits and a nonlinear transformation circuit. Claim 1 of patent ‘977 disclose the limitation of claim 2. The memory system according to claim 1, wherein the seed generator circuit includes a plurality of XorShift circuits, and a nonlinear transformation circuit configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits, and the first random number sequence data are generated by using the plurality of XorShift circuits and a nonlinear transformation circuit. Since Patent ‘924 and Patent ‘977. are both from the same field of endeavor, the purpose disclosed by Patent ‘977 would have been recognized in the pertinent art of Patent ‘924. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘924 to teaching of Patent ‘977 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 3, claim 1 of patent ‘977 discloses the limitation of claim 2. Claim 2 of patent ‘977 further discloses The memory system according to claim 2, wherein the plurality of XorShift circuits include a first XorShift circuit and a second XorShift circuit, the first XorShift circuit is configured to perform the first XorShift operation on the inputted data, and the second XorShift circuit is configured to perform processing on output data from both the first XorShift circuit and the nonlinear transformation circuit to generate the seed. Regarding claim 4, claim 1 of patent ‘977 disclose the limitation of claim 2. Claim 4 of patent ‘977 further discloses the limitation of claim 4. The memory system according to claim 2, wherein the random number generator circuit is configured to perform an XOR operation on an operation result of the second XorShift operation to generate the second random number sequence data. Regarding claim 5, claim 1 of patent ‘977 discloses the limitation of claim 2. Claim 4 of patent ‘977 further discloses the limitation of claim 5. The memory system according to claim 2, wherein the random number generator circuit is configured to: perform an XOR operation on an operation result from the second XorShift circuit; and perform the second XorShift operation on an operation result of the XOR operation to generate the second random number sequence data. Regarding claim 6, claim 1 of recited patent discloses the limitation of claim 1. Claim 6 of patent ‘977 discloses the limitation of claim 6. The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a nonlinear transformation of a same kind. Regarding claim 7, claim 1 of recited patent discloses the limitation of claim 2. Claim 6 of patent ‘977 discloses the limitation of claim 7. The memory system according to claim 2, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a plurality of kinds of different nonlinear transformations. Regarding claim 8, claim 6 of patent ‘977 discloses the limitation of claim 7. Claim 7 of patent ‘977 discloses the limitation of claim 8. The memory system according to claim 7, wherein the plurality of S-box circuits include at least two S-box circuits configured to output different numbers of bits. Regarding claim 9, claim 12 of recited patent discloses the limitation of claim 1. However, Patent ‘924 is silent with respect to The memory system according to claim 1, further comprising an exchange circuit configured to exchange data positions in the second random number sequence data. Claim 8 of patent ‘977 discloses the limitation of claim 9. The memory system according to claim 1, further comprising an exchange circuit configured to exchange data positions in the second random number sequence data. Since Patent ‘924 and Patent ‘977. are both from the same field of endeavor, the purpose disclosed by Patent ‘977 would have been recognized in the pertinent art of Patent ‘924. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘924 to teaching of Patent ‘977 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 10, claim 12 of recited patent discloses the limitation of claim 1. However, patent ‘924 are silent with respect to The memory system according to claim 1, wherein the random number generator circuit includes an inversion circuit configured to perform bit inversion, byte inversion, or word inversion before or after performing the second XorShift operation. Claim 9 of patent ‘977 discloses the limitation of claim 10. The memory system according to claim 1, wherein the random number generator circuit includes an inversion circuit configured to perform bit inversion, byte inversion, or word inversion before or after performing the second XorShift operation. Regarding claim 11, claim 12 of recited patent discloses the limitation of claim 1. However, patent ‘924 is silent with respect to The memory system according to claim 1, further comprising a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein: the first XorShift circuit includes a first input and a first output; the second XorShift circuit includes a second input and a second output; the first input is connected to an output of the first S-box circuit, and the first output is connected to an input the second S-box circuit; and the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit. Claim 10 of patent ‘977 discloses the limitation of claim 11. The memory system according to claim 1, further comprising a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein: the first XorShift circuit includes a first input and a first output; the second XorShift circuit includes a second input and a second output; the first input is connected to an output of the first S-box circuit, and the first output is connected to an input the second S-box circuit; and the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit. Regarding claim 12, claim 12 of recited patent discloses the limitation of claim 1. However, patent ‘924 is silent with respect to The memory system according to claim 1, further comprising a plurality of units, each of which includes a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein in each of the plurality of units, the first XorShift circuit includes a first input and a first output, and the second XorShift circuit includes a second input and a second output, the first input is connected to an output of the first S-box circuit, and the first output is connected to an input of the second S-box circuit, the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit, and a bit shift amount used in the first and second XorShift circuits of each of the plurality of units differs among the plurality of units. Claim 11 of patent ‘977 disclose the limitation of claim 12. The memory system according to claim 1, further comprising a plurality of units, each of which includes a first XorShift circuit, a second XorShift circuit, a first S-box circuit, and a second S-box circuit, wherein in each of the plurality of units, the first XorShift circuit includes a first input and a first output, and the second XorShift circuit includes a second input and a second output, the first input is connected to an output of the first S-box circuit, and the first output is connected to an input of the second S-box circuit, the second input is connected to an output of the second S-box circuit, and the second output is connected to an input of the first S-box circuit, and a bit shift amount used in the first and second XorShift circuits of each of the plurality of units differs among the plurality of units . 08-36 AIA Claim s 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-16 of U.S. Patent No. 12,216,924 in view of U.S Patent No. 11,875,041 . Regarding claim 14, claim 12 of recited patent discloses the limitation of claim 13. However, patent ‘924 is silent with respect to The memory system according to claim 13, wherein the memory controller is configured to store the data at the storage location in the nonvolatile memory designated by a page number, and the storage location data contains the page number, or the page number and a frame number contained in the page number. Claim 14 of patent ‘041 discloses the limitation of claim 14. The memory system according to claim 13, wherein the memory controller is configured to store the data at the storage location in the nonvolatile memory designated by a page number, and the storage location data contains the page number, or the page number and a frame number contained in the page number. Since Patent ‘924 and Patent ‘041 are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘924. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘924 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 15, claim 12 of recited patent disclose the limitation of claim 13. However, patent ‘924 is silent with respect to The memory system according to claim 13, wherein the number generator circuit randomizes user data using the second random number sequence data, and the memory controller stores the randomized user data as the data at the storage location in the nonvolatile memory. Claim 16 of patent ‘041 discloses the limitation of claim 15 The memory system according to claim 13, wherein the number generator circuit randomizes user data using the second random number sequence data, and the memory controller stores the randomized user data as the data at the storage location in the nonvolatile memory. Since Patent ‘924 and Patent ‘041. are both from the same field of endeavor, the purpose disclosed by Patent ‘041 would have been recognized in the pertinent art of Patent ‘924. It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Patent ‘924 to teaching of Patent ‘041 for purpose of using a seed generator circuit to generate a seed by using number sequence data by performing Xorshift operation on the seed. Regarding claim 16, claim 12 of recited patent discloses the limitation of claim 13. However, patent ‘924 is silent with respect to The memory system according to claim 13, wherein the first random number sequence data are generated by using a plurality of XorShift circuits and a nonlinear transformation circuit, and the nonlinear transformation circuit is configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits. Claim 2 of patent ‘041 discloses the limitation of claim 16. wherein the first random number sequence data are generated by using a plurality of XorShift circuits and a nonlinear transformation circuit, and the nonlinear transformation circuit is configured to perform a nonlinear transformation on output data from at least one of the plurality of XorShift circuits. Regarding claim 17, claim 2 of patent ‘041 discloses the limitation of claim 16. Claim 3 of patent ‘041 further discloses the limitation of claim 17. The memory system according to claim 16, wherein the plurality of XorShift circuits include a first XorShift circuit and a second XorShift circuit, the first XorShift circuit is configured to perform the first XorShift operation on the storage location data, and the second XorShift circuit is configured to perform processing on output data from both the first XorShift circuit and the nonlinear transformation circuit to generate the seed. Regarding claim 18, claim 2 of patent ‘041 disclose the limitation of claim 16. Claim 6 of patent ‘041 discloses the limitation of claim 18. The memory system according to claim 16, wherein the nonlinear transformation circuit includes a plurality of S-box circuits configured to perform a nonlinear transformation of a same kind. Regarding claim 19, claim 3 of patent ‘041 discloses the limitation of claim 17. Claim 4 of patent ‘041 further discloses the limitation of claim 19. The memory system according to claim 17, wherein the random number generator circuit is configured to perform an XOR operation on an operation result of the second XorShift operation to generate the second random number sequence data. Regarding claim 20, claim 3 of patent ‘041 discloses the limitation of claim 17. Claim 5 of patent ‘041 further disclose the limitation of claim 20. The memory system according to claim 17, wherein the random number generator circuit is configured to: perform an XOR operation on an operation result from the second XorShift circuit; and perform the second XorShift operation on an operation result of the XOR operation to generate the second random number sequence data. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH D DINH whose telephone number is (571)270-5375. The examiner can normally be reached Monday to Friday 8:00am 5:00pm. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MINH D DINH/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827 Application/Control Number: 19/002,373 Page 2 Art Unit: 2827 Application/Control Number: 19/002,373 Page 3 Art Unit: 2827 Application/Control Number: 19/002,373 Page 4 Art Unit: 2827 Application/Control Number: 19/002,373 Page 5 Art Unit: 2827 Application/Control Number: 19/002,373 Page 6 Art Unit: 2827 Application/Control Number: 19/002,373 Page 7 Art Unit: 2827 Application/Control Number: 19/002,373 Page 8 Art Unit: 2827 Application/Control Number: 19/002,373 Page 9 Art Unit: 2827 Application/Control Number: 19/002,373 Page 10 Art Unit: 2827 Application/Control Number: 19/002,373 Page 11 Art Unit: 2827 Application/Control Number: 19/002,373 Page 12 Art Unit: 2827 Application/Control Number: 19/002,373 Page 13 Art Unit: 2827 Application/Control Number: 19/002,373 Page 14 Art Unit: 2827 Application/Control Number: 19/002,373 Page 15 Art Unit: 2827 Application/Control Number: 19/002,373 Page 16 Art Unit: 2827 Application/Control Number: 19/002,373 Page 17 Art Unit: 2827 Application/Control Number: 19/002,373 Page 18 Art Unit: 2827 Application/Control Number: 19/002,373 Page 19 Art Unit: 2827 Application/Control Number: 19/002,373 Page 20 Art Unit: 2827 Application/Control Number: 19/002,373 Page 21 Art Unit: 2827 Application/Control Number: 19/002,373 Page 22 Art Unit: 2827 Application/Control Number: 19/002,373 Page 23 Art Unit: 2827 Application/Control Number: 19/002,373 Page 24 Art Unit: 2827 Application/Control Number: 19/002,373 Page 25 Art Unit: 2827 Application/Control Number: 19/002,373 Page 26 Art Unit: 2827 Application/Control Number: 19/002,373 Page 27 Art Unit: 2827 Application/Control Number: 19/002,373 Page 28 Art Unit: 2827 Application/Control Number: 19/002,373 Page 29 Art Unit: 2827 Application/Control Number: 19/002,373 Page 30 Art Unit: 2827 Application/Control Number: 19/002,373 Page 31 Art Unit: 2827 Application/Control Number: 19/002,373 Page 32 Art Unit: 2827 Application/Control Number: 19/002,373 Page 33 Art Unit: 2827
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