DETAILED ACTION
This office action is in response to application 19/002,413 filed 12/26/2024 that is a continuation of 17/629,306 filed 9/22/2022 that claims priority to PCT/CN2021/081076 filed 3/16/2021
Claim 1 is cancelled. Claims 2-21 are new. Thus claims 2-21 were examined.
The IDS sent 3/11/2025 has been considered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2-3, 11-15, and 17-20, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-9, 10-11 and 25 of U.S. Patent No. US 12,210,447. Although the claims at issue are not identical, they are not patentably distinct from each other as a comparison of the claims show the limitations of the claims of the instant application shown in the first column are found in the listed claims of U.S. Patent No., 12,210,447 as shown in the second column in the comparison below:
19/002,413
US 12,210,447
2.
A memory system, comprising: one or more non-volatile memory devices;
1.
A memory system, comprising: one or more non-volatile memory devices;
and processing circuitry coupled with the one or more non-volatile memory devices, wherein the processing circuitry is configured to cause the memory system to:
and processing circuitry coupled with the one or more non-volatile memory devices, wherein the processing circuitry is configured to cause the memory system to:
initiate a first timer corresponding to a first region in response to performing one or more first access operations for data stored at the first region;
initiate a timer corresponding to a first region in response to performing one or more access operations for data stored at the first region;
transmit, to a host system and based at least in part on a first value associated with the first timer, a first portion of a mapping that indicates first relationships between first logical addresses and first physical addresses of the one or more non-volatile memory devices in the first region;
transmit, to a host system, ... based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies the threshold;... a first portion of a mapping that indicates relationships between logical addresses and physical addresses of the one or more non- volatile memory devices in the first region
and transmit, to the host system and based at least in part on the first value associated with the first timer, a second portion of the mapping that indicates second relationships between second logical addresses and second physical addresses of the one or more non-volatile memory devices in a second region
transmit, to the host system, ... based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies the threshold, ...a second portion of the mapping that indicates relationships between logical addresses and physical addresses of the one or more non- volatile memory devices in the second region second recency parameter associated with the second region
3.
wherein the processing circuitry is further configured to cause the memory system to: determine, for each of a plurality of regions of the one or more non-volatile memory devices, a respective recency parameter, wherein the respective recency parameters comprise a duration elapsed since performing an access operation on the respective region of the plurality of regions.
3.
wherein the processing circuitry is further configured to cause the memory system to: determine, for each of a plurality of regions of the one or more non-volatile memory devices, a respective recency parameter, wherein the respective recency parameters comprise a duration elapsed since performing an access operation on the respective region of the plurality of regions.
11.
wherein the processing circuitry is further configured to cause the memory system to: maintain the first region as an active region based at least in part on determining that the first value associated with the first timer.
10.
wherein the processing circuitry is further configured to cause the memory system to: maintain the first region a an active region based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies the threshold
12.
wherein the first region comprises a first quantity of data and is associated with a first quantity of logical block addresses (LBAs) and the second region comprises the first quantity of data and is associated with the first quantity of LBAs.
11.
wherein the first region comprises a first quantity of data and is associated with a first quantity of logical block addresses (LBAs) and the second region comprises the first quantity of data and is associated with the first quantity of LBAs.
13.
A memory system, comprising: one or more non-volatile memory devices;
1.
A memory system, comprising: one or more non-volatile memory devices;
and processing circuitry coupled with the one or more non-volatile memory devices,
and processing circuitry coupled with the one or more non-volatile memory devices, wherein the processing circuitry is configured to cause the memory system to:
wherein the processing circuitry is configured to cause the memory system to: initiate a timer corresponding to a first region in response to performing one or more access operations for data stored at the first region;
initiate a timer corresponding to a first region in response to performing one or more access operations for data stored at the first region;
determine a first recency parameter associated with the first region of the one or more non-volatile memory devices does not satisfy a threshold, wherein the first recency parameter is based at least in part on a value of the timer; .
8.
based at least in part on determining that the first recency parameter associated with the first region does not satisfy the threshold; … deactivate the first region from being part of the host performance booster mode
and deactivate the first region from operating in a host performance booster mode based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices does not satisfy the threshold
deactivate the first region from being part of the host performance booster mode based at least in part on determining that the first recency parameter associated with the first region does not satisfy the threshold;
14.
determine whether an index associated with the first region does not satisfies an index threshold in a ranking of regions indicating which regions were accessed most recently, wherein determining the first recency parameter does not satisfy the threshold is based at least in part on the index not satisfying the index threshold.
2.
determine whether an index associated with the first region is greater than an index threshold in a ranking of regions indicating which regions were accessed most recently.... determine whether the first recency parameter satisfies the threshold
15.
wherein determining the first recency parameter does not satisfy the threshold is based at least in part on the value of the timer not satisfying the duration threshold.
1.
determine whether a first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies a threshold, wherein the first recency parameter is based at least in part on a value of the timer;
4.
determine that the first recency parameter satisfies the threshold by determining that an access operation was performed on the first region of the one or more non-volatile memory devices within a duration
17.
transmit, to a host system, an indication that the first region of the one or more non-volatile memory devices is deactivated and a third region of the one or more non-volatile memory devices is activated.
8.
and transmit, to the host system, an indication that the first region of the one or more non-volatile memory devices is deactivated and a third region of the one or more non-volatile memory devices is activated.
18.
activate the third region of the one or more non-volatile memory devices to use as part of the host performance booster mode based at least in part on deactivating the first region of the one or more non-volatile memory devices; and perform a read operation on at least the third region of the one or more non- volatile memory devices based at least in part on activating the third region of the one or more non-volatile memory
9.
activate the third region of the one or more non-volatile memory devices to use as part of the host performance booster mode based at least in part on deactivating the first region of the one or more non-volatile memory devices; and perform a second read operation on at least the third region of the one or more non-volatile memory devices based at least in part on activating the third region of the one or more non-volatile memory devices.
19.
A method by a memory system, comprising:
25.
A Method, comprising
initiating a first timer corresponding to a first region in response to performing one or more access operations for data stored at the first region;
initiating a timer corresponding to a first region in response to performing one or more access operations for data stored at the first region;
determine a first recency parameter associated with the first region of the one or more non-volatile memory devices does not satisfy a threshold, wherein the first recency parameter is based at least in part on a value of the timer; .
based at least in part on determining that the first recency parameter associated with the first region does not satisfy the threshold; … deactivate the first region from being part of the host performance booster mode
and deactivate the first region from operating in a host performance booster mode based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices does not satisfy the threshold
deactivate the first region from being part of the host performance booster mode based at least in part on determining that the first recency parameter associated with the first region does not satisfy the threshold;
20.
determining, for each of a plurality of regions of the one or more non-volatile memory devices, a respective recency parameter, wherein the respective recency parameters comprise a duration elapsed since performing an access operation on the respective region of the plurality of regions.
3.
determine, for each of a plurality of regions of the one or more non-volatile memory devices, a respective recency parameter, wherein the respective recency parameters comprise a duration elapsed since performing an access operation on the respective region of the plurality of regions.
Allowable Subject Matter
Claims 4-10, 13-18, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an statement of reasons for the indication of allowable subject matter:
Regarding claims 4 and 21, the prior art does not teach or suggest ‘receive, after transmitting the first portion and prior to transmitting the second portion, a command to read data that is stored in the first region and the second region of the one or more non-volatile memory devices, the command comprising a physical address of the one or more non-volatile memory devices in accordance with the first portion of the mapping’. Examiner has interpreted the phrase “in accordance with” to mean “consistent with”, thus the system is issuing a command to read data, where the command includes the physical address consistent with the first portion of the mapping.
Thus this limitation requires:
A first portion of mapping information sent to a host associated with a first region of data.
A second portion of mapping information sent to a host associated with a second region of data.
A read command containing a physical address to data in the first region that is associated with first portion of mapping information sent to the host AND contains a request to read data from the second region of data associated with the second portion of mapping information sent to the host.
The read command request is received between the first portion and the second portion.
Thus the read request contains a read request for two pieces of data (1) data in the first portion whose mapping information was sent to the host, and (2) data whose mapping information has not yet been sent to the host. The read request for the first piece of data contains the physical address of the data in the storage device (sent to the host earlier). Thus the read requests is for a plurality of data blocks/chunks/sections and contains the physical addresses for at least one of the data blocks/chunks/sections.
An updated search failed to identify a teaching alone or in combination, to teach the claim limitations. As such, they are in condition for allowance.
Dependent claims 5-10 are allowable based on their dependence from claim 4.
Regarding claim 13, the prior art does not teach or suggest ‘and deactivate the first region from operating in a host performance booster mode based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices does not satisfy the threshold’. Consistent with paragraphs [0010]-[0011] of the instant application, a host performance booster mode in an active state may be a mode where the memory tracks access to a region of memory determined to be active based on how frequently it is accessed and maintains the mapping information in a mapping table on a host that subsequently send the physical address in any command requests to the memory device so that the memory device controller may skip loading logical to physical table entries from system memory. Per [0083] of the instant application, deactivating a region means a region may not be a part of a HB mode request and the host system is notified that the region is not active, and thus the host should no longer send commands with a physical address for this region of memory. Thus this claim recites the limitation that the host is informed that it may no longer send physical addresses in commands to the memory device.
The closest prior art is Kang (KANG US 2021/0216458 A1) that discloses deactivating storing data on a host. However Kang teaches using the host as an auxiliary storage device for the memory controller and it’s deactivating step is instructing the host that it no longer needs to store the mapping. See Kang [0051]. Kang does not teach that while it contains a logical/physical mapping of the data on the host, the host will use the physical addresses instead of the logical address in its data access requests. Thus Kang does not teach ‘deactivate the first region from operating in a host performance booster mode’ that informs the system that it no longer needs to maintain the data and may no longer use the physical data in its access requests.
Dependent claims 14-18 are allowed based on their dependence from allowed independent claim 13 from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 11, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kaniyur (Kaniyur et al., US 2007/0061549 A1) in view of Kim (KIM et al., US 2020/0233796 A1).
Regarding claim 2, Kaniyur teaches A memory system, (Kaniyur Fig 5 and para [0003] that discloses an I/O hub within computer system 500 that contains Memory 520 thus the computer system 500 is an example of a memory system.) … and processing circuitry coupled with the one or more non-volatile memory devices, wherein the processing circuitry is configured to cause the memory system to: (Kaniyur [0018] discloses processing logic that may comprise circuitry may execute software to perform the operations. See also Kaniyur Fig. 5 Processor 510 and para [0049]. )
initiate a first timer corresponding to a first region in response to performing one or more first access operations for data stored at the first region; (Kaniyur [0025]-[0027] teaches a least recently used (LRU) timer and a plurality of memory address mapping flags, LRU Flags, where each LRU Flag counts down with ever tick of the LRU timer. The LRU flag is used to select mapping data for eviction with the mapping associated with the oldest/lowest mapping value evicted first. If an access occurs to the address, the LRU flag value is reset to the highest value.)
Kaniyur teaches a Least Recently Used timer that counts down LRU Flags associated with address translations and de-allocates (i.e. evicts mapping entries whose LRU Flags with the minimum values when a mapping entry must be evicted to create space for a new mapping entry. However, Kaniyur does not disclose transmitting evicted mapping information to a host, and does not disclose comprising: one or more non-volatile memory devices; … transmit, to a host system and based at least in part on a first value associated with the first timer, a first portion of a mapping that indicates first relationships between first logical addresses and first physical addresses of the one or more non-volatile memory devices in the first region;
and transmit, to the host system and based at least in part on the first value associated with the first timer, a second portion of the mapping that indicates second relationships between second logical addresses and second physical addresses of the one or more non-volatile memory devices in a second region.
Kim, of a similar field of endeavor, further discloses comprising: one or more non-volatile memory devices; (Kim [0076] discloses the storage may be directed to nonvolatile memory cells, thus the target of the memory access may be to a non-volatile memory device of Kim figure 2.)
… transmit, to a host system and based at least in part on a first value associated with the first timer, a first portion of a mapping that indicates first relationships between first logical addresses and first physical addresses of the one or more non-volatile memory devices in the first region; (Kim [Abstract] and [0010], [0055]-[0056] discloses a memory controller may remove/evict a logical to physical address segment from the map data storage based on a least recently used LRU algorithm. The system will provide to a host the mapping data for evicted mapping entry. Thus the solution of Kaniyur in view of Kim would look at the LRU flag of each address and select for eviction the address with the lowest LRU Flag to send to the host, where the mapping data contains logical and physical address for the of one or more memory blocks on the memory 510 of Kaniyur.
Kim [0042] and [0053] discloses that the mapping data may be managed on a segment basis and each segment sent to the host may contain a plurality of logical addresses and a plurality of physical addresses. The set of logical addresses within a segment is an example of a first portion of a mapping that indicates a first relationships between the first logical addresses and first physical addresses.)
and transmit, to the host system and based at least in part on the first value associated with the first timer, a second portion of the mapping that indicates second relationships between second logical addresses and second physical addresses of the one or more non-volatile memory devices in a second region. (Kim [Abstract], [0010], [0042], [0053], and [0055]-[0056] discloses the system may send to the host a segment, including a plurality of physical addresses associated with a segment when the mapping information is the LRU data, i.e. has the lowest LRU Flag. The physical addresses for in the segment for addresses 2 and beyond are an example of a second portion of the mapping that indicates second relationships between second logical addresses and second physical address.)
Kaniyur and Kim are in a similar field of endeavor as both relate to managing mapping information in a memory device that has limited space available to store the mapping information. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate sending evicted mapping data from the memory device to the host as taught by Kim into the solution of Kaniyur that must evict mapping data from the memory device due to lack of space. Thus combining prior art elements according to known methods to yield predictable results (saving the mapping data at the host that has a greater memory allocation that may be shared by a plurality of memory devices.)
The motivation to combine Kim into Kaniyur for claims 3, 11, and 12 are the same as those set forth in claim 2 above.
Regarding claim 3, Kaniyur and Kim teach all of the limitations of claim 2 above. Kaniyur further teaches wherein the processing circuitry is further configured to cause the memory system to: (Kaniyur [0018] discloses processing logic that may comprise circuitry may execute software to perform the operations. See also Kaniyur Fig. 5 Processor 510 and para [0049]. )
determine, for each of a plurality of regions of the one or more non-volatile memory devices, a respective recency parameter, wherein the respective recency parameters comprise a duration elapsed since performing an access operation on the respective region of the plurality of regions. (Kaniyur [0025]-[0027] teaches a least recently used (LRU) timer and a plurality of “LRU flag” that count down with ever tick of the LRU timer. If an access occurs to the address, the LRU flag value is reset to the highest value. Thus each LRU flag is an example of a recency parameter that tracks the elapsed time since performing an access operation.)
Regarding claim 11, Kaniyur and Kim teaches all of the limitations of claim 2 above. Kaniyur further teaches wherein the processing circuitry is further configured to cause the memory system to: (Kaniyur [0018] discloses processing logic that may comprise circuitry may execute software to perform the operations. See also Kaniyur Fig. 5 Processor 510 and para [0049]. )
maintain the first region as an active region based at least in part on determining that the first value associated with the first timer. (Examiner notes that the instant application does not contain a specific definition of an active region. Consistent with para [0010] of the instant application, and active region may be a subset of regions being tracked in a L2P table according to a recency parameter. Kaniyur [0025]-[0027] teaches memory address mapping is tracked suing a LRU Flag, that counts down with ever tick of a LRU timer. The LRU flag is used to select mappings for eviction from the mapping table on the memory, where the least recently used (LRU) mapping entries having the smallest LRU flag values and are evicted first. Thus the system maintains a set of mapping data associated with a first region based on determining that the LRU Flag value associated with the LRU Flag (the first timer) is not the lowest value.)
Regarding claim 19, Kaniyur teaches A method (Kaniyur [0015] discloses the inventive concepts are directed to a method and an apparatus.) by a memory system, (Kaniyur [0005] discloses the solution is directed to a Direct Memory Access (DMA) memory system.)
The remainder of claim 19 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 20, The method of claim 19
The remainder of claim 20 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kaniyur (Kaniyur et al., US 2007/0061549 A1) in view of Kim (KIM et al., US 2020/0233796 A1) as detailed in claim 2 above and further in view of Yamada (Yamada et al., US 6,088,780)
Regarding claim 12, Kaniyur and Kim teaches all of the limitations of claim 2 above. However, the combination does not explicitly teach wherein the first region comprises a first quantity of data and is associated with a first quantity of logical block addresses (LBAs) and the second region comprises the first quantity of data and is associated with the first quantity of LBAs.
Yamada, of a similar field of endeavor, further teaches wherein the first region comprises a first quantity of data and is associated with a first quantity of logical block addresses (LBAs) and the second region comprises the first quantity of data (Examiner notes that this limitation claims the second data contains a quantity of data that comprises (i.e. contains) the first quantity of data. In other words, the two regions are the same size. Under widest reasonable interpretation the first region may be the mapping data entry or the data the mapping table points to. See [0037] of the instant application that discloses a region is memory that corresponds to a physical address, thus both the mapping data to the data and the data itself are portions of memory associated with the physical address. Yamada, column 1 lines 24-35 teaches that historically pages are implemented in fixed sized blocks called pages, which of which can be mapped onto any of the physical addresses. Thus the target of a first mapping entry will be a page in size and the target of a second mapping entry will be a page in size and thus the first quantity of data associated with a first quantity of logical block address relationships will be the same quantity of logical block addresses relationships LBAs) and the second region comprises the first quantity of data.)
Kaniyur in view of Kim and Yamada further teaches and is associated with the first quantity of LBAs. (Examiner notes that no specific association with the first quantity of data is claimed, and any association such as maintained within the same management memory is prior art. Kaniyur discloses a first region and a second region may be stored in Memory 520, thus the second region may be associated with the first region in the solution of Kaniyur in view of Kim and Yamada.)
Kaniyur, Kim, and Yamada are all in a similar field of endeavor as all relate to mapping data stored in a memory that organizes data in pages. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the logical and physical pages to be of a single fixed matching size as taught by Kaniyur into the solution of Kaniyur and Kim that manages a mapping table for data stored in pages as taught by Kaniyur in view of Kim, thus combining prior art elements according to know methods to produce predictable results (supporting pages that are fixed size blocks as is traditionally done, which simplifies the management of pages in a fashion that traditional/existing memory controllers are able to support.)
Relevant Art
prior art made of record and not relied upon is considered pertinent to applicant's disclosure is:
A merriam-webster dictionary definition of “in accordance with” that defines it to be “in a way that agrees with or follows (something, such as a rule or request). A screen shot of the page https://www.merriam-webster.com/dictionary/in%20accordance%20with taken on 23/1/2016 by archive.org.
Conclusion
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/JANICE M. GIROUARD/Examiner, Art Unit 2138