DETAILED ACTION
This office action is in response to an Amendment/Request for Reconsideration after Non-Final Rejection filed 5/11/2026 for application 19/002,413 filed 12/26/2024 that is a continuation of 17/629,306 filed 9/22/2022 that claims priority to PCT/CN2021/081076 filed 3/16/2021
Claims 2, 5-6, and 19 have been amended. Claim 1 is cancelled. No claims are new. Thus claims 2-21 were examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Allowable Subject Matter
Claims 13-18 are allowed.
Claims 4-10, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an statement of reasons for the indication of allowable subject matter:
Regarding claims 4 and 21, the prior art does not teach or suggest ‘receive, after transmitting the first portion and prior to transmitting the second portion, a command to read data that is stored in the first region and the second region of the one or more non-volatile memory devices, the command comprising a physical address of the one or more non-volatile memory devices in accordance with the first portion of the mapping’. Examiner has interpreted the phrase “in accordance with” to mean “consistent with”, thus the system is issuing a command to read data, where the command includes the physical address consistent with the first portion of the mapping.
Thus this limitation requires:
A first portion of mapping information sent to a host associated with a first region of data.
A second portion of mapping information sent to a host associated with a second region of data.
A read command containing a physical address to data in the first region that is associated with first portion of mapping information sent to the host AND contains a request to read data from the second region of data associated with the second portion of mapping information sent to the host.
The read command request is received between the first portion and the second portion.
Thus the read request contains a read request for two pieces of data (1) data in the first portion whose mapping information was sent to the host, and (2) data whose mapping information has not yet been sent to the host. The read request for the first piece of data contains the physical address of the data in the storage device (sent to the host earlier). Thus the read requests is for a plurality of data blocks/chunks/sections and contains the physical addresses for at least one of the data blocks/chunks/sections.
An updated search failed to identify a teaching alone or in combination, to teach the claim limitations. As such, they are in condition for allowance.
Dependent claims 5-10 are allowable based on their dependence from claim 4.
Regarding claim 13, the prior art does not teach or suggest ‘and deactivate the first region from operating in a host performance booster mode based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices does not satisfy the threshold’. Consistent with paragraphs [0010]-[0011] of the instant application, a host performance booster mode in an active state may be a mode where the memory tracks access to a region of memory determined to be active based on how frequently it is accessed and maintains the mapping information in a mapping table on a host that subsequently send the physical address in any command requests to the memory device so that the memory device controller may skip loading logical to physical table entries from system memory. Per [0083] of the instant application, deactivating a region means a region may not be a part of a HB mode request and the host system is notified that the region is not active, and thus the host should no longer send commands with a physical address for this region of memory. Thus this claim recites the limitation that the host is informed that it may no longer send physical addresses in commands to the memory device.
The closest prior art is Kang (KANG US 2021/0216458 A1) that discloses deactivating storing data on a host. However Kang teaches using the host as an auxiliary storage device for the memory controller and it’s deactivating step is instructing the host that it no longer needs to store the mapping. See Kang [0051]. Kang does not teach that while it contains a logical/physical mapping of the data on the host, the host will use the physical addresses instead of the logical address in its data access requests. Thus Kang does not teach ‘deactivate the first region from operating in a host performance booster mode’ that informs the system that it no longer needs to maintain the data and may no longer use the physical data in its access requests.
Dependent claims 14-18 are allowed based on their dependence from allowed independent claim 13 from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 11, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kaniyur (Kaniyur et al., US 2007/0061549 A1) in view of Kim (KIM et al., US 2020/0233796 A1).
Regarding claim 2, Kaniyur teaches A memory system, (Kaniyur Fig 5 and para [0003] that discloses an I/O hub within computer system 500 that contains Memory 520 thus the computer system 500 is an example of a memory system.) … and processing circuitry coupled with the one or more non-volatile memory devices, wherein the processing circuitry is configured to cause the memory system to: (Kaniyur [0018] discloses processing logic that may comprise circuitry may execute software to perform the operations. See also Kaniyur Fig. 5 Processor 510 and para [0049]. )
initiate a first timer corresponding to a first region in response to performing one or more first access operations for data stored at the first region; (Kaniyur [0025]-[0027] teaches a least recently used (LRU) timer and a plurality of memory address mapping flags, LRU Flags, where each LRU Flag counts down with ever tick of the LRU timer. The LRU flag is used to select mapping data for eviction with the mapping associated with the oldest/lowest mapping value evicted first. If an access occurs to the address, the LRU flag value is reset to the highest value.)
Kaniyur teaches a Least Recently Used timer that counts down LRU Flags associated with address translations and de-allocates (i.e. evicts mapping entries whose LRU Flags with the minimum values when a mapping entry must be evicted to create space for a new mapping entry. However, Kaniyur does not disclose transmitting evicted mapping information to a host, and does not disclose comprising: one or more non-volatile memory devices; … transmit, to a host system and based at least in part on a first value associated with the first timer satisfying a duration threshold, a first portion of a mapping that indicates first relationships between first logical addresses and first physical addresses of the one or more non-volatile memory devices in the first region;
and transmit, to the host system and based at least in part on the first value associated with the first timer satisfying a duration threshold, a second portion of the mapping that indicates second relationships between second logical addresses and second physical addresses of the one or more non-volatile memory devices in a second region.
Kim, of a similar field of endeavor, further discloses comprising: one or more non-volatile memory devices; (Kim [0076] discloses the storage may be directed to nonvolatile memory cells, thus the target of the memory access may be to a non-volatile memory device of Kim figure 2.)
… transmit, to a host system and based at least in part on a first value associated with the first timer satisfying a duration threshold, a first portion of a mapping that indicates first relationships between first logical addresses and first physical addresses of the one or more non-volatile memory devices in the first region; (Kim [Abstract] and [0010], [0055]-[0056] discloses a memory controller may remove/evict a logical to physical address segment from the map data storage based on a least recently used LRU algorithm. Kim [0042] and [0053] discloses that the mapping data may be managed on a segment basis and each segment sent to the host may contain a plurality of logical addresses and a plurality of physical addresses. The set of logical addresses within a segment is an example of a first portion of a mapping that indicates a first relationships between the first logical addresses and first physical addresses.)
and transmit, to the host system and based at least in part on the first value associated with the first timer satisfying a duration threshold, a second portion of the mapping that indicates second relationships between second logical addresses and second physical addresses of the one or more non-volatile memory devices in a second region. (Kim [Abstract], [0010], [0042], [0053], and [0055]-[0056] discloses the system may send to the host a segment, including a plurality of physical addresses associated with a segment when the mapping information is the LRU data, i.e. has the lowest LRU Flag in the solution of Kaniyur in view of Kim. The physical addresses for in the segment for addresses 2 and beyond are an example of a second portion of the mapping that indicates second relationships between second logical addresses and second physical address.
Thus in the solution of Kaniyur in view of Kim, the system will provide to a host the mapping data for evicted mapping entry and look at the LRU flag of each address and select for eviction the address with the lowest LRU Flag to send to the host, where the mapping data contains logical and physical address for the of one or more memory blocks on the memory 510 of Kaniyur.
Per para [0012] of the instant application states ‘A memory system configured to manage active regions of a memory device based on some parameters is described herein. In some examples, a memory system may track recency parameters associated with regions of the memory system. For example, the memory system may track a duration, for each region, from when a prior access operation was performed. Active regions may refer to a subset of regions having undergone an access operation within a threshold duration.’ Thus the duration tracked may be the period of time since an access was performed. And the threshold may be any value used to determine if the period of time since an access was performed is less than, equal to, or greater than the value. Kaniyur [0025]-[0027] discloses each TLB entry maintains a priority state in the form of a LRU flag that counts down with every tick of a LRU timer, and is restarted when the memory associated with the TLB entry is accessed. Thus the LRU flag of Kaniyur tracks the period of time since an access was performed for the TLB entry and discloses the duration as claimed. Furthermore, Kaniyur schedules the TLB entry with the minimum TLB flag. The threshold value may be the minimum value of the set of LRU flags. Thus Kaniyur schedules entries for eviction which includes sending data to a host system based on a first value associated with the first timer (the LRU flag for the TLB entry) satisfying a duration threshold (having the minimum LRU flag value).
Kaniyur and Kim are in a similar field of endeavor as both relate to managing mapping information in a memory device that has limited space available to store the mapping information. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate sending evicted mapping data from the memory device to the host as taught by Kim into the solution of Kaniyur that must evict mapping data from the memory device due to lack of space. Thus combining prior art elements according to known methods to yield predictable results (saving the mapping data at the host that has a greater memory allocation that may be shared by a plurality of memory devices.)
The motivation to combine Kim into Kaniyur for claims 3, 11, and 12 are the same as those set forth in claim 2 above.
Regarding claim 3, Kaniyur and Kim teach all of the limitations of claim 2 above. Kaniyur further teaches wherein the processing circuitry is further configured to cause the memory system to: (Kaniyur [0018] discloses processing logic that may comprise circuitry may execute software to perform the operations. See also Kaniyur Fig. 5 Processor 510 and para [0049]. )
determine, for each of a plurality of regions of the one or more non-volatile memory devices, a respective recency parameter, wherein the respective recency parameters comprise a duration elapsed since performing an access operation on the respective region of the plurality of regions. (Kaniyur [0025]-[0027] teaches a least recently used (LRU) timer and a plurality of “LRU flag” that count down with ever tick of the LRU timer. If an access occurs to the address, the LRU flag value is reset to the highest value. Thus each LRU flag is an example of a recency parameter that tracks the elapsed time since performing an access operation.)
Regarding claim 11, Kaniyur and Kim teaches all of the limitations of claim 2 above. Kaniyur further teaches wherein the processing circuitry is further configured to cause the memory system to: (Kaniyur [0018] discloses processing logic that may comprise circuitry may execute software to perform the operations. See also Kaniyur Fig. 5 Processor 510 and para [0049]. )
maintain the first region as an active region based at least in part on determining that the first value associated with the first timer. (Examiner notes that the instant application does not contain a specific definition of an active region. Consistent with para [0010] of the instant application, and active region may be a subset of regions being tracked in a L2P table according to a recency parameter. Kaniyur [0025]-[0027] teaches memory address mapping is tracked suing a LRU Flag, that counts down with ever tick of a LRU timer. The LRU flag is used to select mappings for eviction from the mapping table on the memory, where the least recently used (LRU) mapping entries having the smallest LRU flag values and are evicted first. Thus the system maintains a set of mapping data associated with a first region based on determining that the LRU Flag value associated with the LRU Flag (the first timer) is not the lowest value.)
Regarding claim 19, Kaniyur teaches A method (Kaniyur [0015] discloses the inventive concepts are directed to a method and an apparatus.) by a memory system, (Kaniyur [0005] discloses the solution is directed to a Direct Memory Access (DMA) memory system.)
The remainder of claim 19 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 20, The method of claim 19
The remainder of claim 20 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kaniyur (Kaniyur et al., US 2007/0061549 A1) in view of Kim (KIM et al., US 2020/0233796 A1) as detailed in claim 2 above and further in view of Yamada (Yamada et al., US 6,088,780)
Regarding claim 12, Kaniyur and Kim teaches all of the limitations of claim 2 above. However, the combination does not explicitly teach wherein the first region comprises a first quantity of data and is associated with a first quantity of logical block addresses (LBAs) and the second region comprises the first quantity of data and is associated with the first quantity of LBAs.
Yamada, of a similar field of endeavor, further teaches wherein the first region comprises a first quantity of data and is associated with a first quantity of logical block addresses (LBAs) and the second region comprises the first quantity of data (Examiner notes that this limitation claims the second data contains a quantity of data that comprises (i.e. contains) the first quantity of data. In other words, the two regions are the same size. Under widest reasonable interpretation the first region may be the mapping data entry or the data the mapping table points to. See [0037] of the instant application that discloses a region is memory that corresponds to a physical address, thus both the mapping data to the data and the data itself are portions of memory associated with the physical address. Yamada, column 1 lines 24-35 teaches that historically pages are implemented in fixed sized blocks called pages, which of which can be mapped onto any of the physical addresses. Thus the target of a first mapping entry will be a page in size and the target of a second mapping entry will be a page in size and thus the first quantity of data associated with a first quantity of logical block address relationships will be the same quantity of logical block addresses relationships LBAs) and the second region comprises the first quantity of data.)
Kaniyur in view of Kim and Yamada further teaches and is associated with the first quantity of LBAs. (Examiner notes that no specific association with the first quantity of data is claimed, and any association such as maintained within the same management memory is prior art. Kaniyur discloses a first region and a second region may be stored in Memory 520, thus the second region may be associated with the first region in the solution of Kaniyur in view of Kim and Yamada.)
Kaniyur, Kim, and Yamada are all in a similar field of endeavor as all relate to mapping data stored in a memory that organizes data in pages. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the logical and physical pages to be of a single fixed matching size as taught by Kaniyur into the solution of Kaniyur and Kim that manages a mapping table for data stored in pages as taught by Kaniyur in view of Kim, thus combining prior art elements according to know methods to produce predictable results (supporting pages that are fixed size blocks as is traditionally done, which simplifies the management of pages in a fashion that traditional/existing memory controllers are able to support.)
Relevant Art
prior art made of record and not relied upon is considered pertinent to applicant's disclosure is:
A merriam-webster dictionary definition of “in accordance with” that defines it to be “in a way that agrees with or follows (something, such as a rule or request). A screen shot of the page https://www.merriam-webster.com/dictionary/in%20accordance%20with taken on 23/1/2016 by archive.org.
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of 5/11/2026. They have been fully considered. However they are not persuasive I light of the rejections above and remarks detailed below.
Applicant argues on page 11 of their remarks ‘According to Kaniyur, the re-allocation of a TLB entry is based on a prior state relative to other TLB entries. The priority state of Kaniyur is not the same as “a first value associated with the first timer satisfying a duration threshold,” as recited in amended independent claim 2 because Kaniyur is silent as to any threshold, much less a value that satisfied a threshold’
Examiner respectfully disagrees. Per para [0012] of the instant application states ‘A memory system configured to manage active regions of a memory device based on some parameters is described herein. In some examples, a memory system may track recency parameters associated with regions of the memory system. For example, the memory system may track a duration, for each region, from when a prior access operation was performed. Active regions may refer to a subset of regions having undergone an access operation within a threshold duration.’ Thus the duration tracked may be the period of time since an access was performed. And the threshold may be any value used to determine if the period of time since an access was performed is less than, equal to, or greater than the value.
Kaniyur [0025]-[0027] discloses each TLB entry maintains a priority state in the form of a LRU flag that counts down with every tick of a LRU timer, and is restarted when the memory associated with the TLB entry is accessed. Thus the LRU flag of Kaniyur tracks the period of time since an access was performed for the TLB entry and discloses the duration as claimed. Furthermore, Kaniyur schedules the TLB entry with the minimum TLB flag. The threshold value may be the minimum value of the set of LRU flags. Thus Kaniyur schedules entries for eviction based on a first value associated with the first timer (the LRU flag for the TLB entry) satisfying a duration threshold (having the minimum LRU flag value).
Applicant further argues on page 11 ‘Further, even if the priority state of Kaniyur were construed to be relevant to "a first value associated with the first timer satisfying a duration threshold," as claimed, which Applicant asserts is incorrect, Kaniyur fails to teach or suggest a host transmission that is "based at least in part on a first value associated with the first timer satisfying a duration threshold," as claimed. Thus the elements of Kaniyur fails to teach or suggest "transmit[ting], to a host system and based at least in part on a first value associated with the first timer satisfying a duration threshold," as recited in amended independent claim 2.
Examiner respectfully notes Kaniyur discloses a system that selects mapping data to be evicted based on a least recently used (LRU) algorithm that maintains a first timer (a LRU flag associated with a TLB entry). Kim discloses data that is to be evicted from a mapping table (based on a LRU algorithm) is sent to the host before it is removed from the mapping table on the storage device..
Thus the solution of Kaniyur that evicts mapping information due to a LRU algorithm in view of Kim that sends evicted mapping information to a host will ‘transmit, to a host system and based on at least in part on a first value associated with the first timer satisfying a duration threshold’ as claimed.
Applicant argues on page 11 of their remarks ‘Kim is generally directed to "logical to physical (L2P) mapping information." Kim, Abstract. For example, Kim discusses a map data manager that "provide[s]at least one L2P address segment to the host in response to a map data request of the host." Id. According to Kim, "the map data manager 210 may select at least one logical to physical address segment to be provided to the host 300, based on a number of times to each of the plurality of logical to physical address segments is accessed (count of access)" or "based on the size of data to be accessed using each of the plurality of logical to physical address segments in response to a read request provided from the host 300" Id. ¶ [0055] (emphasis added). At the portions cited by the Office Action, Kim discusses prioritizing segments for removal from map data storage. See id. ¶ [0055]-[0065]. For example, Kim discusses that "the map data manager 210 may determine priorities between the plurality of logical to physical addresses segments, based on frequency or recency of access to each of the plurality of logical to physical address segments in response to a request provided from the host 300." Id. T [0055]. According to Kim, "[t]he data manager 210 may select at least one logical to physical address segment to be removed among the plurality of logical to physical address segments stored in the map data storage 220, based on the priorities of the plurality of logical to physical address segments. That is, Kim discusses conditions for selecting segments to provide to the host, and prioritization conventions for removing segments from storage.’
Examiner respectfully notes Kaniyur discloses a system that selects mapping data to be evicted based on a least recently used (LRU) algorithm that maintains a first timer (a LRU flag associated with a TLB entry). Kim discloses data that is to be evicted from a mapping table (based on a LRU algorithm) is sent to the host before it is removed from the mapping table on the storage device..
Kim [Abstract], [0010], [0042], [0053], and [0055]-[0056] discloses evicting data based on a least recently used (LRU) frequency.
Examiner notes Kim discloses in para [0054] the system may select for eviction an entry based on a number of times each of the physical address segments is accessed (count of access) in one embodiment, or based on the size of data to be accessed in a second embodiment. Thus Kim suggests a plurality of LRU means may be used to select a LRU entry.
Kaniyur teaches a third means/embedment for selecting a LRU entry for eviction in the solution of Kaniyur in view of Kim.
Kaniyur is cited to teach evicting data ‘based at least in part on a first value associated with the first timer satisfying a duration threshold’ using third embodiment for selecting a LRU entry to evict and Kim is cited to teach sending the evicted data to the host, thus teaches ‘transmit, to a host system’ evicted data based at least in part on a first value….
A person of ordinary skill in the art with both Kaniyur and Kim before them that there are a plurality of LRU measurements that may be used to evict data, including the LRU algorithm of Kaniyur that may be used to send evicted data to a host as taught by Kim.
Applicant further argues on page 12 of their remarks ‘The Office Action alleges the prioritization rules of Kim are relevant to "transmit[ting], to a host system and based at least in part on a first value associated with the first timer, a first portion of a mapping," as previously presented in independent claim 2. See Office Action, pp. 14-15 (citing Kim, Abstract and 11 [0010], [0055]-[0056]). However, the prioritization rules of Kim are not the same as, and do not teach or suggest "transmit[ting], to a host system and based at least in part on a first value associated with the first timer satisfying a duration threshold, a first portion of a mapping" as recited in amended independent claim 2. Instead, the prioritization rules of Kim are for removing data from the map data storage, and not for any host transmissions.’
Examiner respectfully disagrees with applicants statement ‘the prioritization rules of Kim are for removing data from the map data storage, and not for any host transmissions”. See Kim [0053]-[0054] included below that discloses, based on a LRU priority scheme, Kim sends the evicted data to the host before deleting it. Thus while Kim uses priorities for removing data from the local storage, it also sends the data to be removed to the host.
[0053] The map data manager 210 may provide at least one of the plurality of logical to physical address segments stored in the map data storage 220 to the host 300, in response to a map data request provided from the host 300.
[0054] The map data manager 210 may select at least one logical to physical address segment to be provided to the host 300. In an embodiment, the map data manager 210 may select at least one logical to physical address segment to be provided to the host 300, based on a number of times to each of the plurality of logical to physical address segments is accessed (count of access) in response to a read request provided from the host 300. In an embodiment, the map data manager 210 may select at least one logical to physical address segment to be provided to the host 300, based on the size of data to be accessed using each of the plurality of logical to physical address segments in response to a read request provided from the host 300.
[0055] The map data manager 210 may determine priorities between the plurality of logical to physical addresses segments, based on frequency or recency of access to each of the plurality of logical to physical address segments in response to a request provided from the host 300.
[0056] In detail, the map data manager 210 may set priorities between the plurality of logical to physical addresses segments, based on a least recently used (LRU) frequency of each of the plurality of logical to physical address segments to be accessed in response to a request provided from the host 300.
Applicant further argues on page 12 of their remarks ‘Further, the prioritization rules of Kim are "based on a least recently used (LRU) frequency" where "[t]he LRU frequency may be a relative index indicating a frequency of access to each logical to physical access segment[. Kim ¶ [0056] (emphasis added). A relative index is not the same as, and does not teach or suggest "a first value associated with the first timer satisfying a duration threshold," as claimed.
Examiner respectfully notes that Kaniyur is cited to teach ‘a first value associated with the first timer satisfying a duration threshold’, as Kaniyur selects a L2P mapping entry on a storage device to evict, and Kim is cited to teach that the evicted L2P mapping entry may be sent to a host before it is deleted.
Applicant further argues on page 12 of their remarks ‘Additionally, Kim discusses segments being provided to the host based on a count of access or size of data. However, a quantity of access attempts (e.g., count of access) and a data size are not the same as, and does not teach or suggest "a first value associated with the first timer, a first portion of a mapping," as claimed. Thus, the elements of Kim do not teach or suggest "transmit[ting], to a host system and based at least in part on a first value associated with the first timer satisfying a duration threshold, a first portion of a mapping," as recited in amended independent claim 2.’
Examiner respectfully notes Kim discloses in para [0054] the system may select for eviction an entry based on a number of times each of the physical address segments is accessed (count of access) in one embodiment, or based on the size of data to be accessed in a second embodiment. Thus Kim suggests a plurality of LRU means may be used to select a LRU entry.
Kaniyur teaches a third means/embedment for selecting a LRU entry for eviction in the solution of Kaniyur in view of Kim.
Kaniyur is cited to teach evicting data ‘based at least in part on a first value associated with the first timer satisfying a duration threshold’ using third embodiment for selecting a LRU entry to evict and Kim is cited to teach sending the evicted data to the host, thus teaches ‘transmit, to a host system’ evicted data based at least in part on a first value.
A person of ordinary skill in the art with both Kaniyur and Kim before them would recognize there are a plurality of LRU means for selecting a LRU entry that may be used to evict data, including the LRU algorithm of Kaniyur that may be used to send evicted data to a host as taught by Kim. Thus Kaniyur in view of Kim teaches ‘”transmit[ting], to a host system and based at least in part on a first value associated with the first timer satisfying a duration threshold, a first portion of a mapping’ as recited in amended independent claim 2.’
Applicant further argues on page 12 of their remarks ‘Yamada does not overcome the deficiencies of Kaniyur and Kim, nor does the Office Action suggest otherwise.’
Examiner respectfully notes, as detailed above, Kaniyur in view of Kim is not deficient and Examiner disagrees with Applicant’s conclusion that claims 2 and 19 are allowable..
Applicants argument with respect to dependent claims 3, 11-12, and 20 all rely upon perceived errors in the independent claims from which they depend and have been addressed in the independent claims above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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