Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/26/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-4 rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. (US 2023/0333627) in view of Yamaki et al. (US 5,671,393).
Regarding claim 1, Gao discloses a control device comprising: a first storage unit that requires no refreshing and has volatility [see paragraphs 28 & 45; memory devices may be SRAMs (SRAMs are volatile and do not require refreshing)]; a first processor configured to access the first storage unit [see Fig. 1 & paragraph 29; processor performs various operations on memory device]; and a first control circuit configured to perform mode control for the first storage unit based on the access request received from the first processor via the bus arbiter, wherein the first control circuit instructs, when a time period during which the access request is not received exceeds a predetermined time period in a state where the first storage unit is under a normal mode, the first storage unit to transition from the normal mode to a power saving mode [see paragraphs 30, 33 & 51; memory controller manages flow of data to memory device, after an amount of inactive time exceeds a threshold, the controller may switch the memory device from normal operating mode to a power save mode].
Gao does not expressly disclose a bus arbiter configured to arbitrate an access request from the first processor.
Yamaki discloses a memory system in which a bus arbiter may arbitrate access requests from a processor to a SRAM memory device [see Col. 2, lines 5-55].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the SRAM bus arbiter of Yamaki in the system of Gao.
The motivation for doing so would have been to arbitrate/select access requests from more than one CPU [see Yamaki, Col. 2, lines 5-17].
Therefore, it would have been obvious to combine Yamaki with Gao for the benefits listed above, to obtain the invention as specified in claims 1 and 3-4.
Regarding claim 3, the combination discloses the control device according to claim 1, wherein the first control circuit measures a time period during which the access request is not received [see Gao, paragraph 52; counter is used to determine an amount of time spent in inactive period].
Regarding claim 4, the combination discloses the control device according to claim 1, further comprising a time measurement circuit configured to measure a time period during which the access request is not received [see Gao, paragraph 52; counter is used to determine an amount of time spent in inactive period].
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of Yamaki.
Regarding claim 5, the combination discloses the control device of claim 1.
The combination does not expressly disclose a second storage unit that requires no refreshing and has volatility; and a second control circuit configured to perform mode control for the second storage unit based on the access request received from the first processor via the bus arbiter, wherein the second control circuit instructs, when a time period during which the access request is not received exceeds a predetermined time period in a state where the second storage unit is under a normal mode, the second storage unit to transition from the normal mode to the power saving mode.
The prior art combination discloses a first storage unit and first control circuit similar to the second storage unit and control circuit as discussed in claim 1 [see above rejection]. Although the references do not disclose a second storage unit and control circuit, the court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced [see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)]. Therefore, since a new and unexpected result of having a duplicate storage unit and control circuit is disclosed, it would have been obvious to combine Gao with Yamaki for the benefits listed above, to obtain the invention as specified in claims 5 and 8.
Regarding claim 8, the combination discloses the control device according to claim 5, wherein each of the first storage unit and the second storage unit is a single memory that requires no refreshing and has volatility [see Gao, paragraph 28; SRAM storage device is a single memory].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of Yamaki and further in view of Solomon (US 2025/0244818).
The combination of Gao and Yamaki discloses the control device according to claim 5.
The combination does not expressly disclose each of the first storage unit and the second storage unit is a memory bank including a plurality of memories that require no refreshing and have volatility.
Solomon discloses a system for managing the power of SRAM devices, wherein the SRAM devices are divided into banks and sub-banks [see paragraphs 5, 20 & 24-25].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the banks of Solomon in the system of Gao and Yamaki.
The motivation for doing so would have been control the power usage of portions of an SRAM that are not being accessed (i.e. finer granularity of power management) [see Solomon, paragraphs 24-5].
Therefore, it would have been obvious to combine Solomon with Gao and Yamaki for the benefits listed above, to obtain the invention as specified in claim 7.
Allowable Subject Matter
Claims 2 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record fails to disclose or render obvious the claim limitations regarding returning an acknowledgement for the access request to a first bus bridge via the bus arbiter after the first storage unit transitions to the power saving mode, and the first bus bridge instructs the first processor to stand by until the acknowledgement is received from the bus arbiter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim (US 2019/0220228), Otuksa 2024/0295973, Cho (US 2024/0061591), Kupermann (US 2015/0177820) – Generally teach SRAM memory devices that may be placed into different power modes based on inactivity levels.
Kimura (US 5,737,579) – Generally teaches a memory system which utilizes a bus arbiter and bridge circuitry for sending signals between devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137