DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-22 are pending.
Information Disclosure Statement
The information disclosure statement filed 09/04/2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5-8, 12, 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandra et al. [US 20230366930].
As to claim 1. Chandra discloses A test device, comprising:
a plurality of connection lines, [fig. 1, 0034] interconnections 132, 134;
a plurality of first test circuits, [fig. 1, 0034] Die 110 comprising a plurality of circuits 112, 114, 116, respectively coupled to the connection lines, [fig. 1, 0034], wherein the first test circuits respectively generate a plurality of detection signals according to a plurality of first test data, [fig. 18, 0063] test signal for Die2 is generated from test pattern generator of Die 1 transmitted through each cell of Die 1, and respectively transmit the detection signals to the connection lines, [0063]; and
a plurality of second test circuits, [fig. 1, 0034] Die 120 comprising a plurality of circuits 122, 124, 126, respectively coupled to the connection lines, [fig. 1, 0034], and receiving the detection signals through the connection lines, [fig. 1, 18, 0063] receive test signals from cells of Die 1, wherein the second test circuits respectively compare a plurality of second test data with the detection signals to generate a plurality of test results, [0064] compare error signature against expected signature of the test signals,
wherein the first test circuits and the second test circuits are arranged in an N*M matrix, and N and M are positive integers, [fig. 1] an array of cells of each Die.
As to claim 4. Chandra discloses The test device according to claim 1, further comprising: a shift register coupled to the second test circuits to output the test results sequentially according to a clock signal.
As to claim 5. Chandra discloses The test device according to claim 1, wherein each of the first test circuits comprises:
a logic gate, [fig. 18, 0063] pattern generator 1830, used to receive the first test data, [fig. 14, 0057] receive input data from BIST controller to generate the test pattern data, and perform logic computation on the first test data to generate each of the detection signals, [fig. 18, 0057, 0063] pattern generator 1830 generating test data for Die 2, through the wrapper cells; and
a multiplexer, [fig. 3, 18, 0036] multiplexers 304, 306 of the wrapper cells, coupled to the logic gate to select and transmit each of the detection signals to each of the connection lines according to a mode selection signal, [fig. 6, 18, 00043, 0063] the registers receive the signal from the pattern generator and output the signal to the wrapper cell of Die 2.
As to claim 6. Chandra discloses The test device according to claim 1, wherein each of the second test circuits comprises:
a logic gate receiving the second test data, [0063] wrapper cells scan chain receive test pattern from the other Die, and perform logic computation on the second test data to generate an output signal, [0063]; and
a comparator receiving the output signal and each of the detection signals, [0064], and
comparing the output signal with each of the detection signals to generate each of the test results, [0064].
As to claim 7. Chandra discloses The test device according to claim 1, wherein in a first test mode or a second test mode, when each of the test results has a first logic value, it means that the connection line corresponding to each of the test results having the first logic value operates in a normal connection state, [0064] test passed, and when each of the test results has a second logic value, it means that the connection line corresponding to each of the test results having the second logic value operates in an abnormal connection state, wherein the first logic value is different from the second logic value, [0064] test failed.
As to claim 8. Chandra discloses The test device according to claim 7, wherein the abnormal connection state comprises a short-circuit state, [0048], between the connection line and a power supply voltage or between the connection line and a ground voltage; [0048] all short circuit states of the circuitry are detected.
As to claim 12 is rejected using the same prior arts and reasoning as to that of claim 1.
As to claims 16-19 are rejected using the same prior arts and reasoning as to that of claims 5-8, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENYAM HAILE whose telephone number is (571)272-2080. The examiner can normally be reached 7:00 AM - 5:30 PM Mon. - Thur..
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/Benyam Haile/Primary Examiner, Art Unit 2688
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