CTNF 19/002,735 CTNF 82495 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-8 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Ming et al. (CN 114967811 A, hereinafter “Ming”) . Claim 1: Ming discloses a voltage regulator (Fig.2), configured to receive a supply voltage (V DD- ) to generate a regulated voltage (V O ), and the voltage regulator comprises: an operational amplifier (M P3 , M P4 , C 3 , M N3 , M N4 , I B1 ), configured to receive a reference voltage (V REF ) and a feedback signal (V FB ) to generate an output signal (V G ); and a power transistor (M P2 ), wherein a gate electrode receives the output signal of the operational amplifier (V G- ), a first electrode is coupled to the supply voltage (V DD ), and a second electrode is used to generate the regulated voltage (to V O ); wherein the operational amplifier comprises: an input stage (M N3 , M N4 ), configured to receive the reference voltage and the feedback signal (see Fig.2); a current source (M P3 , M P4 , C 3 ), coupled to the input stage (see Fig.2), wherein the current source comprises a first transistor (M P3 ) and a second transistor (M P4 ), source electrodes of the first transistor and the second transistors are coupled to the supply voltage (to V DD ; see Fig.2), gate electrodes of the first transistor and the second transistors are connected together (see Fig.2), a drain electrode and the gate electrode of the first transistor are connected together at a connection node (see Fig.2), and a drain electrode of the second transistor is coupled to the gate electrode of the power transistor (drain of M P4 connected to V G- ); and a capacitor (C 3 ), coupled between the connection node and a ground voltage (see Fig.2). Claim 5: Ming discloses a voltage regulator (Fig.2), configured to receive a supply voltage (V DD- ) to generate a regulated voltage (V O ), and the voltage regulator comprises: an operational amplifier (M P3 , M P4 , C 3 , M N3 , M N4 , I B1 ), configured to receive a reference voltage (V REF ) and a feedback signal (V FB ) to generate an output signal (V G ); a power transistor (M P2 ), wherein a gate electrode receives the output signal of the operational amplifier (V G- ), a first electrode is coupled to the supply voltage (V DD ), and a second electrode is used to generate the regulated voltage (V O ); and a current generator (M P3 , M P4 , C 3 ) comprising a first transistor (M P3 ), a second transistor (M P4 ) and a capacitor (C 3 ), wherein source electrodes of the first transistor and the second transistors are coupled to the supply voltage (to V DD ), gate electrodes of the first transistor and the second transistors are connected together (see Fig.2), a drain electrode and the gate electrode of the first transistor are connected together at a connection node (see Fig.2), a drain electrode of the second transistor is coupled to the gate electrode of the power transistor (drain of M P4 connected to V G- ), and the capacitor (C 3- ) is coupled between the connection node and a ground voltage (see Fig.2). PNG media_image1.png 450 702 media_image1.png Greyscale Claims 2 and 6: Ming discloses wherein capacitance of the capacitor is equal to gate-drain capacitance of the power transistor (C- 3- being equal to Miller capacitance C 2 , which is the gate-drain capacitance of M P1 ; see Fig.2 and pg.4, first paragraph). Claims 3 and 7: Ming discloses wherein a current flowing through the first transistor and the capacitor is equal to “ΔVDDsC1”, and the second transistor provides a mirrored current “ΔVDDsC1” to the gate electrode of the power transistor, wherein “ΔVDD” is a supply voltage ripple, “s” is Laplace operator, and “Cgs” is the capacitance of the capacitor (Ming discloses an identical structure of providing a capacitor C 3- - equal to the gate-drain capacitance C 2 in order to provide feedforward ripple cancellation; see pg.4, first paragraph, thus may be assumed to inherently operate functionally in the same manner; see MPEP 2114). Claims 4 and 8: Ming discloses wherein the power transistor is a P-type Metal Oxide Semiconductor Field Effect Transistors (M P2 ; see Fig.2) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. (US 2023/0185323) and Wang (US 2014/0340058) disclose similar LDO circuits . Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan Johnson whose telephone number is (571)270-1264. The examiner can normally be reached Monday - Friday, 9:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menna Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN JOHNSON/Primary Examiner, Art Unit 2836 Application/Control Number: 19/002,735 Page 2 Art Unit: 2836 Application/Control Number: 19/002,735 Page 3 Art Unit: 2836 Application/Control Number: 19/002,735 Page 4 Art Unit: 2836 Application/Control Number: 19/002,735 Page 5 Art Unit: 2836
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