Prosecution Insights
Last updated: July 17, 2026
Application No. 19/002,746

INTER-LANE SKEW COMPENSATION METHOD

Non-Final OA §102
Filed
Dec 27, 2024
Priority
Dec 27, 2023 — provisional 63/614,953
Examiner
CHEN, SIBIN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MediaTek Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
893 granted / 1031 resolved
+18.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
25 currently pending
Career history
1046
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
66.6%
+26.6% vs TC avg
§102
28.0%
-12.0% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1031 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 12-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawagoe (US 2012/0200330). Regarding claim 1, fig. 1 and 11 of Kawagoe discloses a circuitry, comprising: a first sampling circuit [e.g. that associated with the channels with 3.sub.8 and 3.sub.9 such as D8, D9, 5.sub.8, 5.sub.9, etc.], configured to use a first clock signal [output of 2.sub.8 and 2.sub.9] to sample first data [at respective D inputs of flip-flops in the channels] to generate sampled first data [at respective D outputs of flip-flops in the channels] to a plurality of first lanes of a transmitter [that receiving data SD, which propagates those signals to the next stage] (not shown) via a plurality of first connection lines; and a second sampling circuit [e.g. that associated with the channels with 3.sub.1 and 3.sub.16], configured to use a second clock signal [output of 2.sub.1 and 2.sub.16] to sample second data to generate sampled second data to a plurality of second lanes of the transmitter via a plurality of second connection lines; wherein lengths of the plurality of second connection lines are longer than lengths of the plurality of first connection lines (par. 83-84 describes where length of CLL is longest for 3.sub.1 and 3.sub.16 and shortest for 3.sub.8 and 3.sub.9), and delay amount of the second clock signal is less than delay amount of the first clock signal (par. 37 and 55 describe correcting for skew based on the length of the lines). Regarding claim 5, fig. 1 and 11 of Kawagoe discloses a third sampling circuit [e.g. that associated with the channels with 3.sub.1 and 3.sub.16 if the second sampling circuit were that associated with the channels with 3.sub.2 and 3.sub.15], configured to use a third clock signal to sample third data to generate sampled third data to a plurality of third lanes of the transmitter via a plurality of third connection lines; wherein lengths of the plurality of third connection lines are longer than the lengths of the plurality of second connection lines, and delay amount of the third clock signal is less than the delay amount of the second clock signal (par. 83-84). Regarding claim 8, fig. 1 and 11 of Kawagoe discloses a third sampling circuit [e.g. that associated with the channels with 3.sub.2 and 3.sub.15 if the second sampling circuit were that associated with the channels with 3.sub.2 and 3.sub.15], configured to use a third clock signal to sample third data to generate sampled third data, wherein the third data is received from a plurality of third lanes of a receiver via a plurality of third connection lines; and a fourth sampling circuit [e.g. that associated with the channels with 3.sub.1 and 3.sub.16 if the second sampling circuit were that associated with the channels with 3.sub.3 and 3.sub.14], configured to use a fourth clock signal to sample fourth data to generate sampled fourth data, wherein the fourth data is received from a plurality of fourth lanes of the receiver via a plurality of fourth connection lines; wherein lengths of the plurality of fourth connection lines are longer than lengths of the plurality of third connection lines, and delay amount of the fourth clock signal is greater than delay amount of the third clock signal. Allowable Subject Matter Claims 2-4, 6, 7, and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang describes a signal sampling circuit. Stuijt describes an apparatus for monitoring performance of a circuit. Shaetfer describes a memory controller with staggered request signal output. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIBIN CHEN/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Dec 27, 2024
Application Filed
May 27, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.2%)
2y 3m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1031 resolved cases by this examiner. Grant probability derived from career allowance rate.

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