DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on 02/25/2026 has been entered Claim 20 has been canceled. Claims 1, 3, 6, and 19 have been amended. Claims 1-19 are pending.
Response to Arguments
Applicant's arguments filed 02/25/2026 have been fully considered but they are not persuasive.
Regarding claim 11, applicant argues on pages 9-10 of the Remarks that Applicant has incorporated claim 20 into independent claim 11. Since the subject matter of claim 20 has been acknowledged as an allowable subject matter over the art of record (page 12 of the Office Action), the currently presented claim 11 is allowable.
In response to the applicant’s argument, examiner respectfully disagrees. Previous claim 20 describes, “a second capacitor, electrically connected between a control terminal of the driving transistor and the scan transistor.” The claim language incorporated into claim 11 describes, “a first capacitor, electrically connected between a control terminal of the driving transistor and the scan transistor” Examiner has introduced a new ground(s) of rejection made in view of Hung et al (US Pub. 20200357332).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim describes that, “a second capacitor, electrically connected between the second terminal of the driving transistor and the control terminal of the driving transistor” Fig. 4 and paragraph 51 discloses otherwise.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gai et al (CN 116189618) in view of Li et al (US Pub. 20210158755).
Regarding claim 1, Gai discloses:
A display device, (at least refer to fig. 1 and paragraph 63. Describes an OLED display panel) comprising:
A pixel circuit, (at least refer to fig. 1 and paragraph 63. Describes the display panel comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels 01) comprising:
A driving transistor, (at least refer to fig. 1, 5 and paragraph 85. Describes the driving module 21 comprises a first transistor T1);
A light-emitting control transistor, electrically connected to a first voltage terminal and the driving transistor, and receiving a light-emitting control signal, (at least refer to fig. 1 and paragraph 59. Describes the gate of the fifth transistor T5 and the sixth transistor T6 is connected with the light emitting control signal EM. The fifth transistor T5, the first transistor T1, the sixth transistor T6 and the light emitting device 1 sequentially connected between the first power supply line Vdd and the second power supply line Vss); and
A light-emitting element, electrically connected to a second voltage terminal and the driving transistor, wherein a voltage value of the second voltage terminal is lower than a voltage value of the first voltage terminal, (at least refer to fig. 1, 5 and paragraph 79. Describes the second end of the light emitting device 1 is electrically connected to the second power line Vss. Fig. 5 depicts Vss lower than Vdd at t3)
Wherein the voltage value of the second voltage terminal in a compensation stage of the pixel circuit is different from the voltage value of the second voltage terminal in a light-emitting stage of the pixel circuit, (at least refer to fig. 1, 5 and paragraph 27. Describes the second end of the light emitting device is electrically connected with the second power supply line, the second power supply line is used for the initialization stage and data writing and threshold compensation stage, transmitting the second voltage to the second end of the light emitting device, and further used for the light emitting stage, transmitting the first voltage to the second end of the light emitting device. Fig. 5 depicts Vss in period t2 as having high value than Vss in period t3 having low value).
Gai does not disclose:
Wherein a voltage value of the light-emitting control signal in the compensation stage of the pixel circuit is a same as voltage value of the light-emitting control signal in a reset stage different from the compensation stage of the pixel circuit.
Li teaches:
Wherein a voltage value of the light-emitting control signal in the compensation stage of the pixel circuit is a same as voltage value of the light-emitting control signal in a reset stage different from the compensation stage of the pixel circuit, (at least refer to fig. 11-13 and paragraph 136. Describes through the control of related control signals, the initialization module 10, the data write module 20, and the threshold compensation module 30 may all turn off and the light emission control module (51 and 52) turns on, so that at the data retention stage, the initialization period a and the data write period b are closed and the light-emitting element 60 is driven to emit light under the control of the light emission control signal Emit to enter the light-emitting period c).
The two references are analogous art because they are related with the same field of invention of display panel.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate same voltage value of the light-emitting control signal in a initialization stage and the compensation stage as taught by Li with the display device as disclose by Gai. The motivation to combine the reference of Li is to drive the emitting light with the retained data voltage, thereby improving picture display quality and effect.
Claim(s) 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gai et al (CN 116189618) in view of Hung et al (US Pub. 20200357332).
Regarding claim 11, Gai discloses:
A display device, (at least refer to fig. 1 and paragraph 63. Describes an OLED display panel) comprising:
A pixel circuit, (at least refer to fig. 1 and paragraph 63. Describes the display panel comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels 01) comprising:
A light-emitting control transistor, (at least refer to fig. 1 and paragraph 59. Describes the gate of the fifth transistor T5 and the sixth transistor T6 is connected with the light emitting control signal EM);
A driving transistor, electrically connected to a first voltage terminal and the light-emitting control transistor, (at least refer to fig. 1, 5 and paragraph 85. Describes the driving module 21 comprises a first transistor T1);
A light-emitting element, electrically connected to a second voltage terminal and the light-emitting control transistor, wherein a voltage value of the second voltage terminal is less than a voltage value of the first voltage terminal, (at least refer to fig. 1, 5 and paragraph 79. Describes the second end of the light emitting device 1 is electrically connected to the second power line Vss. Fig. 5 depicts Vss lower than Vdd at t3);
A scan transistor, electrically connected to the driving transistor and receiving a scan signal, (at least refer to fig. 1, 5 and paragraph 59. Describes wherein the gate of the second transistor T2 and the third transistor T3 is connected to the first scanning signal S1. The second transistor T2 is further connected with the data line Vdata) ; and
Wherein a voltage value of the scan signal in a reset stage of the pixel circuit is a same as the voltage value of the scan signal in a scan stage of the pixel circuit, (at least refer to fig. 1, 5 and paragraphs 82-83. Describes the scanning signal S1 is a signal for controlling the conduction of the compensation module 22, for example, a low level, and the control compensation module 22 is turned on. Para. 83, describes: The scanning signal S1 is a signal for controlling the conduction of the compensation module 22, for example, a low level, and the control compensation module 22 is turned on. Fig. 5 depicts S1 as lower level at t1 and between t2-t3).
Gai does not disclose:
a first capacitor, electrically connected between a control terminal of the driving transistor and the scan transistor
Hung teaches:
a first capacitor, electrically connected between a control terminal of the driving transistor and the scan transistor, (at least refer to fig. 2 and paragraph 35. Describes a first terminal of the seventh switch 244 is configured to receive a second data signal D2 from the data line 260. A second terminal of the seventh switch 244 is coupled with the third node N3. A control terminal of the seventh switch 244 is configured to receive a sixth control signal S6. The second capacitor 246 is coupled between the second node N2 and the third node N3. Para. 37, describes: the plurality of switches and the driving transistor 212)
The two references are analogous art because they are related with the same field of invention of display panel.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a capacitor between the control terminal of the driving transistor and the scan transistor as taught by Hung with the display device as disclose by Gai. The motivation to combine the reference of Hung is to measure the voltage difference between the two terminals.
Regarding claim 2, Gai discloses:
Wherein the voltage value of the second voltage terminal in the compensation stage is greater than the voltage value of the second voltage terminal in the light-emitting stage, (at least refer to fig. 1, 5 and paragraph 27. Describes the second end of the light emitting device is electrically connected with the second power supply line, the second power supply line is used for the initialization stage and data writing and threshold compensation stage, transmitting the second voltage to the second end of the light emitting device, and further used for the light emitting stage, transmitting the first voltage to the second end of the light emitting device).
Regarding claim 3, Gai discloses:
Wherein the voltage value of the second voltage terminal in the reset stage of the pixel circuit is different from the voltage value of the second voltage terminal in the light-emitting stage, (at least refer to fig. 1, 5 and paragraphs 82, 84. Describes the second power supply line Vss at the initialization stage t1 is high level, can avoid the light emitting device 1 is lighted. Para. 84, describes: the second power supply line Vss for the light emitting stage t3, the first voltage to the second end of the light emitting device 1, so as to ensure that the light emitting device 1 can be normally illuminated).
Regarding claim 4, Gai discloses:
Wherein the voltage value of the second voltage terminal in the reset stage is a same as the voltage value of the second voltage terminal in the compensation stage, (at least refer to fig. 1, 5 and paragraphs 82-83. Describes the second power supply line Vss at the initialization stage t1 is high level, can avoid the light emitting device 1 is lighted. Para. 83, describes: the second power supply line Vss for the data writing and threshold compensation stage t2, transmitting the second voltage to the second end of the light emitting device 1, avoiding the light emitting device 1 is lighted by mistake).
Regarding claim 5, Gai discloses:
Wherein the pixel circuit further comprises: a compensation transistor, electrically connected between a control terminal of the driving transistor and a first terminal of the driving transistor, (at least refer to fig. 1 and paragraph 85. Describes the first electrode of the third transistor T3 is electrically connected with the first electrode of the first transistor T1, the second electrode of the third transistor T3 is electrically connected with the second electrode of the first transistor T1).
Regarding claim 6, Gai discloses:
Wherein: a first terminal of the light-emitting control transistor is electrically connected to the first voltage terminal, a second terminal of the light-emitting control transistor is electrically connected to a second terminal of the driving transistor, and a control terminal of the light-emitting control transistor receives the light-emitting control signal, (at least refer to fig. 1 and paragraph 85. Describes the first electrode of the fifth transistor T5 is electrically connected with the first power supply line Vdd, the second electrode of the fifth transistor T5 is electrically connected with the first electrode of the first transistor T1, the grid electrode of the fifth transistor T5 is connected with the light emitting control signal EM).
Regarding claim 7, Gai discloses:
Wherein the pixel circuit further comprises: a scan transistor, wherein a first terminal of the scan transistor receives a data signal, a second terminal of the scan transistor is electrically connected to a second terminal of the driving transistor, and a control terminal of the scan transistor receives a scan signal, (at least refer to fig. 1 and paragraphs 59, 85. Describes wherein the gate of the second transistor T2 and the third transistor T3 is connected to the first scanning signal S1, the second transistor T2 is further connected with the data line Vdata. Para. 85, describes: the first electrode of the second transistor is electrically connected with the second electrode of the first transistor).
Regarding claim 8, Gai discloses:
Wherein the first terminal of the driving transistor is electrically connected to the light-emitting element, (at least refer to fig. 1 and paragraph 59. Describes the fifth transistor T5, the first transistor T1, the sixth transistor T6 and the light emitting device 1 sequentially connected between the first power supply line Vdd and the second power supply line Vss).
Regarding claim 9, Gai discloses:
Wherein the pixel circuit further comprises: a capacitor, electrically connected between a control terminal of the driving transistor and a first terminal of the light-emitting control transistor, (at least refer to fig. 1 and paragraph 85. Describes the first end of the storage capacitor Cst is electrically connected with the gate electrode of the first transistor T1, the second end of the storage capacitor Cst is electrically connected with the first power supply line Vdd).
Regarding claim 10, Gai discloses:
Wherein the pixel circuit further comprises: a reset transistor, wherein a first terminal of the reset transistor receives a reset voltage, a second terminal of the reset transistor is electrically connected to a control terminal of the driving transistor, and a control terminal of the reset transistor receives a reset signal, (at least refer to fig. 1 and paragraph 85. Describes the first electrode of the fourth transistor T4 is electrically connected with the data line Vdata, the second electrode of the fourth transistor T4 is electrically connected with the first electrode of the first transistor T1, the grid electrode access data of the fourth transistor T4 is written into the control signal DR).
Regarding claim 12, Gai discloses:
Wherein the voltage value of the scan signal in a light-emitting stage of the pixel circuit is different from the voltage value of the scan signal in the scan stage, (at least refer to fig. 1, 5 and paragraphs 82, 84. Describes the scanning signal S1 is a signal for controlling the conduction of the compensation module 22, for example, a low level, and the control compensation module 22 is turned on. Para. 84, describes: The scanning signal S1 is a signal for controlling the compensation module 22 to be turned off, for example, a high level, and the control compensation module 22 is turned off. Fig. 5 depicts S1 higher level at t3 and lower level between t2-t3).
Regarding claim 13, Gai discloses:
Wherein the voltage value of the scan signal in the light-emitting stage is greater than the voltage value of the scan signal in the scan stage, (at least refer to fig. 1, 5 and paragraphs 82, 84. Describes the scanning signal S1 is a signal for controlling the conduction of the compensation module 22, for example, a low level, and the control compensation module 22 is turned on. Para. 84, describes: The scanning signal S1 is a signal for controlling the compensation module 22 to be turned off, for example, a high level, and the control compensation module 22 is turned off. Fig. 5 depicts S1 higher level at t3 and lower level between t2-t3).
Regarding claim 14, Gai discloses:
Wherein the voltage value of the scan signal in a compensation stage of the pixel circuit is the same as the voltage value of the scan signal in the scan stage, (at least refer to fig. 1, 5 and paragraph 83. Describes the scanning signal S1 is a signal for controlling the conduction of the compensation module 22, for example, a low level, and the control compensation module 22 is turned on. Fig. 5 depicts S1 as lower level at t2 and between t2-t3).
Regarding claim 15, Gai discloses:
Wherein the pixel circuit further comprises: a compensation transistor, electrically connected between a control terminal of the driving transistor and a first terminal of the driving transistor, (at least refer to fig. 1 and paragraph 85. Describes the first electrode of the third transistor T3 is electrically connected with the first electrode of the first transistor T1, the second electrode of the third transistor T3 is electrically connected with the second electrode of the first transistor T1).
Regarding claim 16, Gai discloses:
Wherein: the first terminal of the driving transistor is electrically connected to a first terminal of the light-emitting control transistor, and a second terminal of the driving transistor is electrically connected to the first voltage terminal, (at least refer to fig. 1 and paragraph 59. Describes the fifth transistor T5, the first transistor T1, the sixth transistor T6 and the light emitting device 1 sequentially connected between the first power supply line Vdd and the second power supply line Vss).
Regarding claim 17, Gai discloses:
Wherein: a second terminal of the light-emitting control transistor is electrically connected to the light-emitting element, and a control terminal of the light-emitting control transistor receives a light-emitting control signal, (at least refer to fig. 1 and paragraph 59. Describes the gate of the fifth transistor T5 and the sixth transistor T6 is connected with the light emitting control signal EM, the fifth transistor T5, the first transistor T1, the sixth transistor T6 and the light emitting device 1 sequentially connected between the first power supply line Vdd and the second power supply line Vss).
Regarding claim 18, Gai discloses:
Wherein the pixel circuit further comprises: a reset transistor, wherein a first terminal of the reset transistor receives a reset voltage, a second terminal of the reset transistor is electrically connected to the control terminal of the driving transistor, and a control terminal of the reset transistor receives a reset signal, (at least refer to fig. 1 and paragraph 85. Describes the first electrode of the fourth transistor T4 is electrically connected with the data line Vdata, the second electrode of the fourth transistor T4 is electrically connected with the first electrode of the first transistor T1, the grid electrode access data of the fourth transistor T4 is written into the control signal DR).
Regarding claim 19, Gai discloses:
Wherein the pixel circuit further comprises: a second capacitor, electrically connected between the second terminal of the driving transistor and the control terminal of the driving transistor, (at least refer to fig. 1 and paragraph 85. Describes the first end of the storage capacitor Cst is electrically connected with the gate electrode of the first transistor T1, the second end of the storage capacitor Cst is electrically connected with the first power supply line Vdd. Wherein the second terminal of the driving transistor is indirectly electrically connected to Vdd).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IFEDAYO B ILUYOMADE whose telephone number is (571)270-7118. The examiner can normally be reached Monday-Friday.
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/IFEDAYO B ILUYOMADE/Primary Examiner, Art Unit 2624 03/25/2026