Detailed Action
This action is in response to the application filed on 12/27/2024. Claims 1-26 are
pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-26 are rejected under 35 U.S.C 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 12, 15, and 19-26 are rejected under 35 U.S.C. 103 as being unpatentable over Poppe et al. (U.S. Publication No. 2021/0025938 A1), hereinafter referred to as Poppe, in view of Becht et al. (U.S. Publication No. 2021/0232471 A1), hereinafter referred to as Becht.
Regarding Claim 1, Poppe teaches:
A processor-implemented method for testing comprising:
accessing a testing environment, wherein the testing environment includes a target device domain, wherein the target device domain includes a trace encoder software device-under-test interface (SDI), and wherein the SDI is coupled to a device-under-test (DUT); ([0141]; regarding, “The automated test equipment 100 comprises an on-chip system test controller 110. The on-chip system test controller 110 comprises at least one debug interface or control interface 112 which is configured to communicate with the device under test 104.”; [0147]; regarding, “The automated test equipment 200 comprises an on-chip system test controller 210 which may, for example, correspond to the on-chip system test controller 110. Moreover, the automated test equipment 200 comprises a device under test interface 216 which may, for example, combine the functionality of interfaces 112, 114. The automated test equipment 200 further comprises one or more parametric test resources or analog test resources 220 and one or more digital test resources 230. The automated test equipment further comprises a development and debug environment 240.”; [0145]; regarding, “the automated test equipment 100 can optionally be supplemented by any of the features, functionalities and details disclosed herein, both individually and taken in combination.”);
inserting, into the SDI, a plurality of software access points, wherein the plurality of software access points allow observability, by the trace encoder, of one or more internal signals within the SDI; ([0170]; regarding, “The development and debug environment 240 may, for example, comprise a user interface to allow a software engineer to develop on-chip system test software and/or test programs.”; [0164]; regarding, “the on-chip system test controller may control and/or synchronize one or more digital test resources 230 which, for example, provide digital stimulus signals for testing the device under test and/or evaluate digital response signals from the device under test.”; [0151]; regarding, “it should be noted that signals provided by the debug interface 252 to the device under test or signals received by the debug interface 252 from the device under test may be variably allocated”);
programming, by a user, the SDI with one or more modification instructions, wherein the one or more modification instructions cause the SDI to alter a response to the DUT, and wherein the one or more modification instructions are based on a test instruction set architecture (TISA); ([0161]; regarding, “the data received from the device under test may characterize a test execution and may, for example, describe characteristics of signals received by the device under test (like, for example, a signal-to-noise ratio, a bit-error-rate, or the like)… the adaptation of the test flow may be performed by the application specific routines provided by the user… different concepts are possible for adapting the test flow execution in dependence on data received from the device under test.”; [0155]; regarding, “the individual on-chip system tests may, for example, define steps (or substeps) of an overall test procedure executed for testing the device under test.”);
sending, by the user to the SDI, a test sequence, wherein the test sequence causes the SDI to send one or more communications to the DUT; ([0155]; regarding, “the on-chip system test controller 210 may perform a high degree of interaction and communication with the device under test… the on-chip system test controller 210 may upload one or more programs and/or test parameter sets to the device under test, wherein the debug interface 252 and/or the control interface 254 and/or the high bandwidth interface 256 may be used to upload one or more programs and/or test parameter sets to the device under test via the device under test interface 216.”);
receiving, by the SDI, one or more replies from the DUT, wherein the one or more replies are responsive to the test sequence; ([0160]; regarding, “the on-chip system test controller 210 may also receive commands and/or control information from the device under test via one of the interfaces 252, 254, 256 and react to said commands and/or control information… the device under test may request an adaptation of certain test conditions… and the on-chip system test controller 210 may respond to such commands or control information...”)
responding, by the SDI, to the one or more replies from the DUT, wherein the responding includes one or more additional communications to the DUT, and wherein the responding is based on the one or more modification instructions; ([0161]; regarding, “the on-chip system test controller 210 may also receive data from the device under test… the on-chip system test controller may also use the data received from the device under test in order to adapt a test execution flow in dependence on the data… the adaptation of the test flow may be performed by the application specific routines provided by the user.”);
obtaining, by the SDI, one or more additional replies from the DUT, wherein the one or more additional replies are responsive to the responding; ([0161]; regarding, “the on-chip system test controller 210 may also receive data from the device under test… may use said data to decide whether the device under test fulfils the requirement (i.e., to decide whether the device under test should be classified as being acceptable or as failing).”);
Poppe fails to explicitly disclose but Becht teaches:
and creating, by the trace encoder, a logic trace, wherein the logic trace includes one or more states of the plurality of software access points, and wherein the creating is based on the sending, the receiving, the responding, and the obtaining. ([0018]; regarding, “Information repository 114 is a data repository that can store, gather, compare, and/or combine information… information repository 114 includes trace data for the external interfaces of DUT 132. For example, the trace data may include Peripheral Component Interconnect Express (PCIe) trace data that are sent to, and received from, DUT 132.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe with the teachings of Becht. Doing so could reduce development costs (Becht, [0008]).
Regarding Claim 2, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
accessing, by the user, the logic trace, wherein the logic trace is stored in a trace memory. (Becht, [0018]; regarding, “information repository 114 includes trace data for the external interfaces of DUT 132. For example, the trace data may include Peripheral Component Interconnect Express (PCIe) trace data that are sent to, and received from, DUT 132.”; [0028]; regarding, “the user via a user interface on computing device 110 scans delayed buffer 204 via emulation capture program 112.”; [0031]; regarding, “emulation capture program 112 creates delayed buffer 204 in information repository 114”; [0037]; regarding, “emulation capture program 112 uses scan engine 212 and clock controller 214 to enable the user via the user interface to view trace or AET events.”).
Regarding Claim 4, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
setting a state of the SDI, wherein the setting is accomplished by the plurality of software access points, and wherein the setting preconditions the SDI for the responding. (Poppe, [0161]; regarding, “the on-chip system test controller may also use the data received from the device under test in order to adapt a test execution flow… the adaptation of the test flow may be performed by the application specific routines provided by the user.”; [0164]; regarding, “the on-chip system test controller may control and/or synchronize one or more digital test resources 230 which, for example, provide digital stimulus signals for testing the device under test and/or evaluate digital response signals from the device under test.”; [0151]; regarding, “it should be noted that signals provided by the debug interface 252 to the device under test or signals received by the debug interface 252 from the device under test may be variably allocated.”).
Regarding Claim 12, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
wherein the SDI includes a PCI-Express (PCI-E) controller. (Poppe, [0285]; regarding, “The on-chip-system test controller further comprises… a PCIe physical interface 1652”).
Regarding Claim 15, Poppe in view of Becht teaches the method of claim 12 as referenced above. Poppe in view of Becht further teaches:
wherein the PCI-express controller comprises a PCI-E endpoint device. (Poppe, [0141]; regarding, “The on-chip system test controller 110 comprises at least one debug interface or control interface 112 which is configured to communicate with the device under test 104. Moreover, the on-chip system test controller 110 optionally also comprises at least one high bandwidth interface 114 (which may, for example, be a USB interface, or a PCI interface, or a PCI-express interface, or a PCI-express compliant interface, or a thunderbolt interface, or an Ethernet interface, or an IEEE-1394 interface, or a SATA interface or an IEEE-1149 interface or an IEEE-1500 interface, or an IEEE-1687 interface).”; [0285]; regarding, “the optional PCIe physical interface and the optional USB physical interface may be coupled to high speed pins (e.g., LVDS pins) of the field programmable gate array 1640.”).
Regarding Claim 19, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
wherein the SDI includes an ethernet controller. (Poppe, [0141]; regarding, “The on-chip system test controller 110 comprises at least one debug interface or control interface 112 which is configured to communicate with the device under test 104. Moreover, the on-chip system test controller 110 optionally also comprises… an Ethernet interface...”).
Regarding Claim 20, Poppe in view of Becht teaches the method of claim 19 as referenced above. Poppe in view of Becht further teaches:
wherein the DUT comprises an ethernet controller. (Poppe, [0141]; regarding, “The on-chip system test controller 110 comprises at least one debug interface or control interface 112 which is configured to communicate with the device under test 104. Moreover, the on-chip system test controller 110 optionally also comprises… an Ethernet interface...”).
Regarding Claim 21, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
wherein the SDI includes a USB controller. (Poppe, [0141]; regarding, “The on-chip system test controller 110 comprises at least one debug interface or control interface 112 which is configured to communicate with the device under test 104. Moreover, the on-chip system test controller 110 optionally also comprises… a USB interface...”).
Regarding Claim 22, Poppe in view of Becht teaches the method of claim 21 as referenced above. Poppe in view of Becht further teaches:
wherein the DUT comprises a USB controller. (Poppe, [0141]; regarding, “The on-chip system test controller 110 comprises at least one debug interface or control interface 112 which is configured to communicate with the device under test 104. Moreover, the on-chip system test controller 110 optionally also comprises… a USB interface...”).
Regarding Claim 23, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
wherein the logic trace includes one or more inputs and/or outputs to the SDI.
(Poppe, [0189]; regarding, “The test system 620, which is typically also part of the automated test equipment, comprises one or more on-chip system test controllers 622”; [0190]; regarding, “The test system 620 also comprises on or more digital input/output instruments 624”), (Becht, [0012]; regarding, “creating a copy of the design under test (DUT) with a delayed buffer that captures the inputs into the original DUT. Once the copy of the DUT is created, along with the delayed buffer, the operating system or application is run as normal. The DUT will receive the inputs and generate the corresponding output. At the same time, the delayed buffer is being loaded, and the copy of the DUT receives the inputs and generates the same corresponding output as the DUT, but delayed in time.”; [0018]; regarding, “Information repository 114 includes, but is not limited to, user data, event data, FPGA configuration data, delayed buffer storage data, data associated with the normal test program, other data that is received by emulation capture program 112 from one or more sources, and data that is created by emulation capture program 112.”).
Regarding Claim 24, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
wherein the test sequence comprises a compliance test. (Poppe, [0332]; regarding, “Furthermore, embodiments according to the described invention optionally enable future solutions…”; [0333]; regarding, “By defining standard interfaces, the invention enables an automated flow of SOC verification tests (that are implemented as embedded software) to a test environment for effective execution and qualification of each test”).
Claims 25-26 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Poppe et al. (U.S. Publication No. 2021/0025938 A1), hereinafter referred to as Poppe, in view of Becht et al. (U.S. Publication No. 2021/0232471 A1), hereinafter referred to as Becht, in further view of Varadarajan et al. (U.S. Publication No. 2023/0324456 A1), hereinafter referred to as Varadarajan.
Regarding Claim 3, Poppe in view of Becht teaches the method of claim 2 as referenced above. Poppe in view of Becht fails to explicitly disclose but Varadarajan teaches:
comparing the logic trace to an expected logic trace. ([0028]; regarding, “…selects a subset of values from the plurality of memory circuits, and determines a logic signature based on the subset of values. Example ATE circuitry compares the logic signature with an expected signature…”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Varadarajan. Doing so could increase observability, by increasing the observable memory values in a DUT (Varadarajan, [0037, 0109]).
Claims 5-9, 13-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Poppe et al. (U.S. Publication No. 2021/0025938 A1), hereinafter referred to as Poppe, in view of Becht et al. (U.S. Publication No. 2021/0232471 A1), hereinafter referred to as Becht, in further view of Halleck et al. (U.S. Publication No. 2016/0179740 A1), hereinafter referred to as Halleck.
Regarding Claim 5, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht further teaches:
wherein the programming comprises converting, by a code exerciser within the target device domain, the one or more modification instructions...to the SDI (Poppe, [0170]; regarding, “The development and debug environment 240 may, for example, comprise a user interface to allow a software engineer to develop on-chip system test software and/or test programs…”; [0155]; regarding, “the on-chip system test controller 210 may upload one or more programs and/or test parameter sets to the device under test, wherein the debug interface 252 and/or the control interface 254 and/or the high bandwidth interface 256 may be used to upload one or more programs and/or test parameter sets…”).
Poppe in view of Becht fail to explicitly disclose but Halleck teaches:
wherein the programming comprises converting, by a code exerciser within the target device domain, the one or more modification instructions into one or more packetized communications to the SDI ([0031]; regarding, “Packets can be used to communicate information between components.”; [0169]; regarding, “core 1201 is associated…instructions executable on processor 1200.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Halleck. Doing so could accelerate and execute applications more efficiently (Halleck, [0184]).
Regarding Claim 6, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht fail to explicitly disclose but Halleck teaches:
wherein the test sequence comprises one or more opcodes from within the TISA. ([0169]; regarding, “machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 1225 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Halleck. Doing so could accelerate and execute applications more efficiently (Halleck, [0184]).
Regarding Claim 7, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht fail to explicitly disclose but Halleck teaches:
wherein the TISA includes one or more opcodes for control and testing of the DUT. ([0169]; regarding, “Decode logic 1225 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders 1225, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 1225, the architecture or core 1201 takes specific, predefined actions to perform tasks associated with the appropriate instruction.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Halleck. Doing so could accelerate and execute applications more efficiently (Halleck, [0184]).
Regarding Claim 8, Poppe in view of Becht in further view of Halleck teaches the method of claim 7 as referenced above. Poppe in view of Becht in further view of Halleck further teaches:
storing, in an instruction memory, the one or more modification instructions. (Poppe, [0155]; regarding, “the one or more programs and/or test parameter sets to be uploaded to the device under test may be taken from the software repository 260, which may be part of the on-chip system test controller, and which may store dut software.”).
Regarding Claim 9, Poppe in view of Becht in further view of Halleck teaches the method of claim 8 as referenced above. Poppe in view of Becht in further view of Halleck further teaches:
fetching, by a fetch and decode unit, the one or more modification instructions, wherein the fetching includes decoding the one or more modification instructions. (Halleck, [0173]; regarding, “A trace cache—a type of instruction cache—instead may be coupled after decoder 1225 to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).”).
Regarding Claim 13, Poppe in view of Becht teaches the method of claim 12 as referenced above. Poppe in view of Becht further fail to explicitly disclose but Halleck teaches:
wherein the PCI-express controller comprises a PCI-E root complex. ([0026]; regarding, “controller hub 115 can include a root hub, root complex, or root controller, such as in a PCIe interconnection hierarchy.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Halleck. Doing so could accelerate and execute applications more efficiently (Halleck, [0184]).
Regarding Claim 14, Poppe in view of Becht in further view of Halleck teaches the method of claim 13 as referenced above. Poppe in view of Becht in further view of Halleck further teaches:
wherein the DUT comprises a PCI-E endpoint device. (Poppe, [0141]; regarding, “The on-chip system test controller 110 comprises at least one debug interface or control interface 112 which is configured to communicate with the device under test 104. Moreover, the on-chip system test controller 110 optionally also comprises at least one high bandwidth interface 114 (which may, for example, be a USB interface, or a PCI interface, or a PCI-express interface, or a PCI-express compliant interface, or a thunderbolt interface, or an Ethernet interface, or an IEEE-1394 interface, or a SATA interface or an IEEE-1149 interface or an IEEE-1500 interface, or an IEEE-1687 interface).”).
Regarding Claim 16, Poppe in view of Becht teaches the method of claim 15 as referenced above. Poppe in view of Becht further teaches:
wherein the DUT comprises a PCI-E… (Poppe, [0286]; regarding, “the PCIe physical interface 1652 and of the USB physical interface 1654 may, for example, be coupled to a DUT interface”);
Poppe in view of Becht fail to explicitly disclose but Halleck teaches:
wherein the DUT comprises a PCI-E root complex. ([0026]; regarding, “controller hub 115 can include a root hub, root complex, or root controller, such as in a PCIe interconnection hierarchy.”; [0028]; regarding, “Switch/bridge 120 routes packets/messages from device 125 upstream, i.e. up a hierarchy towards a root complex, to controller hub 115 and downstream, i.e. down a hierarchy away from a root controller, from processor 105 or system memory 110 to device 125.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Halleck. Doing so could accelerate and execute applications more efficiently (Halleck, [0184]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Poppe et al. (U.S. Publication No. 2021/0025938 A1), hereinafter referred to as Poppe, in view of Becht et al. (U.S. Publication No. 2021/0232471 A1), hereinafter referred to as Becht, in further view of
Swoboda et al. (U.S. Publication No. 2006/0273944 A1), hereinafter referred to as Swoboda.
Regarding Claim 10, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht fails to explicitly disclose but Swoboda teaches:
wherein the logic trace comprises one or more 64-bit words. ([0072]; regarding, “the PU stores a number of trace transmission packets in 64-bit words”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Swoboda. Doing so could reduce bandwidth requirements (Swoboda, [0265]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Poppe et al. (U.S. Publication No. 2021/0025938 A1), hereinafter referred to as Poppe, in view of Becht et al. (U.S. Publication No. 2021/0232471 A1), hereinafter referred to as Becht, in further view of Todd et al. (U.S. Publication No. 2003/0212937 A1), hereinafter referred to as Todd.
Regarding Claim 11, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht fails to explicitly disclose but Todd teaches:
wherein the logic trace includes a count, wherein the count records a number of times a same packetized communication occurred between the SDI and the DUT. ([0027]; regarding, “The software may provide such data as memory snapshots, counter values, internal system variables, etc. The logic data packets can also contain processor op-code execution flow associated with a plurality of processors that are asynchronous or synchronous processing units that are independent of or dependent on op-code instructions to be measured by trace logic analysis system 108”; [0036]; regarding, “FIGS. 1 and 2 illustrate a system designed to request and receive sampled state-based logic data via network packets, it should be noted that the present invention's system is preferably bi-directional, allowing for modification of data (such as memory snapshots, counter values, internal system variables, etc.).”; [0042]; regarding, “…this trace information could be transmitted "on-demand" to the logic analysis device. One example of a purely software approach would be the monitoring of a counter variable…”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Todd. Doing so could increase debug usability (Todd, [0041]).
Claim 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Poppe et al. (U.S. Publication No. 2021/0025938 A1), hereinafter referred to as Poppe, in view of Becht et al. (U.S. Publication No. 2021/0232471 A1), hereinafter referred to as Becht, in further view of De La Puente et al. (U.S. Publication No. 2024/0096432 A1), hereinafter referred to as Puente.
Regarding Claim 17, Poppe in view of Becht teaches the method of claim 1 as referenced above. Poppe in view of Becht fail to explicitly disclose but Puente teaches:
wherein the SDI includes a CXL controller. ([0046]; regarding, “exemplary system 100 for memory queue operations in testers to increase throughput in an ATE system”; [0074]; regarding, “FIG. 5 illustrates a block diagram of an exemplary electronic system 500, which may be used as a platform to implement and/or as a control system, e.g., system controller 110 and/or CPU 130”; [0045]; regarding, “It is to be appreciated that embodiments in accordance with the present invention are not limited to the illustrated PCIe embodiments. Rather, embodiments in accordance with the present invention are well suited to use with a wide range of other well-known computer expansion busses, including, for example, Compute Express Link (CXL)...”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Poppe and Becht with the teachings of Puente. Doing so could increase the maximum allowable PCIe trace length and allow for more flexibility in system design (Puente, [0050]).
Regarding Claim 18, Poppe in view of Becht in further view of Peunte teaches the method of claim 17 as referenced above. Poppe in view of Becht in further view of Puente further teaches:
wherein the DUT comprises a CXL controller. ([0052]; regarding, “A plurality of devices under test (DUTs), e.g., DUT 150A to DUT 150N, are coupled to PCIe bus 145.”; [0074]; regarding, “FIG. 5 illustrates a block diagram of an exemplary electronic system 500, which may be used as a platform to implement and/or as a control system, e.g., system controller 110 and/or CPU 130”); [0045]; regarding, “It is to be appreciated that embodiments in accordance with the present invention are not limited to the illustrated PCIe embodiments. Rather, embodiments in accordance with the present invention are well suited to use with a wide range of other well-known computer expansion busses, including, for example, Compute Express Link (CXL)...”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATHEW GUSTAFSON whose telephone number is (571)272-5273. The examiner can normally be reached Monday-Friday 8:00-4:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571) 272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.D.G./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113