DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 9, and 19-20 are objected to because of the following informalities:
Claim 1 line 8- insert --of-- after “invalidation” to improve clarity
Claim 9 line 8- inserts a comma after “executing” and after “thread” to improve grammar
Claim 9 line 10- insert --of-- after “invalidation” to improve clarity
Claims 19 and 20 both refer to a proper subset of the plurality of hardware threads. Examiner suggests amending claim 19 to refer to a first proper subset and claim 20 (which depends on claim 19) to refer to a second proper subset.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-7 and 9-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “a value of the first source operand” in line 1. It is unclear whether this is the same as the value of the first source operand introduced in claim 1 or if they are different. For purposes of examination, they will be interpreted to be the same.
Claims 5-7, 12-15, and 18 recite the same limitation and are rejected for the same reason. For purposes of examination the same interpretation will also be applied.
Claim 4 recites “a value of the second source operand” in line 2. It is unclear whether this is the same as the value of the second source operand introduced in claim 1 or if they are different. For purposes of examination, they will be interpreted to be the same.
Claims 5-7, 12-15, and 18 recite the same limitation and are rejected for the same reason. For purposes of examination the same interpretation will also be applied.
Claim 9 recites “in some examples, an identifier of a second source operand” in lines 6-7. The phrase "in some examples" renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d). For purposes of examination, the claim will be interpreted as requiring an identifier of a second source operand.
Claim 17 recites the same limitation and is rejected for the same reason. For purposes of examination the same interpretation will also be applied.
Claim 18 recites “a first hardware thread” in line 1. It is unclear if this is the same as the first hardware thread introduced in claim 17 or if they are different. For purposes of examination, they will be interpreted as the same.
Claims dependent on a rejected base claim are further rejected based on their dependence.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 18 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 18 recites “wherein the execution circuitry of a first hardware thread is to further execute the decoded instruction to invalidate one or more TLB entries in accordance with a value of the first source operand and/or a value of the second source operand.” However, this feature is already required in claim 17, which claim 18 depends from. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-11, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Guthrie US 2017/0177422 in view of Slegel US 2017/0017577.
Regarding claim 1, Guthrie teaches:
1. An apparatus comprising:
decoder circuitry to decode an instance of a single instruction ([0036] discloses a processor core including execution units which execute instructions including a Translation Lookaside Buffer Invalidate Entry TLBIE instruction, which would inherently include decoder circuitry that decodes the instructions for execution); and
execution circuitry of a first hardware thread to execute the decoded instruction ([0036]: any hardware thread that includes the TLBIE instruction is a first hardware thread and the corresponding execution unit that executes the instruction is execution circuitry) to broadcast a command to a plurality of hardware threads to cause an invalidation one or more translation lookaside buffer (TLB) entries for each of the plurality of hardware threads ([0048] discloses that the TLBIE instruction generates a corresponding TLBIE request/command that invalidates translation entries in all translation structures throughout the processing system and Figs. 5-10 disclose broadcasting the TLBIE request to the L2 cache of the initiating core and those of all other cores (see [0059]-[0060]) so that the translation sequencer in each core can invalidate the translation entries of the TLBIE request (see Fig. 9, 904), that is, the TLBIE request is broadcasted to the cores to cause invalidation of TLB entries used by/for the threads and the broadcast is to the threads of the cores in that the TLBIE request marks memory referent requests of the -threads that have had their target addresses translated by an entry invalidated by the TLBIE request (see Fig. 9, 906 and [0066])).
Guthrie does not teach:
wherein the instance of the single instruction includes fields to indicate one or more operations to perform, an identifier of a first source operand, and an identifier of a second source operand;
executing the instruction according to the fields to cause an invalidation of TLB entries in accordance with a value of the first source operand and/or a value of the second source operand.
However, Slegel teaches:
an instruction that includes fields to indicate one or more operations to perform, an identifier of a first source operand, and an identifier of a second source operand ([0065] and Fig. 6: Invalidate Dynamic Address Translation Table Entry IDTE includes fields to indicate an opcode (i.e., one or more operations to perform) and registers, any one of the registers R1-R3 is an identifier of a first source operand and any other of the registers is an identifier of a second source operand);
executing the instruction according to the fields to cause an invalidation of TLB entries in accordance with a value of the first source operand and/or a value of the second source operand ([0064]-[0068] describes executing the instruction according to its opcode and registers R1-R3 to invalidate TLB entries in accordance with the values of the registers R1-R3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the TLBIE invalidate instruction of Guthrie with the IDTE instruction of Slegel. One of ordinary skill in the art would have been motivated to make this modification to enable invalidating/clearing a range of TLB entries with one instruction, which would reduce code size.
Claim 9 is directed to a non-transitory machine-readable medium performing steps corresponding to the apparatus of claim 1 and is rejected for the same reasons as claim 1.
Claim 17 is directed to a system comprising the decoder circuitry and execution circuitry of claim 1 and is rejected for the same reasons as claim 1. Additionally, claim 17 recites a memory external to a processor core to store an instance of a single instruction, which is taught by Guthrie [0030] which discloses system memory that stores instructions accessed by a processor core.
Claim 18 is directed to the same execution circuitry as the apparatus of claim 1 and the system of claim 17 and is rejected for the same reason as claim 1.
Regarding claim 2, Guthrie in view of Slegel teaches:
2. The apparatus of claim 1, wherein at least a proper subset of the plurality of hardware threads are on a different core than the execution circuitry of the first hardware thread (Guthrie [0032] discloses that each core may execute multiple threads, which indicates that a proper subset of the threads may be on a different core than the core of the first thread that initiates the invalidation).
Claim 10 is directed to a non-transitory machine-readable medium corresponding to the apparatus of claim 2 and is rejected for the same reasons as claim 2.
Claim 19 is directed to a system corresponding to the apparatus of claim 2 and is rejected for the same reasons as claim 2.
Regarding claim 3, Guthrie in view of Slegel teaches:
3. The apparatus of claim 1, wherein at least a proper subset of the plurality of hardware threads are on a same core as the execution circuitry of the first hardware thread (Guthrie [0032] discloses that each core may execute multiple threads, which indicates that a proper subset of the threads may be on the same core as the thread that initiates the invalidation).
Claim 11 is directed to a non-transitory machine-readable medium corresponding to the apparatus of claim 3 and is rejected for the same reasons as claim 3.
Claim 20 is directed to a system corresponding to the apparatus of claims 2 and 3 and is rejected for the same reasons as claims 2 and 3.
Regarding claim 7, Guthrie in view of Slegel teaches:
7. The apparatus of claim 1, wherein when a value of the first source operand is a non-zero value and a value of the second source operand is a non-zero value, all entries of the TLB that match the non-zero value of the first source operand and are a part of an address space identified by the non-zero value of the second source operand are invalidated (Slegel [0076]-[0077] discloses using the segment index of R2 (i.e., a non-zero value of the second source operand) with the segment table origin of R1 (i.e., a non-zero value of the first source operand) to select an entry to invalidate, that is, all entries of the TLB that match the segment table origin of R1 and segment index of R2 are invalidated).
Claim 15 is directed to a non-transitory machine-readable medium performing steps corresponding to the apparatus of claim 7 and is rejected for the same reasons as claim 7.
Regarding claim 8, Guthrie in view of Slegel teaches:
8. The apparatus of claim 1, wherein the execution circuitry is further to perform a fence operation to order all reads and writes (Guthrie [0036] discloses that the instructions executed by the execution units may include synchronization instructions and [0049] discloses that HWSYNC instruction 410 enforces a barrier that prevents any memory reference instructions (i.e., reads and writes) following it from executing until the TSYNC instruction preceding it has completed processing, which orders all reads and writes).
Claim 16 is directed to a non-transitory machine-readable medium performing steps corresponding to the apparatus of claim 8 and is rejected for the same reasons as claim 8.
Prior Art Considerations
Examiner notes that while no prior art rejection is given for claims 4-6 and 12-14, these claims are currently rejected under 112(b) and a not allowable at the current point. The following prior art considerations are given for these claims.
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claim, when a value of the first source operand is equal to zero and a value of the second source operand is equal to zero, all entries of the TLB are invalidated for all address spaces, as recited in claims 4 and 12.
The closest prior art of record was found to be Slegel US 2017/0017577. While Slegel teaches using an IDTE instruction to purge TLB entries, see [0091], and that all TLB entries may be purged, see [0064], Slegel does not teach purging all the TLB entries when a value of a first source operand of the instruction is equal to zero and a value of a second source operand of the instruction is equal to zero.
Further, the known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claim, wherein when a value of the first source operand is a zero value and a value of the second source operand is a non-zero value, all entries of the TLB that are in an address space identified by the non-zero value of the second source operand are invalidated, as recited in claims 5 and 13, or wherein when a value of the first source operand is a non-zero value and a value of the second source operand is a zero value, all entries of the TLB that match the non-zero value of the first source operand are invalidated, as recited in claims 6 and 14.
The closest prior art of record was found to be Slegel US 2017/0017577. While Slegel discloses an IDTE instruction including operands R1, R2, and R3 (see Fig. 6A), using the values in R1 and R2 to identify entries to invalidate, see [0076]-[0077], and that R3 may be zero, see [0068], Slegel does not teach all entries of the TLB that are in an address space identified by a non-zero value of a source operand are invalidated or that match a non-zero value of a source operand are invalidated as Slegel uses both R1 and R2 is identify entries to invalidate (i.e., there may be entries in address spaces identified by (or that match) R1 and not R2 or vice versa that are not invalidated).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2011/0153952 teaches a repeat invalidate TLB entry instruction that invalidates multiple TLB entries, see [0044]
US 2017/0286314 teaches invalidating a TLB in response to at least one TLB invalidation command, see Abstract
US 2015/0242319 teaches an invalidation command the invalidates a stored address translation by specifying a first address and an identifier, see Abstract. Further, the background at [0005] teaches flushing all stored address translations.
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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