Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
The IDS, filed 12/27/24, has been considered.
Claim Objections
Claim 7 is objected to because of the following informalities: the acronym CXL should be written out fully initially. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
As to claim 1, the limitation “determining a latency for processing of the request” lacks enablement. The disclosure does not specifically any step that determines a latency. The disclosure also does not provide any detail of how latency is calculated or what parameters are used in that calculation. The disclosure only indicates that throttling request traffic improves latency. The disclosure only determines the number of outstanding requests, which is compared to a threshold to determine if latency occurs. The disclosure indicates that latency is a condition that occurs if the number of outstanding requests exceed a threshold. No actual step for calculating/determine a latency is disclosed. Applicant must amend the claim to remove this limitation as it is not enabled by the disclosure. For purposes of examination, the Examiner will interpret that determining latency and determining whether it exceeding a threshold comprises determining whether the number of outstanding requests exceeding a threshold, leading to latency.
Independent claims 11 and 17 are similarly rejected for the same deficiency.
Dependent claims 2-10, 12-16, and 18-20 are rejected for incorporating the deficiency of parent claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 4, and 7-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 11-14 of U.S. Patent No. 11,593,024.
Claim(s) 1, 2, 4, 11-14 of U.S. Patent No. 11,593,024 contain(s) every element of claim(s) 1, 2, 4, and 7-10 of the instant application and as such anticipate(s) claim(s) 1, 2, 4, and 7-10 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example claim mapping between the current application and patent:
Current Application
A method, comprising:
providing a request, from a front-end of a memory sub-system, to a back-end of the memory sub-system;
deleting the request from a buffer of the front-end of the memory sub-system; responsive to deleting the request from the buffer and providing the request to the back-end, determining a latency for processing of the request in the back-end of the memory sub-system; and determining whether to provide a response to a host, based on a comparison of the latency to a latency threshold.
Patent 11,583,524
A method, comprising:
providing a request, from a front-end of a memory sub-system, to a processing device of the memory sub-system; deleting the request from a buffer of the front-end of the memory sub-system; responsive to deleting the request from the buffer, determining a first quantity of requests in the buffer;
responsive to deleting the request from the buffer, determining a second quantity of outstanding requests in the back-end of the memory sub-system; and determining whether to provide a response, including an indication of the quantity of requests in the buffer, to a host, based on a comparison of the second quantity of outstanding requests to a threshold.
The limitation “latency” in current claim 1 is read by “second quantity of outstanding requests” in the patent. Although the two uses different terminology, each represent a quantity that is being used in a comparison. Applicant is his own lexicographer and can name this quantity any thing he wishes. Since the patent includes all of the limitations of the current application, and more, the patent anticipates the current application.
Claims 2, 4, and 7-10 are similarly mapped to claims 2, 4, 11-14 in patent 11,593,024.
Claims 1-3, 5-10, 17, 19, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-10, 17, 19, and 20 of U.S. Patent No. 12,182,442.
Claim(s) 1-3, 5-10, 17, 19, and 20 of U.S. Patent No. 12,182,442 contain(s) every element of claim(s) 1-3, 5-10, 17, 19, and 20 of the instant application and as such anticipate(s) claim(s) 1-3, 5-10, 17, 19, and 20 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example claim mapping between the current application and patent:
Current Application
A method, comprising:
providing a request, from a front-end of a memory sub-system, to a back-end of the memory sub-system;
deleting the request from a buffer of the front-end of the memory sub-system;
responsive to deleting the request from the buffer and providing the request to the back-end, determining a latency for processing of the request in the back-end of the memory sub-system; and determining whether to provide a response to a host, based on a comparison of the latency to a latency threshold.
Patent 12,182,442
A method, comprising:
providing a request, from a front-end of a memory sub-system, to a back-end of the memory sub-system;
deleting the request from a buffer of the front-end of the memory sub-system; responsive to deleting the request from the buffer and providing the request to the back-end, determining a quantity of outstanding requests in the back-end of the memory sub-system; and determining whether to provide a response to a host, based on a comparison of the quantity of outstanding requests to a threshold.
The limitation “latency” in current claim 1 is read by “a quantity of outstanding requests” in the patent. Although the two uses different terminology, each represent a quantity that is being used in a comparison. Furthermore, there is a direct correlation between outstanding requests and latency. Applicant is his own lexicographer and can name this quantity anything he wishes. Since the patent includes all of the limitations of the current application, and more, the patent anticipates the current application.
Claims 2, 3, 5-10, 17, 19, and 20 are similarly mapped to claims 2, 3, 5-10, 17, 19, and 20 in patent 11,593,024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeddeloh (US20050172084).
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeddeloh (US20050172084).
As to claim 1, Jeddeloh teaches a method (method, abstract, 0008, 0010), comprising:
providing a request, from a front-end of a memory sub-system, to a back-end of the memory sub-system (receive request from processor 104, provide request to queue 204 to memory system 120; 0017, 0019, 0021, Fig. 1, 2);
deleting the request from a buffer of the front-end of the memory sub-system (requests are removed from queue 204 when they serviced by memory system; 0021); responsive to deleting the request from the buffer and providing the request to the back-end, determining a latency for processing of the request in the back-end of the memory sub-system (latency is time required to service data from system memory devices; 0004-0005; latency directly related to the number of outstanding requests in the queue; 0008-0010; determine number of outstanding requests issued to system memory; 0009, 0010, 0017, 0020-0025), and determining whether to provide a response to a host, based on a comparison of the latency to a latency threshold (compare number of outstanding requests with a threshold, if greater than threshold, latency occurs; abstract, 0010, 0004-0005, claims 2-5; determine and notify controller whether additional requests should be issued; 0021, 0024, 0032).
As to claim 2, Jeddeloh teaches, responsive to determining that the latency is greater than the latency threshold, refraining from providing the response (monitor number of outstanding requests, which is directly correlates to the latency (0004-0005, 0008-0010), if greater than a threshold, halt sending requests to system memory; 0024, 0032).
As to claim 3, Jeddeloh teaches, responsive to determining that a quantity of outstanding requests in the back-end is less than a threshold but greater than a different threshold after the quantity of outstanding requests had previously been greater than the threshold, refraining from providing the response (monitor outstanding requests; maintain between first and second threshold; halt sending requests if outside of this range; 0010, 0024, 0032).
As to claim 4, Jeddeloh teaches, responsive to determining that the latency is less than the latency threshold providing the response to the host (allow request to be sent to system memory when number of outstanding requests that correlates to the latency, is below the maximum threshold; 0023, 0024, 0032).
As to claim 5, Jeddeloh teaches, responsive to determining to provide the response, providing the response to the host, wherein the response indicates whether the host can provide additional requests to the memory sub-system based on a different quantity of requests of the buffer of the front end and a quantity of requests (monitor total number of outstanding requests and a threshold; 0023, 0024, 0032; issue resume signal to indicate that additional requests can be sent if number of outstanding request is below threshold; 0023, 0024, 0025, 0032).
As to claim 6, Jeddeloh teaches receiving the request at the front-end of the memory sub-system (receive memory request into request queue; Fig. 2, 0009, 0019).
As to claim 7, Jeddeloh teaches wherein the request is received from the host coupled to the memory sub-system via a CXL link (memory coupled to high speed interface; 0006-0007).
As to claim 8, Jeddeloh teaches storing, responsive to receipt of the request, the request in the buffer of the front-end of the memory sub-system (store requests in request queue; Fig. 2; 0009, 0019).
As to claim 9, Jeddeloh teaches, responsive to storing the request in the buffer, incrementing a different count representative of a different quantity of requests in the buffer (increase counter to track number of requests; 0022-0023).
As to claim 10, Jeddeloh teaches the response includes a count from the different count as the indication of the different quantity of requests in the buffer (track different read and write request counts; 0022, 0023, 0028).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeddeloh (US20050172084) in view of Thomas et al (US20150006630, “Thomas”).
As to claim 11, Jeddeloh teaches an apparatus (Fig 1, 0015-0017), comprising: a processing device of a front-end of a memory sub-system (system controller including a memory controller; 0015-0016), configured to: provide a request, from the front-end of the memory sub-system, to a back-end of the memory sub-system (receive request from processor 104, provide request to queue 204 to memory system 120; 0017, 0019, 0021, Fig. 1, 2); delete the request from a buffer of the processing device of the front-end of the memory sub-system (requests are removed from queue 204 when they serviced by memory system; 0021); responsive to deleting the request from the buffer and providing the request to the back-end, determine a latency for processing the request in the back-end (latency is time required to service data from system memory devices; 0004-0005; latency directly related to the number of outstanding requests in the queue; 0008-0010; determine number of outstanding requests issued to system memory; 0009, 0010, 0017, 0020-0025); responsive to deleting the request from the buffer and providing the request to the back-end, determine whether the latency is greater than a latency threshold (compare number of outstanding requests with a threshold; abstract, 0010, claims 2-5; determine and notify controller whether additional requests should be issued; 0021, 0024, 0032). Jeddeloh teaches tracking the number of requests in the queue and determining if the latency is greater than a threshold (from comparing the number of outstanding requests with a threshold; abstract, 0010, 0020-0025; claims 2-5) but does not specifically teach providing to a host, an indication of a quantity of requests stored in the buffer.
Thomas teaches load balancing of requests and sending feedback information to the host, including the number of outstanding requests waiting in the queue and the current load (0016, 0050, 0054). This information is used by the host to then redistribute the load to optimize resource use (0005).
It would have been obvious to one of ordinary skills in the art, at the time of the invention, to use Thomas’s teaching to send the number of requests stored in the buffer, in the invention of Jeddeloh, so that this information can be used to control the amount of requests sent to optimize resource use, lowering the number of outstanding of requests waiting to be serviced, and lowering the latency.
As to claim 12, Jeddeloh teaches the processing device is further configured to: responsive to determining that the latency is greater than the latency threshold, refraining from providing, to the host, the indication of the quantity of requests stored in the buffer to allow the back-end of the memory sub-system to process more requests without the memory sub-system receiving additional requests (Jeddeloh: monitor outstanding requests; maintain between first and second threshold; halt sending requests if outside of this range; 0010, 0024, 0032).
As to claim 13, Jeddeloh teaches the processing device is further configured to: responsive to determining that the latency less than the latency threshold (compare number of outstanding requests with a threshold; abstract, 0010, claims 2-5). However, Jeddeloh does not teach providing a number of credits corresponding to the quantity of requests stored in the buffer of the front-end. Thomas teaches load balancing of requests and sending feedback information to the host, including the number of outstanding requests waiting in the queue and the current load (0016, 0050, 0054). This information is used by the host to then redistribute the load to optimize resource use (0005). It would have been obvious to one of ordinary skills in the art, at the time of the invention, to use Thomas’s teaching to send the number of requests stored in the buffer, in the invention of Jeddeloh, so that this information can be used to control the amount of requests sent to optimize resource use, lowering the number of outstanding of requests waiting to be serviced, and lowering the latency.
As to claim 14, Thomas further teaches, wherein the processing device is further configured to provide a response comprising the number of credits as metadata (send number of outstanding requests waiting in a queue as feedback information; 0016, 0050, 0054).
As to claim 15, Jeddeloh teaches the processing device is further configured to provide the response responsive to receipt of the request (servicing the requests in the request queue; 0008, 0009, 0017, 0021).
As to claim 16, Jeddeloh teaches the processing device is further configured to provide the response responsive to receipt of a different request (system can process large quantity of requests from clients (0004-0005), each request is stored in the request queue and serviced by the system memory; 0008, 0009, 0017, 0021).
As to claim 17, Jeddeloh teaches a non-transitory computer readable medium having computer readable instructions (computer system implementing software to implement a method; 0015; 0008, 0010) stored thereon that are executable by a processor to: receive a request, at the front-end of the memory sub-system, from a host coupled to the memory sub-system (receive request from processor 104, provide request to queue 204 to memory system 120; 0017, 0019, 0021, Fig. 1, 2); store the request in a buffer of the front-end of the memory sub-system (store requests in request queue; 0019-0021); responsive to storing the request in the buffer, update a number of credits corresponding to a quantity of requests stored the buffer (monitor and count the number of outstanding requests in the request buffer; 0022-0023); and responsive to determining that a latency for processing the request is less than a latency threshold (compare number of outstanding requests with a threshold and determine if greater/less than the threshold; abstract, 0010, claims 2-5). Jeddeloh does not teach providing a response comprising the number of credits to the host, wherein the credits indicate whether the host provides additional requests to the memory sub-system. Thomas teaches load balancing of requests and sending feedback information to the host, including the number of outstanding requests waiting in the queue and the current load (0016, 0050, 0054). This information is used by the host to then redistribute the load to optimize resource use (0005). It would have been obvious to one of ordinary skills in the art, at the time of the invention, to use Thomas’s teaching to send the number of requests stored in the buffer, in the invention of Jeddeloh, so that this information can be used to control whether more requests should be sent, optimizing resource use, lowering the number of outstanding of requests waiting to be serviced, and lowering the latency.
As to claim 18, Jeddeloh teaches further comprises determining that the quantity of requests causes the latency for processing the request (determine number of outstanding requests issued to system memory; 0009, 0010, 0017, 0020-0025; compare number of outstanding requests with a threshold to determine if there is latency; abstract, 0010, claims 2-5; a determine and notify controller whether additional requests should be issued; 0021, 0024, 0032).
As to claim 19, Thomas teaches the response is one of a data response (DRS) (sending feedback information to the host, including the number of outstanding requests waiting in the queue and the current load (0016, 0050, 0054)) and a non-data response (NDR).
As to claim 20, Jeddeloh teaches provide the response via a compute express link (CXL) coupling the host to the memory sub-system (data communication is through a high speed interface; 0006-0007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138