Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/09/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 11-12 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Leonard (U.S. Publication No 2009/0121549 A1).
Regarding claims 1 and 11, Leonard teaches an inverter and method (e.g. 10)(Fig. 1), comprising a direct current DC bus (e.g. switch 20 connects each PV to DC bus)(Fig. 1), an inversion circuit (e.g. 37)(Fig. 1), a controller (e.g. 16)(Fig. 1), and a plurality of boost circuits (e.g. 26/32)(Fig. 1), wherein an input terminal (e.g. terminal that switch 20 connects to from each PV and goes to inductors connected to 26)(Fig. 1) of each of the boost circuits is configured to connect to a corresponding photovoltaic unit (e.g. 12)(Fig. 1), output terminals (e.g. 36)(Fig. 1) of the boost circuits are connected in parallel and connected to the DC bus, the inversion circuit is configured to convert DC power outputted by the DC bus into alternating current AC power (Para [0021], “The DC link circuit 19 includes an inverter circuit 37 that "chops" the DC power from the boost circuits to form AC power”), and the controller is connected to the boost circuits (e.g. 30/31)(Fig. 1), and wherein the controller is configured for:
determining, during an operation stage of the inverter, a to-be-adjusted boost circuit from the boost circuits, in response to determining that there is a loss boost circuit in a preset loss condition among the boost circuits, wherein the preset loss condition is an operation condition where there is a mismatch of input voltages in the boost circuits, resulting in a boost ratio greater than a preset boost ratio (Para [0027-0028], “To improve the efficiency of the DC input section 18, the boost circuit 26 for a PV array is disabled when the voltage level (Vmpp) of the array is at least at the minimum DC voltage level needed by the DC link circuit 19. Disabling one or more of the boost circuits reduces the efficiency losses that inherently occur when operating boost circuits. When the boost circuit is disabled the voltage output of the corresponding PV array is regulated by the DC-AC inverter….Further, the DC link voltage is periodically recalculated to determine if the voltage can be reduced from a default DC link voltage. Minimizing the DC link voltage reduces the level of the DV voltage needed from the PV arrays. By reducing the needed DC link voltage, it is more likely that the Vmpp for one or more of the PV arrays is at or above the needed minimum DC link voltage. If the Vmpp for an array is at or above the minimum DC link voltage, the boost circuit for that PV array may be disabled. Periodically determining a minimum DC link voltage allows the boost circuit(s) to be disabled more often”); and adjusting the to-be-adjusted boost circuit while ensuring that a change threshold for a total power output of the boost circuits is less than a preset adjustment threshold, to reduce a boost ratio of the loss boost circuit (Para [0019], “The ratio of the DC voltage level output by and input to the boost circuit 26 is proportional to the ratio of the entire duty cycle divided by the ON portion of the cycle. Typically, the greatest effective boost in voltage is achieved with a duty cycle in which the switches are open one-half of the cycle (50-50 cycle)”, Para [0030], “In step 106, the DC power from the PV arrays, which is now above the threshold, is applied to the DC input circuit 18 and, particularly, to the boost circuit 26. The boost control routine 31 in the controller 16 adjusts the boost circuit, e.g., the duty cycle, to draw power from the PV arrays and step up the DC power from the PV arrays to a higher DC voltage level, in step 108”).
Regarding claims 2 and 12, Leonard teaches wherein the determining the to-be-adjusted boost circuit from the boost circuits comprises: determining the to-be-adjusted boost circuit from the boost circuits based on first attribute information of the boost circuits (Para [0027], “To improve the efficiency of the DC input section 18, the boost circuit 26 for a PV array is disabled when the voltage level (Vmpp) of the array is at least at the minimum DC voltage level needed by the DC link circuit 19. Disabling one or more of the boost circuits reduces the efficiency losses that inherently occur when operating boost circuits. When the boost circuit is disabled the voltage output of the corresponding PV array is regulated by the DC-AC inverter”).
Regarding claim 20, Leonard teaches a power system, comprising a plurality of photovoltaic units (e.g. 12)(Fig. 1) and at least one inverter (e.g. 37)(Fig. 1) according to claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Leonard (U.S. Publication No 2009/0121549 A1) in view of Ogura (JP Publication No 2014/072944A).
Regarding claims 3 and 13, although Leonard teaches wherein the first attribute information comprises at least one of a temperature, an input voltage, and an input power; and the determining the to-be-adjusted boost circuit from the boost circuits based on first attribute information of the boost circuits comprises: determining, from the boost circuits, a boost circuit which has an input voltage satisfying a preset voltage condition as the to-be-adjusted boost circuit, in a case where the first attribute information comprises the input voltage (Para [00247], “To improve the efficiency of the DC input section 18, the boost circuit 26 for a PV array is disabled when the voltage level (Vmpp) of the array is at least at the minimum DC voltage level needed by the DC link circuit 19. Disabling one or more of the boost circuits reduces the efficiency losses that inherently occur when operating boost circuits. When the boost circuit is disabled the voltage output of the corresponding PV array is regulated by the DC-AC inverter”); and determining, from the boost circuits, a boost circuit which has an input power satisfying a preset power condition as the to-be-adjusted boost circuit, in a case where the first attribute information comprises the input power Para [0006], “applying the DC power generated by the PV array to the PV inverter; boosting the DC power from the PV array from a predetermined voltage level (Vmpp) to a predetermine DC link voltage (the voltage required to connect to the AC Grid), wherein the PV array is regulated by the boosting to output a voltage at the predetermined voltage level (Vmpp); converting the boosted DC power to AC power”).
Leonard does not teach determining, from the boost circuits, a boost circuit which has a temperature satisfying a preset temperature condition as the to-be-adjusted boost circuit, in a case where the first attribute information comprises the temperature.
However, Ogura teaches determining, from the boost circuits, a boost circuit which has a temperature satisfying a preset temperature condition as the to-be-adjusted boost circuit, in a case where the first attribute information comprises the temperature (Espacenet JP2014072944A English translation, Para [0042], “Therefore, in this first boost mode, each control circuit 53 starts monitoring the temperature (temperature of the switching element) detected by the corresponding temperature sensor 52 when the boost operation in the boost circuit 51 begins (see step S1 in Figure 3). The temperature monitoring by each control circuit 53 periodically checks whether the switching element has reached a predetermined upper limit temperature T1, which is set in advance as the temperature at which it can generate heat (see step S2 in Figure 3)”).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “inverter” teachings of Leonard such that it comprises “determining, from the boost circuits, a boost circuit which has a temperature satisfying a preset temperature condition as the to-be-adjusted boost circuit, in a case where the first attribute information comprises the temperature” as taught by Ogura. The reason for doing so would be to provide monitor temperature in order to protect circuit components from damage.
Regarding claims 4 and 14, Ogura teaches wherein the boost circuit which has the temperature satisfying the preset temperature condition comprises at least one of:
a boost circuit having a highest temperature (Espacenet JP2014072944A English translation, Para [0042], “Therefore, in this first boost mode, each control circuit 53 starts monitoring the temperature (temperature of the switching element) detected by the corresponding temperature sensor 52 when the boost operation in the boost circuit 51 begins (see step S1 in Figure 3). The temperature monitoring by each control circuit 53 periodically checks whether the switching element has reached a predetermined upper limit temperature T1, which is set in advance as the temperature at which it can generate heat (see step S2 in Figure 3)”), a boost circuit having a lowest temperature, a boost circuit having a temperature greater than or equal to a first preset temperature threshold, and a boost circuit having a temperature less than or equal to a second preset temperature threshold.
Leonard teaches the boost circuit which has the input voltage satisfying the preset voltage condition comprises at least one of: at least one boost circuit of two boost circuits having an input voltage difference greater than or equal to a first preset voltage difference threshold, a boost circuit having a highest input voltage, and a boost circuit having a lowest input voltage the boost circuit 26 for a PV array is disabled when the voltage level (Vmpp) of the array is at least at the minimum DC voltage level needed by the DC link circuit 19. Disabling one or more of the boost circuits reduces the efficiency losses that inherently occur when operating boost circuits. When the boost circuit is disabled the voltage output of the corresponding PV array is regulated by the DC-AC inverter.; and
the boost circuit which has the input power satisfying the preset power condition comprises at least one of:
a boost circuit having a highest input power (Para [0006], “applying the DC power generated by the PV array to the PV inverter; boosting the DC power from the PV array from a predetermined voltage level (Vmpp) to a predetermine DC link voltage (the voltage required to connect to the AC Grid), wherein the PV array is regulated by the boosting to output a voltage at the predetermined voltage level (Vmpp); converting the boosted DC power to AC power”…Para [0009], “selecting a maximum power output from the power outputs in the operating range and designating a corresponding voltage as a voltage at maximum power point (Vmpp) for the array; periodically repeating the prior steps to update Vmpp; operating the photovoltaic array at the Vmpp; dithering the Vmpp by slightly shifting the voltage of the array away from the Vmpp, and if the power output of the array at the shifted voltage is greater than the power output of the array at Vmpp, designating the shifted voltage as the Vmpp”) and a boost circuit having a lowest input power.
Allowable Subject Matter
Claims 5-6, 7-10, 15-16, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5 and 15, none of the prior art, taken singly or in combination, teaches or fairly suggest “wherein the determining that there is the loss boost circuit in the preset loss condition among the boost circuits comprises: obtaining second attribute information of the boost circuits; and determining, from the boost circuits, a boost circuit whose second attribute information satisfies a preset attribute condition as the loss boost circuit in the preset loss condition”.
Claim 6 is indicated as allowable, as it depends on claim 5.
Claim 16 is indicated as allowable, as it depends on claim 15.
Regarding claims 7 and 17, none of the prior art, taken singly or in combination, teaches or fairly suggest “wherein the adjusting the to-be-adjusted boost circuit while ensuring that the change threshold for the total power output of the boost circuits is less than the preset adjustment threshold, to reduce the boost ratio of the loss boost circuit, comprises: adjusting an input voltage of the to-be-adjusted boost circuit while ensuring that an equivalent input voltage of the inverter is within a designated voltage range, to reduce the boost ratio of the loss boost circuit, wherein the equivalent input voltage is determined based on the input voltages of the boost circuits, and the designated voltage range corresponds to a voltage limiting power in a power-voltage curve of the inverter; or adjusting the input voltage of the to-be-adjusted boost circuit, and determining whether the total power output of the boost circuits after the adjustment is less than the total power output of the boost circuits before the adjustment; drawing back the adjustment on the input voltage of the to-be-adjusted boost circuit, in response to determining that the total power output after the adjustment is less than the total power output before the adjustment; and keeping the adjustment on the input voltage of the to-be-adjusted boost circuit, in response to determining that the total power output after the adjustment is greater than or equal to the total power output before the adjustment, until the total power output of the boost circuits after the adjustment is less than the total power output of the boost circuits before the adjustment”.
Claims 8-10 are indicated as allowable, as they depend on claim 7.
Claims 18-19 are indicated as allowable, as they depend on claim 17.
Conclusion
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/JONATHAN WALTER SOILEAU/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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