DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s arguments filed on 07/06/2026.
Response to Arguments
Applicant’s arguments, see Remarks, filed on 07/06/2026, with respect to claims 1-16 have been fully considered and are persuasive. The 102(a)(1) Rejection of claims 1-16 has been withdrawn.
Applicant’s arguments with respect to claim(s) 17-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17 and 23 is/are rejected under 35 U.S.C 102(a)(1) as being anticipated by Ricky Setiawan et al. (“Ricky”, US Pub 2021/0255653).
Regarding independent claim 17, Ricky teaches (Fig. 1-7) a regulator circuit apparatus (Fig. 1; multiple LDOs 115 0-1, 116 0-1; wherein LDO’s detail can be any one of Fig. 3 or Fig. 4; wherein the selected LDO includes two loops i) main loop ‘340 with main output transistor 346 or 440 with main output transistor 446’ and ii) replica loop ‘330 with replica output transistor 336 or 430 with replica output transistor 436’) comprising:
a single output transistor (multiple LDOs 115 0-1, 116 0-1’s detail can be any one of Fig. 3 or Fig. 4; wherein the selected LDO includes two loops i) main loop ‘340 with main output transistor 346 or 440 with main output transistor 446’ and ii) replica loop ‘330 with replica output transistor 336 or 430 with replica output transistor 436’) configured to supply power to core circuitry (Fig. 7; 720):
in an active state (normal or active state) at an operating voltage (i.e., use of selective high-powered and low powered LDO’s output; Para 47-48 and 19-28) within a safe operating range for core circuitry (Fig. 7; 720); and
in a low-power state (snooze/low-power mode) at a low voltage (i.e., use of only low powered LDO’s output; Para 47-48 and 19-28) below the operating voltage (i.e., use of selective high-powered and low powered LDO’s output; Para 47-48 and 19-28) without shutting down the single output transistor (multiple LDOs 115 0-1, 116 0-1’s detail can be any one of Fig. 3 or Fig. 4; wherein the selected LDO includes two loops i) main loop ‘340 with main output transistor 346 or 440 with main output transistor 446’ and ii) replica loop ‘330 with replica output transistor 336 or 430 with replica output transistor 436’); and
an amplifier (multiple LDOs 115 0-1, 116 0-1’s detail can be any one of Fig. 3 or Fig. 4; wherein the selected LDO includes two loops and both loop use amplifier Fig. 3’s 320 or Fig. 4’s 420) configured to selectively supply a bias voltage (multiple LDOs 115 0-1, 116 0-1’s detail can be any one of Fig. 3 or Fig. 4; wherein the selected LDO includes two loops and both loop use two bias voltages Vb or Vb1; Para 37-38) to the single output transistor effective to cause the single output transistor (multiple LDOs 115 0-1, 116 0-1’s detail can be any one of Fig. 3 or Fig. 4; wherein the selected LDO includes two loops i) main loop ‘340 with main output transistor 346 or 440 with main output transistor 446’ and ii) replica loop ‘330 with replica output transistor 336 or 430 with replica output transistor 436’) to:
supply the operating voltage when the single output transistor is in the active state (i.e., use of selective high-powered and low powered LDO’s output; Para 47-48 and 19-28); and
supply the low power voltage when the single output transistor is in the low-power state (i.e., use of only low powered LDO’s output; Para 47-48 and 19-28);
wherein the regulator circuit includes a capacitance (Fig. 3-4; Cmain) to apply miller compensation between an output of the amplifier and the output of the single output transistor to limit the bandwidth of the regulator circuit.
Regarding claim 23, Ricky teaches (Fig. 1-7) a plurality of regulator circuit apparatuses configured to provide separate supply powers each with operating voltages (i.e., use of selective high-powered and low powered LDO’s output; Para 47-48 and 19-28) within the safe operating range for separate loads of the core circuitry (Fig. 7; 720) (Fig. 1; multiple LDOs 115 0-1, 116 0-1; wherein LDO’s detail can be any one of Fig. 3 or Fig. 4; wherein the selected LDO includes two loops i) main loop ‘340 with main output transistor 346 or 440 with main output transistor 446’ and ii) replica loop ‘330 with replica output transistor 336 or 430 with replica output transistor 436’)
Allowable Subject Matter
Claims 18-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 18, cited art(s) failed to teach, “a current source configured to switchably bias the amplifier and to provide current to power the core circuitry, the current source including: a current mirror configured to provide operating current to the amplifier when the current mirror is in a stable operating condition; a startup circuit configured to direct supplemental current to the current mirror to drive the current mirror into the stable operating condition; and a biasing circuit configured to stop the startup circuit from directing the supplemental current to the current mirror when the current mirror is in the stable operating condition”.
Regarding claim 19, cited art(s) failed to teach, as a whole, nor would it be obvious to piecewise combine with any other arts to teach, “a switchable reference voltage including; an always-on source configured to provide an approximation of the reference voltage from an input voltage; a precision voltage source configured to provide the reference voltage after an interval; and a switch configured to provide a reference voltage source configured to provide the approximation of the reference voltage source during the interval and transition to the reference voltage at the end of the interval”.
Claims 20-22 are depending from claim 19.
Claims 1-16 are allowed. The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 1, cited art(s) failed to teach, “a current source configured to switchably bias the amplifier and to provide current to power the core circuitry, the current source including: a current mirror configured to provide operating current to the amplifier when the current mirror is in a stable operating condition; a startup circuit configured to direct supplemental current to the current mirror to drive the current mirror into the stable operating condition; and a biasing circuit configured to stop the startup circuit from directing the supplemental current to the current mirror when the current mirror is in the stable operating condition”.
Claims 3-6, 9-10 are depending from claim 1.
Regarding independent claim 11, cited art(s) failed to teach, as a whole, nor would it be obvious to piecewise combine with any other arts to teach, “a switchable reference voltage including; an always-on source configured to provide an approximation of the reference voltage from an input voltage; a precision voltage source configured to provide the reference voltage after an interval; and a switch configured to provide a reference voltage source configured to provide the approximation of the reference voltage source during the interval and transition to the reference voltage at the end of the interval”.
Claims 12-16 are depending from claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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