DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 12/27/2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsao et al. (“Tsao”, US Pub 2022/0365550).
Regarding independent claim 1, Tsao teaches (Fig. 1-8) a regulator circuit apparatus (Fig. 2; DC LDO regulator 200; Para 32) comprising:
a single output transistor (Fig. 2, 6B; use of transistors for decoupling capacitor(s) 204; Para 32-33, 36-37 52-55) configured to supply power to core circuitry (Fig. 2; any one of core design(s) 210, 212):
in an active state (active state vs. power-down mode; abstract, para ‘20-22, 29-30, 35-36, 52, 62, 64, 66’, claims ‘2, 14, 20’) at an operating voltage within a safe operating range for core circuitry (Fig. 2, 4; using VREFGEN 206 providing varied VREFM supply voltage 230 (for example, ±0.5V, 0.6V, 0.7V, etc.) to meet each core design(s) ‘210, 212’ requirement(s), via the respective the output voltage 214, 216; abstract, para ‘2, 20, 32, 45-49’); and
in a low-power state (active state vs. power-down mode; abstract, para ‘20-22, 29-30, 35-36, 51-52, 62, 64, 66’, claims ‘2, 14, 20’) at a low voltage (Fig. 2, 5; PDCTRL 208 providing HGND 228 at the value of 0.45V at least, thus never shutting down fully rather maintaining operating voltage within a safe operating range; Para 50-55) below the operating voltage (Fig. 2, 4; using VREFGEN 206 providing varied VREFM supply voltage 230 (for example, ±0.5V, 0.6V, 0.7V, etc.) to meet each core design(s) ‘210, 212’ requirement(s), via the respective the output voltage 214, 216; abstract, para ‘2, 20, 32, 45-49’) without shutting down (Para 50-55) the single output transistor (Fig. 2, 6B; use of transistors for decoupling capacitor(s) 204, wherein one of the transistors is always conducting based on ‘HPWR, HGND or LPWR’ values); and
an amplifier (Fig. 2, 3A-E; 202’s different examples being shown in Fig. 3A-E; Para 32-44) configured to selectively supply a bias voltage (Fig. 2, 3A-E; use of various bias voltage(s) ‘vbpx, vbnx, vbp1, vpb2, vbn1, vbn2’ for 202’s detail in Fig. 3C-E; Para 41-44) to the single output transistor effective to cause the single output transistor (Fig. 2, 6B; use of transistors for decoupling capacitor(s) 204, wherein one of the transistors is always conducting based on ‘HPWR, HGND or LPWR’ values) to:
supply the operating voltage (Fig. 2, 4; using VREFGEN 206 providing varied VREFM supply voltage 230 (for example, ±0.5V, 0.6V, 0.7V, etc.) to meet each core design(s) ‘210, 212’ requirement(s), via the respective the output voltage 214, 216; abstract, para ‘2, 20, 32, 45-49’) when the single output transistor (Fig. 2, 6B; use of transistors for decoupling capacitor(s) 204, wherein one of the transistors is always conducting based on ‘HPWR or LPWR’ values) is in the active state (active state vs. power-down mode; abstract, para ‘20-22, 29-30, 35-36, 52, 62, 64, 66’, claims ‘2, 14, 20’); and
supply the low power voltage (Fig. 2, 5; PDCTRL 208 providing HGND 228 at the value of 0.45V at least, thus never shutting down fully rather maintaining operating voltage within a safe operating range; Para 50-55) when the single output transistor (Fig. 2, 6B; use of transistors for decoupling capacitor(s) 204, wherein one of the transistors is always conducting based on ‘HGND or LPWR’ values) is in the low-power state (active state vs. power-down mode; abstract, para ‘20-22, 29-30, 35-36, 51-52, 62, 64, 66’, claims ‘2, 14, 20’).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tsao (US Pub 2022/0365550), in view of Buist et al. (“Buist”, US Pat 2021/0242865).
Regarding claim 7, Tsao teaches … the regulator circuit (Fig. 2; DC LDO regulator 200; Para 32) from the core (or load) circuitry (Fig. 2; any one of core design(s) 210, 212) when the regulator circuit is in the low-power state (Fig. 2, 5; PDCTRL 208 providing HGND 228 at the value of 0.45V at least, thus never shutting down fully rather maintaining operating voltage within a safe operating range; Para 50-55).
However, Tsao fails to teach use of a switch to isolate the regulator circuit from the load when the regulator circuit is in the low-power state.
However, Buist teaches (Fig. 1, 3; para 38-42, 51-66) use of a switch to isolate (i.e., 307; para 56-58) the regulator circuit (i.e., 100 described as 301) from the load (110) when the regulator circuit is in the low-power state.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsao’s regulator circuit to use a switch to isolate the regulator circuit from the core or load circuitry when the regulator circuit is in the low-power state, as doing so would have prevented considerable damage to components and printed circuit board, leading to stable overall operation thru protection, as taught by Buist (Para 2 and abstract).
Regarding claim 10, Tsao teaches a … regulator circuit (Fig. 2; DC LDO regulator 200; Para 32) configured to provide separate supply powers each with operating voltages within the safe operating range for separate loads of core circuitry (Fig. 2, 4; using VREFGEN 206 providing varied VREFM supply voltage 230 (for example, ±0.5V, 0.6V, 0.7V, etc.) to meet each core design(s) ‘210, 212’ requirement(s), via the respective the output voltage 214, 216; abstract, para ‘2, 20, 32, 45-49’).
However, Tsao fails to teach use of a plurality of regulator circuits configured to provide separate supply powers.
However, Buist teaches (Fig. 1, 3; para 38-42, 51-66) use of a plurality of regulator circuits (Fig. 1) configured to provide separate supply powers (at 108).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsao’s regulator circuit to use a switch to isolate each of the plurality of regulator circuits from the core or load circuitry when the respective regulator circuit being in the low-power state, as doing so would have prevented considerable damage to components and printed circuit board, leading to stable overall operation thru protection, as taught by Buist (Para 2 and abstract).
Allowable Subject Matter
Claims 2-6, 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, cited art(s) failed to teach, “a current source configured to switchably bias the amplifier and to provide current to power the core circuitry, the current source including: a current mirror configured to provide operating current to the amplifier when the current mirror is in a stable operating condition; a startup circuit configured to direct supplemental current to the current mirror to drive the current mirror into the stable operating condition; and a biasing circuit configured to stop the startup circuit from directing the supplemental current to the current mirror when the current mirror is in the stable operating condition”.
Regarding claim 3, Tsao teaches (Fig. 1-8) (Fig. 2, 4; using VREFGEN 206 providing varied VREFM supply voltage 230 (for example, ±0.5V, 0.6V, 0.7V, etc.) to meet each core design(s) ‘210, 212’ requirement(s), via the respective the output voltage 214, 216; abstract, para ‘2, 20, 32, 45-49’)
a switchable reference voltage including (VREFM 230 being a switchable reference voltage, using sw0 to provide Vx (which is based on LPWR or HPWR) or sw1 to provide constant or always-on Vref source);
an always-on source configured to provide an approximation of the reference voltage (VREFM 230) from an input voltage (i.e., 222 VREF);
a precision voltage source (i.e., using combined operation of elements in Fig. 4 that provides Vx) configured to provide the reference voltage (VREFM 230) after an interval (i.e., using sw0 to provide Vx (which is based on LPWR or HPWR) after an anticipated interval, as required by core design(s) ‘210, 212’).
However, cited art(s) failed to teach, as a whole, nor would it be obvious to piecewise combine with any other arts to teach, “a precision voltage source configured to provide the reference voltage after an interval; and a switch configured to provide a reference voltage source configured to provide the approximation of the reference voltage source during the interval and transition to the reference voltage at the end of the interval”.
Claims 4-6 are depending from claim 3.
Regarding claim 8, cited art(s) failed to teach the switch includes a switching transistor “controlled by a level shifter (responsive to an output voltage of the regulator circuit), the level shifter disabling the switching transistor when the output voltage of the regulator indicates the regulator circuit is in the low-power state”.
Regarding claim 9, cited art(s) failed to teach the regulator circuit includes “a capacitance to apply middle compensation between an output of the amplifier and the output of the single output transistor to limit the bandwidth of the regulator circuit”.
Conclusion
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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