Prosecution Insights
Last updated: April 20, 2026
Application No. 19/003,253

SELECTIVE PACKING OF PATCHES FOR IMMERSIVE VIDEO

Non-Final OA §102§103
Filed
Dec 27, 2024
Examiner
YANG, NIEN
Art Unit
2484
Tech Center
2400 — Computer Networks
Assignee
Intel Corporation
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
287 granted / 399 resolved
+13.9% vs TC avg
Strong +29% interview lift
Without
With
+28.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
30 currently pending
Career history
429
Total Applications
across all art units

Statute-Specific Performance

§101
5.6%
-34.4% vs TC avg
§103
73.6%
+33.6% vs TC avg
§102
6.5%
-33.5% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 399 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Preliminary Remarks This is a reply to the application filed on 12/27/2024, in which, claims 1-20 remain pending in the present application with claims 1, 8, and 15 being independent claims. When making claim amendments, the applicant is encouraged to consider the references in their entireties, including those portions that have not been cited by the examiner and their equivalents as they may most broadly and appropriately apply to any particular anticipated claim amendments. Information Disclosure Statement The three information disclosure statements (IDS) submitted on January 14, 2026 are in compliance with the provisions of 37 CFR 1.97 and are being considered by the Examiner. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. - An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. Use of the word “means” (or “device”, “step for”, “unit”, “element”, “mechanism”, “module”, “engine”, “component”, “member”, “apparatus”, “machine”, “system”, “assembly”, “portion”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function. Absence of the word “means” in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function. The claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: means for packing… in claim 15; and means for encoding… in claim 15. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. (FP 7.30.06). For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011). Claims 16-20 depend on claim 15 thus 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is also invoked. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-4, 8, 10-11, 15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mammou et al. (US 20170227765 A1, hereinafter referred to as “Mammou”). Regarding claim 1, Mammou discloses at least one memory comprising instructions to cause at least one processor circuit (see Mammou, paragraph [0047]: “a computer readable non-transitory medium including instructions which when executed in a processing system cause the processing system to execute a method”) to at least: pack first patches of data into a first atlas associated with a first camera (see Mammou, paragraph [0036]: “FIG. 3 shows a wireless VR system 300 in accordance with certain embodiments that overcomes the limitations discussed previously by combining a texture-space rendering approach with efficient low latency compression as discussed above. As discussed, scene content from the wireless VR system 300 is decoupled into three information components and each information component is then encoded and streamed differently”); pack second patches of data into a second atlas associated with a second camera (see Mammou, paragraph [0038]: “A video encoder 330 compresses and encodes the texture atlas 325 for transmission as a bitstream to the video decoder 335. The video decoder 335 decodes the bitstream and feeds the decoded texture atlas 325 to a client-side rendering engine 340”); and encode information of the first atlas and information of the second atlas into a video bitstream (see Mammou, paragraph [0038]: “The rendering engine 340 processes the decoded texture atlas 325 with updated head/camera motion from the HMD 305 and updated object motion data from the game engine 315. The left and right view outputs from the client-side rendering engine 340 are presented to the HMD 305”). Regarding claim 3, Mammou discloses the at least one memory of claim 1, wherein the first camera is associated with a first projection viewpoint, and the second camera is associated with a second projection viewpoint (see Mammou, paragraph [0031]: “a given object is rendered from different camera viewpoints to generate a database of rendered textures”). Regarding claim 4, Mammou discloses the at least one memory of claim 1, wherein the first atlas is a first image and the second atlas is a second image (see Mammou, paragraph [0041]: “The video encoder encodes the texture atlas and the server transmits the encoded image/bitstream to a video decoder”). Claim 8 is rejected for the same reasons as discussed in claim 1 above. In addition, Mammou also discloses an apparatus comprising: interface circuitry (see Mammou, paragraph [0049]: “Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC), and/or a state machine”); and instructions (see Mammou, paragraph [0047]: “a computer readable non-transitory medium including instructions which when executed in a processing system”). Claim 10 is rejected for the same reasons as discussed in claim 3 above. Claim 11 is rejected for the same reasons as discussed in claim 4 above. Claim 15 is rejected for the same reasons as discussed in claim 1 above. Claim 17 is rejected for the same reasons as discussed in claim 3 above. Claim 18 is rejected for the same reasons as discussed in claim 4 above. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 5-7, 9, 12-14, 16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mammou in view of Pang et al. (US 20180035134 A1, hereinafter referred to as “Pang”). Regarding claim 2, Mammou discloses all the claimed limitations with the exception of the at least one memory of claim 1, wherein the video bitstream is an immersive video bitstream. Pang from the same or similar fields of endeavor discloses the at least one memory of claim 1, wherein the video bitstream is an immersive video bitstream (see Pang, paragraph [0315]: “represent immersive video data by creating a three-dimensional sampling grid over the viewing volume. Each point of the sampling grid is called a “vantage.” Various vantage arrangements may be used, such as a rectangular grid, a polar (spherical) matrix, a cylindrical matrix, and/or an irregular matrix. Each vantage may contain a projected view, such as an omnidirectional view projected onto the interior of a sphere, of the scene at a given coordinate in the sampling grid. This projected view may be encoded into video data for that particular vantage”). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Pang with the teachings as in Mammou. The motivation to doing so would ensure the system to have the ability to use the method for decoding a video stream of a scene for a virtual reality or augmented reality experience disclosed in Pang to represent immersive video data by creating sampling grid wherein each point of the sampling grid is a vantage; to include two-dimensional image data by computing data representative of a scene; and to use a metafile to describe any additional information such as the codec used for compression thus encoding an immersive video bitstream; including respective two-dimensional image data in patches of data; and including metadata to reconstruct a video from the patches of data in order to allow clients not decode the entire coded picture but only patches of video data so that high network bandwidth for transmission is not needed. Regarding claim 5, the combination teachings of Mammou and Pang as discussed above also disclose the at least one memory of claim 1, wherein the first patches include respective two-dimensional image data (see Pang, paragraph [0148]: “data acquisition device can be any device or system for acquiring, recording, measuring, estimating, determining and/or computing data representative of a scene, including but not limited to two-dimensional image data”). The motivation for combining the references has been discussed in claim 2 above. Regarding claim 6, the combination teachings of Mammou and Pang as discussed above also disclose the at least one memory of claim 1, wherein the information of the first atlas includes metadata to reconstruct a video from the first patches of data (see Pang, paragraph [0389]: “Each tile may then be compressed by an encoder 4750, which may be an encoder as described in any of the previous sections. For each tile, a metafile may be used to describe any additional information, such as the codec used for compression, time segmentation, tile playback dependences and file storage, etc. The metadata may thus support playback”). The motivation for combining the references has been discussed in claim 2 above. Regarding claim 7, the combination teachings of Mammou and Pang as discussed above also disclose the at least one memory of claim 6, wherein the instructions are to cause one or more of the at least one processor circuit to: encode the first atlas in a first stream of the video bitstream (see Mammou, paragraph [0038]: “A video encoder 330 compresses and encodes the texture atlas 325 for transmission as a bitstream to the video decoder”); and encode the metadata in a second stream of the video bitstream (see Pang, paragraph [0389]: “For each tile, a metafile may be used to describe any additional information”). The motivation for combining the references has been discussed in claim 2 above. Claim 9 is rejected for the same reasons as discussed in claim 2 above. Claim 12 is rejected for the same reasons as discussed in claim 5 above. Claim 13 is rejected for the same reasons as discussed in claim 6 above. Claim 14 is rejected for the same reasons as discussed in claim 7 above. Claim 16 is rejected for the same reasons as discussed in claim 2 above. Claim 19 is rejected for the same reasons as discussed in claim 5 above. Claim 20 is rejected for the same reasons as discussed in claim 7 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIENRU YANG whose telephone number is (571)272-4212. The examiner can normally be reached Monday-Friday 10AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THAI TRAN can be reached at 571-272-7382. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NIENRU YANG Examiner Art Unit 2484 /NIENRU YANG/Examiner, Art Unit 2484 /THAI Q TRAN/Supervisory Patent Examiner, Art Unit 2484
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Prosecution Timeline

Dec 27, 2024
Application Filed
Feb 12, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+28.7%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 399 resolved cases by this examiner. Grant probability derived from career allow rate.

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