Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 12/27/2024. Claims 1-20 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-5 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gao et al. Pub. No. 2013/0162349.
Regarding claim 1. Fig. 1 of Gao et al. discloses harmonic compensation apparatus (paragraph 0030), comprising: a harmonic compensation circuit (LUT memory); configured to perform a harmonic generation process (DPD) and a compensation adjusting process ((e(t) =f(t)-u(t)) on a digital input signal (digital Signal generator) according to a compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) to generate a harmonic compensation digital signal (output of LUT memory); a conversion circuit ( Subtractor of output Signal Generator and DAC) configured to perform a harmonic compensation (Subtraction of Signal Generator and output of LUT memory) and a signal conversion (DAC) on the digital input signal (digital signal generator) according to the harmonic compensation digital signal (output of LUT memory) to generate an analog input signal (analog output of DAC) an analog output circuit (Non-linear PA) configured to generate an analog output signal (analog output of PA) to an external circuit (load Capacitor) according to the analog input signal (analog output of DAC) and detect a loading state (Resistors 1:BETA) of the external circuit (load Capacitor) to generate a loading state detection signal ((f(t)) , wherein the harmonic compensation (DPD) eliminates a harmonic component (paragraph 0030) of the analog output signal (output of Non-Linear PA) that is generated by the conversion circuit ( Subtractor of Signal Generator and DAC) and the analog output circuit (output of Non-Linear PA) according to the digital input signal (digital signal generator) ; and a compensation control circuit (feedback Subtraction of D and ADC circuits) configured to generate the compensation parameter output control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) according to the loading state detection signal (f(t)).
Regarding claim 2. The harmonic compensation apparatus of claim 1, Fig. 1 further discloses wherein the analog output circuit (Non-linear PA) is configured to detect a current detection value (current for load capacitor) and a voltage detection value (voltage of 1:BETA) of the analog output signal (output of PA)such that the loading state detection signal (f(t)) generated thereby comprises the current detection value (current of capacitor load) and the voltage detection value voltage of 1:BETA), and the compensation control circuit (feedback Subtraction of D and ADC circuits) calculates an output wattage or a resistive value (Resistor 1:BETA) of the external circuit (load capacitor) according to the current detection value (current of the capacitor load) and the voltage detection value (1:BETA) and generates the compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) according to the output wattage or the resistive value (resistor 1:BETA).
Regarding claim 3. The harmonic compensation apparatus of claim 1, Fig. 1 further discloses wherein the analog output circuits (Non-Linear PA) configured to detect a current detection value (current of the capacitor Load) and a voltage detection value (Voltage of Resistors) of the analog output signal (output of Non-linear PA) and calculates an output wattage or a resistive value (Resistor 1:BETA) of the external circuit (load capacitor) according to the current detection value (current of the capacitor load) and the voltage detection value (1:BETA) such that the loading state detection signal (f(t)) generated thereby comprises the output wattage or the resistive value (Resistor 1:BETA), and the compensation control circuit (feedback Subtraction of D and ADC circuits) generates the compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) according to the output wattage or the resistive value (Resistors 1:BETA).
Regarding claim 4. The harmonic compensation apparatus of claim 1, Fig. 1 further discloses wherein the compensation control circuit (feedback Subtraction of D and ADC circuits) is configured to store a compensation parameter look-up table (LUT memory) to look up the compensation parameter look-up table (LUT Memory) according to the loading state detection signal (f(t)) to generate the compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits).
Regarding claim 5. The harmonic compensation apparatus of claim 1, Fig. 1 further discloses wherein the conversion circuit (Subtractor of output Signal Generator and DAC) comprises: a mixer (Subtractor) configured to perform the harmonic compensation (paragraph 0030) on the digital input signal (digital signal generator) and the harmonic compensation digital signal (output of LUT memory) to generate a digital output signal (digital output of subtractor); and a digital-to-analog converter (DAC) configured to perform the signal conversion on the digital output signal (output signal of Subtractor) to generate the analog input signal (analog output of DAC).
Regarding claim 11. Fig. 1 of Gao et al. A harmonic compensation (paragraph 0030) method, comprising: performing a harmonic generation process (LUT memory) and a compensation adjusting process (DPD) on a digital input signal (digital signal generator) according to a compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) by a harmonic compensation circuit (LUT memory) to generate a harmonic compensation digital signal (output of LUT memory); performing a harmonic compensation(Subtractor of signal generator and output of LUT memory) and a signal conversion (DAC) on the digital input signal (digital signal generator ) according to the harmonic compensation digital signal (digital output of Subtractor) by a conversion circuit (DAC) to generate an analog input signal (analog output of DAC); generating an analog output signal (output of Non-linear PA) to an external circuit (Load Capacitor) according to the analog input signal (analog output of DAC) and detecting a loading state (resistors feedback) of the external circuit (load capacitor) by an analog output circuit (output of Non-Linear PA) to generate a loading state detection signal (f(t)) , wherein the harmonic compensation (LUT memory) eliminates a harmonic component (paragraph 0030) of the analog output signal (output of Non-Linear PA) that is generated by the conversion circuit (DAC) and the analog output circuit (Non-Linearity PA) according to the digital input signal (digital signal generator ); and generating the compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) according to the loading state detection signal (f(t)) by a compensation control circuit (control input signal of LUT memory from feedback Subtraction of D and ADC circuits).
Regarding claim 12. The harmonic compensation method of claim 11, Fig. 1 further comprising: detect a current detection value (current for load capacitor) and a voltage detection value (voltage of 1:BETA) of the analog output signal (output of PA)such that the loading state detection signal (f(t)) generated thereby comprises the current detection value (current of capacitor load) and the voltage detection value voltage of 1:BETA), and calculates an output wattage or a resistive value (Resistor 1:BETA) of the external circuit (load capacitor) according to the current detection value (current of the capacitor load) and the voltage detection value (1:BETA) and generates the compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) according to the output wattage or the resistive value (resistor 1:BETA) by the compensation control circuit (feedback Subtraction of D and ADC circuits).
Regarding claim 13. The harmonic compensation method of claim 11, Fig. 1 further comprising: to detect a current detection value (current of the capacitor Load) and a voltage detection value (Voltage of Resistors) of the analog output signal (output of Non-linear PA) by the analog output circuit (Non-Linear PA) and calculates an output wattage or a resistive value (Resistor 1:BETA) of the external circuit (load capacitor) according to the current detection value (current of the capacitor load) and the voltage detection value (1:BETA) by the analog output circuit (Non-Linear PA) such that the loading state detection signal (f(t)) generated thereby comprises the output wattage or the resistive value (Resistor 1:BETA), and generates the compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits) according to the output wattage or the resistive value (Resistors 1:BETA) by the compensation control circuit (feedback Subtraction of D and ADC circuits).
Regarding claim 14. The harmonic compensation method of claim 11, Fig. 1 further comprising: storing a compensation parameter look-up table (LUT) by the compensation control circuit (feedback Subtraction of D and ADC circuits) to look up the compensation parameter look-up table (LUT) according to the loading state detection signal (f(t)) to generate the compensation parameter control signal (control input signal of LUT memory from feedback Subtraction of D and ADC circuits).
Regarding claim 15. The harmonic compensation method of claim 11, Fig. 1 further comprising: performing the harmonic compensation (LUT) on the digital input signal (Digital signal generator) and the harmonic compensation digital signal (output of subtractor between signal generator and output of LUT memory) by a mixer (Subtractor between signal generator and output of LUT memory) comprised the conversion circuit (Subtractor and DAC) to generate a digital output signal (digital output of subtractor); and performing the signal conversion (DAC) on the digital output signal (output of subtractor) by a digital-to-analog converter (DAC) comprised by the conversion circuit (DAC) to generate the analog input signal (analog output of DAC).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 6-10 and 16 -20 are rejected under 35 U.S.C. 103 as being unpatentable over by Gao et al. applied to claims 1 and 11 above, respectively, in view of Cheng et al. Pub. No. 2020/0144972.
Regarding claim 6 and 16, Fig. 1 of Gao et al. applied to claims 1 and 11 above further discloses wherein the conversion circuit ( Subtractor of output Signal Generator and DAC) comprises: a digital-to-analog converter (DAC) configured to perform the signal conversion on the digital input signal (digital signal generator) to generate a first analog input signal (analog output of DAC), but does not discloses and perform the signal conversion on the harmonic compensation digital signal to generate a second analog input signal; and a mixer configured to perform the harmonic compensation on the first the analog input signal and the second analog input signal to generate the analog input signal.
Fig. 7 of Cheng et al. Gao et al. discloses harmonic compensation apparatus comprising the conversion circuit (705) comprises: a digital-to-analog converter (DAC) configured to perform the signal conversion (710) on the digital input signal (DIN) to generate a first analog input signal (AIN1) and perform the signal conversion (710) on the harmonic compensation digital signal (DHM) to generate a second analog input signal (AIN2); and a mixer (720) configured to perform the harmonic compensation (110) on the first the analog input signal ((AIN1) and the second analog input signal (AIN2) to generate the analog input signal (AIN).
Gao et al. and Cheng et al. are common subject matter of harmonic compensation for DAC; therefore, it would have been obvious before effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Cheng et al. into Gao et al. for the purpose of providing harmonic compensation by the mixer generates the analog input signal A.sub.IN according to the first analog input signal A.sub.IN1 and the second analog input signal A.sub.IN2, in which the DAC and the mixer are included in a conversion circuit (paragraph 0027 of Cheng et al.).
Regarding claim 7 and 17, Fig. 1 of Gao et al. applied to claims 1 and 11, respectively, above does not disclose : wherein the harmonic generation process generates K harmonics according to the harmonic generation parameter, and a frequency of each of the K harmonics is N times of a frequency of the digital input signal, K being a positive integer and N being an integer larger than 1; and a gain adjusting circuit configured to adjust a gain adjusting parameter according to the compensation parameter control signal to perform a gain adjusting process of the compensation adjusting process, wherein the gain adjusting process adjusts gains of the K harmonics according to the gain adjusting parameter to generate K gain-adjusted harmonics; wherein the harmonic compensation digital signal is the K gain-adjusted harmonics or K phase-adjusted harmonics generated according to the K gain-adjusted harmonics to providing analog output signal according to the analog input signal while the harmonic distortion of the analog output signal is offset or reduced by the aforementioned harmonic predistortion (paragraph 0004 of Cheng et al.).
Fig. 4 of Cheng et al. discloses harmonic compensation apparatus (400) wherein the harmonic generation process (110; see Fig. 3 for discloses a detailed diagram of 110) generates K harmonics (paragraph 0020) according to the harmonic generation parameter (SHM in Fig. 2) , and a frequency of each of the K harmonics is N times of a frequency of the digital input signal, K being a positive integer and N being an integer larger than 1 (paragraph 0020 and claim 4 of Cheng et al.); and a gain adjusting circuit (220 in Fig. 3) configured to adjust a gain adjusting parameter (SGA IN Fig. 2) according to the compensation parameter control signal (SCTRL ) to o perform a gain adjusting process (220) of the compensation adjusting process (110), wherein the gain adjusting process (220) adjusts gains of the K harmonics (paragraph 0020) according to the gain adjusting parameter (220) to generate K gain-adjusted harmonics (SGA); wherein the harmonic compensation digital signal (DOUT) is the K gain-adjusted harmonics or K phase-adjusted harmonics generated according to the K gain-adjusted harmonics (paragraph 0020 and claim 4 of Cheng et al.).
Gao et al. and Cheng et al. are common subject matter of harmonic compensation for DAC; therefore, it would have been obvious before effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Cheng et al. into Gao et al. for the purpose of providing analog output signal according to the analog input signal while the harmonic distortion of the analog output signal is offset or reduced by the aforementioned harmonic predistortion (paragraph 0004 of Cheng et al.).
Regarding claims 8 and 18, Gao et al. and Cheng et al. applied to claims 7 and 17, respectively above, Figs. 3 and 4 of Cheng et al. further discloses wherein the harmonic compensation circuit (110) comprises: a phase adjusting circuit (230) configured to adjust a phase adjusting parameter (SGA) according to the compensation parameter control signal (SCTRL) to perform a phase adjusting process (230) of the compensation adjusting process (110), wherein the phase adjusting process (230) adjusts phases of the K gain-adjusted harmonics (Claim 4 of Cheng et al.) according to the phase adjusting parameter (Claim 5 of Cheng et al.) to generate the K phase-adjusted harmonics as the harmonic compensation digital signal (SPH=DHM).
Regarding claims 9 and 19, Gao et al. and Cheng et al. applied to claims 7 and 17, respectively, above, Figs. 3 and 4 of Cheng et al. further discloses further comprising: a delay circuit (310) configured to perform a delay operation on the digital input signal (Din) and transmit the delayed digital input signal (output of 310) to the conversion circuit (130), wherein a delay amount of the delay operation (amount delay of 310) is determined by a signal processing time of the harmonic compensation circuit (Claim 8 of Cheng et al.).
Regarding claims 10 and 20, Gao et al. and Cheng et al. applied to claims 9 and 19, respectively, above, Figs. 3 and 4 of Cheng et al. further discloses further comprising wherein the delay amount of the delay operation (310) is determined by the signal processing time of the harmonic compensation circuit and the analog output signal (Aout), and the harmonic compensation digital signal is the K gain-adjusted harmonics (Claim 9 of Cheng et al.).
Contact Information
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
07/27/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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