DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 12/27/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 02/11/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, 18 & 22, the limitation citing “having conductive tracks and first conductive vias”, it is unclear how the conductive tracks and first conductive vias are related to each other? It is further unclear if whether the conductive tracks and vias in the first stacks and second stacks are the same or different.
Regarding claims 2, cites “fourth layer, and the seventh layer” without prior citing the layers prior to reaching to fourth or seventh layers.
Regarding claims 3 & 20, cites “sixth doped and seventh doped” without prior citing the prior doped semiconductors prior to reaching to sixth and seventh doped.
Regarding claim 4 & 21, the limitation “an eight semiconductor layer” the same rejection applies as claim 2. Furthermore, the limitation "the first doped areas", there is insufficient antecedent basis for this limitation in the claim.
Claim 9 & 18 recite the limitation "the third layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “the materials of the first and second layers in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-23 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Hsu et al (US20220059618) .
Regarding claim 1, Hsu discloses an electronic device comprising(FIG 14): a semiconductor substrate having a plurality of selection transistors arranged therein(FIG 3 & 14; [0030-0032]; transistors on 200); a first interconnection stack on the semiconductor substrate including at least one level([0041]; stack 250, 248, 230, 228, 226, 224 on 200), each level including first and second insulating layers having conductive tracks and first conductive vias defined therein(M3 and M2); a third insulating layer, resting on the first interconnection stack(M1 resting on stack including in 224) ; a second interconnection stack(204 on 200), arranged on the third insulating layer(204 arranged on M1), including at least one level, each level including first and second insulating layers(M3 and M2), having the conductive tracks and the first conductive vias defined therein; a plurality of memory cells arranged in the third insulating layer(ReRAM on M1 level in 224); and at least one second conductive via extending through an entire height of the third insulating layer and coupling the conductive tracks and first conductive vias of the first and second stacks (V1 V2 vertically in CT of interconnection stacks).
Regarding claim 2, Hsu discloses wherein each memory cell includes a resistive element in contact with a fourth layer made of a phase-change material (FIG 14; ReRAM memory phase change), the seventh layer being topped with a fifth conductive layer(ReRAM conductive layers).
Regarding claim 3, Hsu discloses wherein the semiconductor substrate includes, from an upper surface, a sixth doped semiconductor layer of a first conductivity type, located on top of and in contact with a seventh doped semiconductor layer of a second conductivity type opposite to the first conductivity type (FIG 14; [0031] discloses having 200 interlayer dielectrics made of TEO with SiCN and contact layer made of Cu, AL, W etc).
Regarding claim 4, Hsu discloses wherein the semiconductor substrate includes an eighth semiconductor layer including first doped areas of the second conductivity type, each of the first doped areas of the eighth semiconductor layer being coupled to a memory cell (layer above CT 204, e.g., material of CT connected to ReRAM).
Regarding claim 5, Hsu discloses wherein the sixth semiconductor layer, the seventh semiconductor layer, and the first regions of the sixth semiconductor layer form the selection transistors (FIG 14; layers of ReRAM).
Regarding claim 6, Hsu discloses wherein the eighth semiconductor layer includes second doped areas of the first conductivity type (FIG 14[0033-0034]; 204 layer and CT connected to 204 layer material e.g., the bottom layer of ReRAM made of TaN), each of the second areas of the eighth semiconductor layer being coupled to a set of first conductive vias and of conductive tracks running through the interconnection stack (stack 250, 248, 230, 228, 226, 224 connected to 204 and CT).
Regarding claim 7, Hsu discloses wherein each of the first areas of the eighth semiconductor layer is coupled to a memory cell by a single third via extending along the entire height of the first stack (FIG 14; stack of 250, 248, 230, 228, 226, 224 CT coupled to ReRAM by Vias e.g., V1).
Regarding claim 8, Hsu discloses wherein each third via is in contact with the resistive element of the memory cell (FIG 14; V1s in contact with ReRAM).
Regarding claim 9, Hsu discloses wherein each of the first areas of the eighth semiconductor layer is coupled to a memory cell by the conductive vias and conductive tracks of the first interconnection network and by a fourth via extending in the third layer and being in contact with the resistive element of the memory cell, each fourth via being made of the same material as the second vias (FIG 14; V1s connected with ReRAM).
Regarding claim 10, Hsu discloses wherein the third layer is made of a material different from the materials of the first and second insulating layers (FIG 14; [0032-0034] SiCN and TaN).
Regarding claim 11, Hsu discloses wherein the material of the third layer has a dielectric constant higher than those of the materials of the first and second layers (FIG 14; ReRAM layer has higher dielectric than other layers).
Regarding claim 12, Hsu discloses wherein the height of the third layer is greater than the heights of the levels of the first and second stacks (FIG 14; 250 is higher height than first and second stacks).
Regarding claim 13, Hsu discloses wherein the height of the third layer is higher than the height of the memory cell (226 is higher than ReRAM).
Regarding claim 14, Hsu discloses wherein the level of the second stack closest to the third layer only includes conductive tracks in contact with the third via (FIG 14; M2 and M3 stack in contact with V2 and V1, is only in conductive tracks in contact with V1).
Regarding claim 15, Hsu discloses wherein the conductive tracks of the first and second stacks extend laterally over a surface area greater than the surface area of the first conductive vias of the same level (FIG 14; V2 extends higher than V1s).
Regarding claim 16, Hsu discloses wherein the third layer is in a single material (FIG 14; 226 224), the memory cells being entirely in the third layer (ReRAM in 224).
Regarding claim 17, Hsu discloses wherein the third layer includes not conductive tracks (FIG 14; [0039; discloses 226 being SiCN e.g., when a low temperature, the silicon carbonitride acts as an insulator).
Regarding claim 18, Hsu discloses a method of manufacturing an electronic device comprising: forming a semiconductor substrate having selection transistors arranged therein FIG 3 & 14; [0030-0032]; transistors 200); forming a first interconnection stack arranged on the semiconductor substrate and including at least one level l([0041]; stack 250, 248, 230, 228, 226, 224 on 200), each level including first and second insulating layers having conductive tracks and first conductive vias defined therein(M3 and M2); forming a third insulating layer on the first interconnection stack(M1 resting on stack including in 224); forming a plurality of memory cells arranged in the third insulating layer(ReRAM on M1 level in 224); forming a second interconnection stack(204 on 200), arranged on the third insulating layer, including at least one level, each level including first and second insulating layers having conductive tracks and first conductive vias defined therein(M1 level, and M3 and M2 having V2s and V1s); and forming at least one second conductive via extending through an entire height of the third layer(FIG 14; 250) and coupling the conductive tracks and the first conductive vias of the first and second stacks(M2 M3 coupled to V1 and V2).
Regarding claim 19, Hsu discloses wherein each memory cell includes a resistive element in contact with a fourth layer made of a phase-change material, the seventh layer being topped with a fifth conductive layer (FIG 14; ReRAM memory phase change), the seventh layer being topped with a fifth conductive layer (ReRAM conductive layers).
Regarding claim 20, Hsu discloses wherein the semiconductor substrate includes, from an upper surface, a sixth doped semiconductor layer of a first conductivity type, located on top of and in contact with a seventh doped semiconductor layer of a second conductivity type opposite to the first conductivity type (FIG 14; [0031] discloses having 200 interlayer dielectrics made of TEO with SiCN and contact layer made of Cu, AL, W etc).
Regarding claim 21, Hsu discloses wherein the semiconductor substrate includes an eighth semiconductor layer including first doped areas of the second conductivity type, each of the first doped areas of the eighth semiconductor layer being coupled to a memory cell (layer above CT 204, e.g., material of CT connected to ReRAM).
Regarding claim 22, Hsu discloses a device (FIG 14), comprising: a semiconductor substrate including first doped regions of a first conductivity type and second doped regions of a second conductivity type (FIG 14; 200 comprising dielectrics made of TEO with SiCN and contact layer made of Cu, AL, W etc) ; a first stack of first insulating layers on the semiconductor substrate( M2s of stack 250, 248, 230, 228, 226, 224 on 200); a second insulating layer on the first stack of first insulating layers(M1s on 226 224 on 200); a plurality of memory cells in the second insulating layer(ReRAM on M1); a second stack of second insulating layers on the memory cells(ReRAM on M1s); a first group of first conductive interconnection structures in the first stack of first insulating layers including a plurality of first metal tracks and first conductive vias electrically coupled to a first doped region of the plurality of first doped regions; stack 250, 248, 230, 228, 226, 224 on 200 including V2s); a plurality of second conductive vias each extending through an entirety of the first stack of insulating layers and coupling a respective memory cell to a second doped region(V1s coupled to 228); and a third conductive via extending through an entirety of the second insulating layer and coupled to the first group of conductive interconnection structures (226).
Regarding claim 23, Hsu discloses comprising a second group of second conductive interconnection structures in the second stack of second insulating layers including a plurality of second metal tracks and second conductive vias electrically coupled to the third conductive via (M1 layer comprising ReRAM connected to 226 by metal tracks and via 226 comprising V1s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lin et al (US20210272896 FIG 1; discloses interfacial layer having high and low areas, and having different level layers with different heights).
Lanzillo et al (US20230187341 FIG 2; discloses different layer metals stacked on each other).
Hwang et al (20210375905 FIG 23) & Iwata et al (US20040207011 FIG 10)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUNA A TECHANE/Primary Examiner, Art Unit 2827
Prosecution Insights