Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to remarks and amendments received 08/05/2026.
Claims 1 – 20 are pending.
Response to Arguments
Applicant's arguments filed 08/05/2026, regarding the rejection of claims 1 – 5, 7 – 9, 11 – 13, and 17 – 20, under 35 U.S.C. 102(a)(1), have been fully considered but they are not persuasive.
Applicant argues the prior art of record fails to disclose, teach, or reasonable suggest in combination the limitations “control circuitry configured to, in response to receiving a signal from a host device, initiate a test mode” and “a memory array comprising memory cells, wherein executing the test mode includes memory cell operations customized for each partition of the memory array”.
Specifically, Applicant argues: “Yang describes none of these elements, either individually or in the combinations required. Yang is directed to selecting between a “fast read mode” and a “normal read mode” based on measured bit error rates for a set of memory cells”. And “This is a runtime read-optimization selection between two normal user reads — not a test mode initiated in response to a signal from a host device”.
The Examiner disagrees.
Yang, paragraph 0079, explicitly discloses “In one embodiment, the error rate storage circuit 504 may generate a fast read mode indicator based on a number of bit errors resulting from a fast read test on a plurality of memory cells” and “In some embodiments, the error rate storage circuit 504 may generate a normal read mode indicator based on a number of bit errors resulting from a normal read test on the plurality of memory cells”.
Paragraph 0084/ 0085, more explicitly discloses: “the read mode tuning component 150 may facilitate performing read mode tuning”, “the read mode tuning component 150 includes a test circuit 602”, and “the test circuit 602 is a circuit that determines the error rate information by performing one or more tests on a set of memory cells”.
Finally, as disclosed by figure 9, the tuning circuit is activated and a test mode to determine the reading mode is performed.
The Examiner asserts Yang discloses activating the tuning circuit to determine the reading mode and as a result performs a fast read test and a normal read test, as claimed.
Applicant additionally argues: Yang does not describe “memory cell operations customized for each partition of the memory array” as a consequence of executing a test mode. Yang’s mode selection results in a single choice of read speed applied to a set of memory cells to serve a read request; Yang does not describe multiple partitions with distinct, per-partition customized operations”.
The Examiner disagrees.
Yang, paragraph 0036, discloses “determine a fast read error rate corresponding to performing a fast read on the memory block using a set of predetermined read parameters”. The examiner asserts Yang discloses read parameters for a memory block.
Paragraph 0080, additionally discloses: “Table 1 shows one embodiment of a table used to store error rate information for multiple sets of memory cells (e.g., multiple memory blocks)”. The examiner asserts Yang discloses distinct read parameters for multiple memory blocks.
Paragraph 0034, discloses “semiconductor storage device(s) that are arranged and/or partitioned into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any quantity of physical storage media on a non-volatile memory device 120). Memory units may include, but are not limited to: pages, memory divisions, blocks, sectors, collections or sets of physical storage locations (e.g., logical pages, logical blocks)”. The Examiner asserts Yang discloses partitioned memory as memory block which each may maintain unique read parameters, as claimed.
Regarding claim 8, applicant argues the prior art of record fails to disclose, teach, or reasonably suggest in combination the limitation: logic circuitry configured to generate at least one read enable signal in response to receiving a test mode sequence from a host device.
Specifically applicant argues: Yang neither uses the phrase “test mode sequence” nor describes logic circuitry that generates a read enable signal in response to receiving a test mode sequence from a host device.
The Examiner disagrees.
In light of the argument above, the Examiner asserts the disclose of “fast read test” and “normal read test” and figure 9, element 902, a read enable single would be an inherent event from the read test process.
Regarding claim 17, applicant argues the prior art of record fails to disclose, teach, or reasonably suggest in combination the limitation: circuitry configured to generate a trigger signal, wherein the trigger signal initiates a built-in self-test process for the memory device.
Specifically, Applicant argues: Yang, however, has no built-in self-test (BIST) at all. Yang’s “read mode tuning” is a read-speed optimization decision made during ordinary reads.
The Examiner disagrees.
In light of the argument above, the Examiner asserts Yang, paragraph 0084/ 0085: “the read mode tuning component 150 includes a test circuit 602. In one embodiment, the test circuit 602 is a circuit that determines the error rate information by performing one or more tests on a set of memory cells” discloses built-in self-test functionality, as claimed.
Applicant's arguments filed 08/05/2026, regarding the rejection of 6, under 35 U.S.C. 103, have been fully considered but they are not persuasive.
Applicant argues “Hsu at paragraph [0088] describes wear leveling only in the generic sense of a flash controller function” and “its passing reference to wear leveling as a background housekeeping function does not describe customizing test-mode memory cell operations based on level of wear associated with a partition”.
The Examiner disagrees.
The Examiner asserts “ware leveling” is a fundamental housekeeping element of flash memories. One of ordinary skill in the art, at the time of filing, would recognize the necessity of managing the limited number of program/ erase cycles of a flash memory and as disclosed in Hsu, use such techniques as “wear leveling” to mange the lifespan of the memory device. One of ordinary skill in the art, at the time of filing, would additionally recognize the utility of the teachings of Yang and Hsu to manage “wear leveling” as the same granularity as the read parameters for each partitioned memory block.
And in light of the arguments above the rejection of the claims is maintained.
Double Patenting (maintained)
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1 – 4, and 8 – 20 are rejected on the ground of nonstatutory double patenting over claims 14, 6, 10, 13, 21, and 23 – 28 of U.S. Patent No. 12,210,766 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/004138
Claim 1 – Patent 12,210,766
An apparatus comprising:
An apparatus comprising:
control circuitry configured to, in response to receiving a signal from a host device, initiate a test mode; and
periphery circuitry configured to receive a test mode sequence from the host device via the I/O interface, and to generate a trigger signal in response to receiving the test mode sequence; control circuitry configured to receive the trigger signal, wherein the control circuitry comprises a state machine, and
a memory array comprising memory cells, wherein executing the test mode includes memory cell operations customized for each partition of the memory array.
the state machine is configured to initiate execution by the control circuitry of a command sequence upon receiving the trigger signal; and a memory array comprising memory cells, wherein each cell has a unique address, and the command sequence specifies an order of operations performed on the memory cells.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/004138 is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,210,766. Specifically, both claim 1, of the current application 19/004138, and claim 1, of patent 12,210,766 discloses: An apparatus, comprising “receiving a signal from a host device, initiate a test mode”/ “generate a trigger signal in response to receiving the test mode sequence” and “memory cell operations customized for each partition of the memory array”/ “wherein each cell has a unique address, and the command sequence specifies an order of operations performed on the memory cells”.
One of ordinary skill in the art would recognize the apparatus disclosed by claim 1, of the current application 19/004138, as a broad recitation of the operations performed by the apparatus disclosed in claim 1 of Patent 12,210,766. An apparatus performing the operations and an apparatus capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the apparatus claim 1, of the current application 19/004138, as performing the operations of the apparatus of claim 1, of U.S. Patent 12,210,766, and as such are obvious variants of each other.
Claim 2 – Application 19/004138
Claim 1 – Patent 12,210,766
Claim 3 – Application 19/004138
Claim 10 – Patent 12,210,766
Claim 4 – Application 19/004138
Claim 1 – Patent 12,210,766
Claim 8 – Application 19/004138
Claim 1 – Patent 12,210,766
Claim 9 – Application 19/004138
Claim 21 – Patent 12,210,766
Claim 10 – Application 19/004138
Claim 23 – Patent 12,210,766
Claim 11 – Application 19/004138
Claim 24 – Patent 12,210,766
Claim 12 – Application 19/004138
Claim 25 – Patent 12,210,766
Claim 13 – Application 19/004138
Claim 26 – Patent 12,210,766
Claim 14 – Application 19/004138
Claim 26 – Patent 12,210,766
Claim 15 – Application 19/004138
Claim 27 – Patent 12,210,766
Claim 16 – Application 19/004138
Claim 28 – Patent 12,210,766
Claim 17 – Application 19/004138
Claim 1 – Patent 12,210,766
Claim 18 – Application 19/004138
Claim 4 – Patent 12,210,766
Claim 19 – Application 19/004138
Claim 6 – Patent 12,210,766
Claim 20 – Application 19/004138
Claim 13 – Patent 12,210,766
Claim Rejections - 35 USC § 102 (maintained)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5, 7 – 9, 11 – 13 and 17 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al., U.S. Publication 2019/0130989 (herein Yang).
Regarding claim 1, Yang discloses: An apparatus comprising: control circuitry configured to, in response to receiving a signal from a host device, initiate a test mode (figure 1A, element 102; paragraph 0079, 0084, 0085; figure 9); and a memory array comprising memory cells, wherein executing the test mode includes memory cell operations customized for each partition of the memory array (figure 1A, element 126, 150; paragraph 0036, 0080, 0034).
Regarding claim 2, Yang discloses: voltages for the operations are controlled based on a targeted partition of the memory array (figure 1A, element 126, 150; paragraph 0036, 0063 – 0066).
Regarding claim 3, Yang discloses: the voltages include read and write voltages (figure 1A, element 126, 150; paragraph 0036, 0056 – 0058).
Regarding claim 4, Yang discloses: executing the test mode comprises specifying data to be written into the memory cells (figure 1A, element 126, 150; paragraph 0036, 0056 – 0058).
Regarding claim 5, Yang discloses: the operations are customized based on an error rate associated with a partition (claim 1).
Regarding claim 7, Yang discloses: the operations are customized based on a type of memory cell associated with a partition (paragraph 0038).
Regarding claim 8, Yang discloses: An apparatus comprising: a memory array comprising memory cells (figure 1A, element 122, 123, 129, 150); logic circuitry configured to generate at least one read enable signal in response to receiving a test mode sequence from a host device (figure 1A, element 126, 150; paragraph 0036, 0079, 0084, 0085; figure 9); and control circuitry configured to, in response to receiving the read enable signal, sense data stored in the memory cells (figure 1A, element 126, 150; paragraph 0036, 0079, 0084, 0085; figure 9).
Regarding claim 9, Yang discloses: row and column decoders, wherein the control circuitry is further configured to, provide control signals to the row and column decoders to select the memory cells (paragraph 0052).
Regarding claim 11, Yang discloses: the at least one read enable signal is a plurality of read enable signals, each respective read enable signal causing sensing of data for a respective one of a plurality of columns in a first partition of the memory array (figure 1A, element 126, 150; paragraph 0036, 0063 – 0066).
Regarding claim 12, Yang discloses: wherein the at least one read enable signal is sent to a state machine causing the state machine to generate consecutive enable signals for enabled states, and wherein each enabled state includes a read, write, or delay operation (figure 1A, element 126, 150; paragraph 0036, 0063 – 0066).
Regarding claim 13, Yang discloses: the logic circuitry is further configured to generate trigger signals for multiple partitions of the memory array in response to receiving the test mode sequence (figure 1A, element 126, 150; paragraph 0036, 0063 – 0066).
Regarding claim 17, Yang discloses: A memory device comprising: a memory array comprising memory cells (figure 1A, element 122, 123, 129, 150); and circuitry configured to generate a trigger signal, wherein the trigger signal initiates a built-in self-test process for the memory device (figure 1A, element 126, 150; paragraph 0036, 0063 – 0066, 0079, 0084, 0085; figure 9).
Regarding claim 18, Yang discloses: the memory cells are located at an array address in the memory array, the array address is provided with the trigger signal, and the array address corresponds to an address provided by a host device (figure 1A, element 126, 150; paragraph 0036, 0055, 0063 – 0066).
Regarding claim 19, Yang discloses: address latches configured to latch the array address from the circuitry, wherein the array address is held by the address latches until a command sequence is completed (paragraph 0055).
Regarding claim 20, Yang discloses: registers to store parameters provided by the circuitry with the trigger signal, wherein the parameters specify an order of operations in the command sequence (paragraph 0047 – 0050).
Claim Rejections - 35 USC § 103 (maintained)
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, in view of Hsu et al., U.S. Publication 2023/0350606 (herein Hsu).
Regarding claim 6, Yang teaches the limitations of the parent claim. Yang does not explicitly teach: the operations are customized based on level of wear associated with a partition.
Hsu teaches: wear leveling (paragraph 0088).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Yang: executing the test mode includes memory cell operations customized for each partition of the memory array; with the teaching of Hsu: wear leveling for the purpose of managing the state of a memory (paragraph 0088). Memory testing is well-known in the art (abstract). Wear leveling is a well-known design choice in the art (paragraph 0088). Wear leveling state of a flash memory is a well-known parameter (paragraph 0088). One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result.
Allowable Subject Matter
Claims 10 and 14 – 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and a resolution of the nonstatutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Louie; Benjamin et al. US 20060048033 A1
Roohparvar, Frankie F. US 20040225934 A1
Shore; Michael A. US 20110225471 A1
Cho; Hoon et al. US 9564233 B1
Roohparvar; Frankie F. et al. US 6067598 A
control circuitry configured to, in response to receiving a signal from a host device, initiate a test mode; and
a memory array comprising memory cells, wherein executing the test mode includes memory cell operations customized for each partition of the memory array.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
