CTNF 19/004,156 CTNF 99226 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claim 8 and 20 are objected to for being grammatically confusing. Necessary amendment is required. Allowable Subject Matter Claim 8 and 20 are further objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as well as necessary amendments are made to address the previously mentioned objections. Claim 8 recites The processor of claim 7, wherein the second circuitry is to said load said at least the portion of the 128-bit block of data from the memory with an address based on the 64-bit pointer and having a value of bit 63 of the 64-bit pointer in bits [60:57]. The Examiner was unable to find the above claim limitation in a prior art or in an obvious combination of multiple prior art. Although Radovic teaches a specialized second circuitry [0034] that can be used to allow access to the associated block of data when specific conditions are met [0042], it does not teach “an address based on the 64-bit pointer and having a value of bit 63 of the 64-bit pointer in bits [60:57].” Per claim 20, similar claim language as claim 8 is recited and thus is allowable for similar reasons pending the necessary amendments. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-7, 9, 10-13, 15-16, 21-25, 28-29, 31-36 of this application is patentably indistinct from claims in the following patents: #10162694, #10776190, #11645135. Claims 1, 13, 20, 22 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over copending Application No. 19004156; they are considered rejected under provisional nonstatutory double patenting because the patentably indistinct claims have not in fact been patented. Although the claims at issue are not identical, they are not patentably distinct from each other because of the reasons below. Patent #10162694 Patent #10776190 Patent #11645135 Application #19004156 Claim 1 Claim 1 and 3. Generating the fault clause is not taught explicitly however it is an obvious variant. Claim 1, 3, and 8. Generating the fault clause is not taught explicitly however it is an obvious variant. Claim 1 Claim 1, 14, and 15 Claim 2 Claim 7 Claim 3 Obvious variant. (Vasudevan, col 12, lines 53-54, col 13 lines 8-10.). Same as 14977354 Claim 8 Claim 4 Claim 6 Claim 6 Claim 5 Claim 2 Claim 2 Claim 6 Claim 4 Claim 4 Claim 4 Claim 7 Claim 1 Claim 9 Claim 5 Claim 5 Claim 6 Claim 10 Claim 10 Claim 11 Claim 11 Claim 12 Obvious variant Claim 13 Obvious variant: (Radovic , FIG. 2) Claim 7 Claims 1, 8, 14, and 15 Claim 15 Obvious variant: (Radovic, FIG. 2); Claim 16 Obvious variant: (Radovic, FIG. 2); Claim 20 Claim 10 Claim 21 Claim 23 Claim 32 Obvious variant Claim 33 Obvious variant Claim 34 Obvious variant Claim 35 Obvious variant As per claim 22, it recites similar claim language as claim 13, and thus is considered a double patent for similar reasons. It further recites the following limitation, but it is taught by Radovic (the exact reference number is seen in the 35 U.S.C. 103 section below). load the 128-bit block of data from the memory when the value from the 64-bit pointer matches the value from the memory (Radovic, [0042] the memory can be accessed. Because loading is one form of accessing the data, it is the Examiner’s interpretation that the prior art teaches this claim limitation). Per claim 23, it recites similar claim language as claim 14 and is considered a double patent for similar reasons Per claim 24, it recites similar claim language as claim 15. Instead of “3 most significant bits” it recites “4 most significant bits,” but the same teaching from the prior art applies and thus is considered a double patent for similar reasons. Per claim 25, it recites similar claim language as claim 16. Instead of “3 most significant bits” it recites “4 most significant bits,” but the same teaching from the prior art applies and thus is considered a double patent for similar reasons. Per claims 28, 29, the claim language recites similar claim language as claims 6, 9, and thus are considered a double patent for similar reasons. Per claim 31, the claim language recites similar claim language as claim 12. It additionally recites that the field is not in 4 most significant bits, which is taught by the same prior art citing in claim 15 and thus is considered a double patent for similar reasons. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1, 3-5, 11, 13-16, 18, 22, 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Radovic et al (US 20120246437 A1) from henceforth referred to as Radovic in view of Vasudevan et al (US 9710279 B2) from henceforth referred to as Vasudevan in further view of Kosuke et al (JP 2002196975 A) from henceforth referred to as Kosuke . Per claim 1, Radovic teaches A processor ([0026] a processor) comprising: first circuitry to … ([0054] in some embodiments, the masking mechanisms can be implemented as dedicated hardware modules in processor, and can include one or more specialized circuits for performing the operations of the mechanism, therefore, it is the Examiner’s interpretation that the “second circuitry” later in the claim refers to this specialized circuits that deals with the masking mechanism, and the claim language “first circuitry” is used to distinguish itself from it), the instruction to operate on a 64-bit pointer ([0026] during operation, the processor may need to reference virtual memory pointer to access data at the associated virtual address), the 64-bit pointer comprising an address to … block of data in memory and a 4-bit value in bits [60:57] (FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer); and second circuitry coupled with the first circuitry, the second circuitry, to perform operations associated with the instruction ([0054] in some embodiments, the masking mechanisms can be implemented as dedicated hardware modules in processor, and can include one or more specialized circuits for performing the operations of the mechanism), including to: access a 4-bit value corresponding to the 128-bit block of data; ([0042] the version number is stored in the unused pointer bits, and is double checked as a way to detect memory corruption. Although not explicitly stated, during the process of double-checking, this 4-bit value is accessed) determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the …block of data; and ([0042] the system can double-check the version numbers during memory accesses to confirm that the memory buffer being accessed via a pointer is still valid and that the access is allowed) generate a fault ([0036] generate a fault during the memory corruption checks) when the 4-bit value from the 64-bit pointer does not match the 4-bit value corresponding to the 128-bit block of data. ([0042] teaches the conditional state of the values matching) Radovic fails to teach decode an instruction However, Vasudevan teaches decode an instruction (col 2 lines 60-62 decode unit decode instructions) It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Vasudevan with that of Radovic because by including memory corruption checks by utilizing the unused bits of memory pointers as shown in Radovic, it helps detect when unusual memory address access is detected (Radovic, [0036]). Radovic in view of Vasudevan fails to explicitly teach [a 64 bit pointer pointing to a…] 128-bit block of data However, Kosuke teaches [a 64 bit pointer pointing to a…] 128-bit block of data (page 11, 5 th paragraph, 64 bit pointer used to reference a 128 bit of data) It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Radovic in view of Vasudevan with the teachings of Kosuke because Kosuke simply shows a detailed description of how a 64-bit architecture may operate. Per claim 3, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 2, wherein the table is to be stored separately from the 128-bit block of data (Vasudevan, col 12, lines 53-54, teaches storing the data in a queue which is separate from the data array P which is represented in col 13 lines 8-10. Although the data in the queue in Vasudevan is used differently than that of Radovic’s use, it still teaches the concept of data needed for memory access being stored in a functionally-table-like structure that is separate from the block of memory). Per claim 4, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 1, further comprising a first register to store a first base of a first table, the first table to have the 4-bit value corresponding to the 128-bit block of data (Vasudevan, col 10 line 62-col 11 line 10, teaches storing data in queue in which it is referenced through position and offset information. It is the Examiner’s interpretation that this is functionally similar to storing and accessing data from a table; the base of the queue is stored in order for the queue to be accessed). Per claim 5, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 4, further comprising a second register to store a second base of a second table, the second table to have a plurality of 4-bit values for a different region of the memory than a region corresponding to the first table (Vasudevan, col 10 line 62-col 11 line 10, teaches storing data in queue in which it is referenced through position and offset information. It is the Examiner’s interpretation that this is functionally similar to storing and accessing data from a table; the base of the queue is stored in order for the queue to be accessed. Additionally, this concept of a table can easily be expanded to multiple smaller tables since the usage of multiple smaller tables is functionally similar to one large table since only the position and the offset value would be changed once the base is saved). Per claim 11, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 1, wherein the processor is a general-purpose CPU core, the general-purpose CPU core further comprising: a branch prediction circuitry; a register rename circuitry; and scheduler circuitry. (Vasudevan, col 2, lines 56-57, branch prediction unit) As per claim 13, it recites similar claim language as claim 1, and thus is rejected for similar reasons. It further recites a value in a field, the field more significant than the address and not including at least one most significant bit of the 64-bit pointer (Radovic , FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer) Per claim 14, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 13, wherein the field has a size of 4 bits. (Radovic, FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer; the field can be any number of bits within [63:40] ); Per claim 15, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 13, wherein the field is not in 3 most significant bits. (Radovic, FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer; any of the bits [63:40] can be used to store metadata, and thus could exclude the three most significant bits ); Per claim 16, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 13, wherein the field has a size of 4 bits, and wherein the field is not in 3 most significant bits. (Radovic, FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer; any of the bits [63:40] can be used to store metadata, and thus could exclude the three most significant bits ); Per claim 18, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 13, further comprising: a first register to store a first base of a first table, the first table to have the value corresponding to the 128-bit block of data (col 10 line 62-col 11 line 10, teaches storing data in queue in which it is referenced through position and offset information. It is the Examiner’s interpretation that this is functionally similar to storing and accessing data from a table; the base of the queue is stored in order for the queue to be accessed); and a second register to store a second base of a second table, the second table to have a plurality of values for a different region of the memory than a region corresponding to the first table. (Vasudevan, col 10 line 62-col 11 line 10, teaches storing data in queue in which it is referenced through position and offset information. It is the Examiner’s interpretation that this is functionally similar to storing and accessing data from a table; the base of the queue is stored in order for the queue to be accessed. Additionally, this concept of a table can easily be expanded to multiple smaller tables since the usage of multiple smaller tables is functionally similar to one large table since only the position and the offset value would be changed once the base is saved). As per claim 22, it recites similar claim language as claim 13, and thus is rejected for similar reasons. It further recites load the 128-bit block of data from the memory when the value from the 64-bit pointer matches the value from the memory (Radovic, [0042] the memory can be accessed. Because loading is one form of accessing the data, it is the Examiner’s interpretation that the prior art teaches this claim limitation) Per claim 23, it recites similar claim language as claim 14 and are rejected for similar reasons Per claim 24, it recites similar claim language as claim 15. Instead of “3 most significant bits” it recites “4 most significant bits,” but the same teaching from the prior art applies and thus are rejected for similar reasons. Per claim 25, it recites similar claim language as claim 16. Instead of “3 most significant bits” it recites “4 most significant bits,” but the same teaching from the prior art applies and thus are rejected for similar reasons . 07-21-aia AIA Claim s 2, 6, 7, 9, 10, 12, 17, 19, 21, 26-31 are rejected under 35 U.S.C. 103 as being unpatentable over Radovic in view of Vasudevan in view of Kosuke in further view of Armv8.5-A Memory Tagging Extension (2019) from henceforth referred to as MTE-NPL: Per claim 2, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 1, wherein the 4-bit value corresponding to the 128-bit block of data is to be accessed (Kosuke, page 11, 5 th paragraph, 64 bit pointer is used to reference a 128 bit block of data) from a table in the memory (Vasudevan, col 10 line 62-col 11 line 10, teaches storing data in queue in which it is referenced through position and offset information. It is the Examiner’s interpretation that this is functionally similar to storing and accessing data from a table) Radovic in view of Vasudevan in view of Kosuke fails to teach explicilty … a plurality of 4-bit values respectively corresponding to different ones of a plurality of 128-bit blocks of data in the memory. However, MTE-NPL teaches … a plurality of 4-bit values respectively corresponding to different ones of a plurality of 128-bit blocks of data in the memory. (MTE-NPL, page 3, “Memory safety with MTE” section utilizes storing a tag for each associated data for matching). It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Radovic in view of Vasudevan with that of MTE-NPL because MTE-NPL offers one implementation example of utilizing the unused 4-bit data in the 64-bit pointer in order to detect any memory corruption. Per claim 6, Radovic in view of Vasudevan in view of Kosuke fails to explicitly teach The processor of claim 1, wherein the second circuitry is to access the 4-bit value from the memory with an address that lacks the 4-bit value from the 64-bit pointer. MTE-NPL teaches The processor of claim 1, wherein the second circuitry is to access the 4-bit value from the memory with an address that lacks the 4-bit value from the 64-bit pointer (page 3, “Memory safety with MTE” section, lock/key matching mechanism is used in order to detect memory corruption by storing the tagged information in the unused bits in the pointer. The values need to be accessed in order to be compared. If there is a mismatch, as in, the value that is accessed is not the 4-bit value from the 64-bit pointer, then memory corruption is detected. It is the Examiner’s interpretation that this use case of memory corruption detection teaches the claim language. “Lacks the 4-bit value from the 64-bit pointer” is interpreted as the aforementioned mismatch). Per claim 7, Radovic in view of Vasudevan in view of Kosuke fails to teach The processor of claim 1, wherein the second circuitry is to load at least a portion of the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data. MTE-NPL teaches The processor of claim 1, wherein the second circuitry is to load at least a portion of the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data (page 3, “Memory safety with MTE” section, lock/key matching mechanism is used in order to detect memory corruption by storing the tagged information in the unused bits in the pointer) Per claim 9, Radovic in view of Vasudevan in view of Kosuke in view of MTE-NPL fails to teach The processor of claim 1, wherein, in addition to the 4-bit value from the bits [60:57], the processor is also to protect the 64-bit pointer based on another value from the 64-bit pointer. (MTE-NPL, page 2, “Threat Model” section, 3 rd paragraph, pointer authentication code). Per claim 10, Radovic in view of Vasudevan in view of Kosuke in view of MTE-NPL teaches The processor of claim 1, further comprising a register to control whether the second circuitry is to determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data. (Radovic, [0034] a specialized second circuitry is used to [0042] allow access to the associated block of data utilizing the 4-bit value corresponding to the 128-bit block of data; MTE-NPL, page 3, teaches the matching) Per claim 12, Radovic in view of Vasudevan in view of Kosuke in view of MTE-NPL teaches The processor of claim 1, wherein the second circuitry is to load at least a portion of the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data (MTE-NPLpage 3, “Memory safety with MTE” section, lock/key matching mechanism is used in order to detect memory corruption by storing the tagged information in the unused bits in the pointer), wherein the 4-bit value corresponding to the 128-bit block of data is to be accessed from a table in the memory, wherein the table is to be stored separately from the 128-bit block of data (Vasudevan, col 12, lines 53-54, teaches storing the data in a queue which is separate from the data array P which is represented in col 13 lines 8-10. Although the data in the queue in Vasudevan is used differently than that of Radovic’s use, it still teaches the concept of data needed for memory access being stored in a functionally-table-like structure that is separate from the block of memory), and wherein the processor further comprises a register to store a first base of a table (col 10 line 62-col 11 line 10, teaches storing data in queue in which it is referenced through position and offset information. It is the Examiner’s interpretation that this is functionally similar to storing and accessing data from a table. The base of the queue is stored in order to be referenced). Per claim 17, Radovic in view of Vasudevan in view of Kosuke teaches The processor of claim 13, wherein the value corresponding to the 128-bit block of data is to be accessed from a table in the memory, the table to have a ... of values respectively corresponding to… 128-bit blocks of data in the memory (Kosuke, page 11, 5 th paragraph, 64 bit pointer used to reference a 128 bit of data), and wherein the table is to be stored separately from the 128-bit block of data. (Vasudevan, col 12, lines 53-54, teaches storing the data in a queue which is separate from the data array P which is represented in col 13 lines 8-10. Although the data in the queue in Vasudevan is used differently than that of Radovic’s use, it still teaches the concept of data needed for memory access being stored in a functionally-table-like structure that is separate from the block of memory) Radovic in view of Vasudevan in view of Kosuke fails to explicitly teach plurality of values… corresponding to different ones of a plurality of …block of data in the memory (MTE-NPL, page 3, “Memory safety with MTE” section utilizes storing a tag for each associated data for matching). MTE-NPL teaches plurality of values… corresponding to different ones of a plurality of …block of data in the memory (MTE-NPL, page 3, “Memory safety with MTE” section utilizes storing a tag for each associated data for matching). Claim 19 recites similar claim limitation as claim 7. Instead of “4-bit value,” it additionally recites “the value,” but they are functionally equivalent and therefore the claim is rejected for similar reason. Claim 21 recites similar claim language as claim 9, but instead of “4-bit value,” it recites “the value,” but they are functionally equivalent and therefore the claim is rejected for similar reason. Per claim 26, Radovic in view of Vasudevan in view of Kosuke in further view of MTE-NPL teaches The processor of claim 22, wherein the 64-bit pointer is to indicate whether the second circuitry is to determine whether the value from the 64-bit pointer matches value from the memory corresponding to the 128-bit block of data (MTE-NPL, page 3, “Memory safety with MTE” section, lock/key matching mechanism is used in order to detect memory corruption by storing the tagged information in the unused bits in the pointer). Per claim 27, Radovic in view of Vasudevan in view of Kosuke in further view of MTE-NPL teaches The processor of claim 22, wherein a value in the 64-bit pointer is to indicate whether the second circuitry is to determine whether the value from the 64-bit pointer matches the value from the memory corresponding to the 128-bit block of data (MTE-NPL, page 3, “Memory safety with MTE” section, lock/key matching mechanism is used in order to detect memory corruption by storing the tagged information in the unused bits in the pointer). Per claims 28-30, the claim language recites similar claim language as claims 6, 9, and 17, and thus are rejected for similar reasons. Per claim 31, the claim language recites similar claim language as claim 12. It additionally recites that the field is not in 4 most significant bits, which is taught by the same prior art citing in claim 15 and thus are rejected for similar reasons . 07-21-aia AIA Claim s 32-36 are rejected under 35 U.S.C. 103 as being unpatentable over Radovic in view of Vasudevan in view of MTE-NPL in further view of Kosuke . As per claim 32, Radovic teaches A non-transitory machine-readable storage media storing instructions that when executed cause a machine to perform operations ([0020] non-transitory computer-readable storage medium with stored instructions that can be read and executed), including to: receive a request to allocate a block of memory from an application; ([0038] a system call can be invoked by applications to enable loading a program and determining how many bits of memory pointer can or will be used to store other data) allocate the block of memory; ([0038] the address space is setup accordingly after determining how many bits of memory pointer can or will be used to store other data) generate a value ([0038] data is stored. It is the examiner’s interpretation that the value must be generated prior to it being stored); generate a 64-bit pointer, the 64-bit pointer including an address to a … portion of the block of memory, and the 64-bit pointer including a copy of the value in a field, the field more significant than the address and not including at least one most significant bit of the 64-bit pointer (FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer; [0038] the pointer is setup); … provide the 64-bit pointer including the address and the copy of the value to the application. ([0035] a range of different software or hardware entities may need to access the masking mechanisms) Radovic fails to explicitly teach store a copy of the value in an entry of a table in memory, the entry corresponding to… portion of the block of memory [pointer pointing to a…] 128 bit block of data However, Vasudevan teaches in an entry of a table in memory (col 10 line 62-col 11 line 10, teaches storing data in queue in which it is referenced through position and offset information. It is the Examiner’s interpretation that this is functionally similar to storing and accessing data from a table) It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Radovic and Vasudevan because the data storage using queue (with the position and offset data to pinpoint the exact location) is functionally similar to data storage using a table. Radovic in view of Vasudevan fails to teach store a copy of the value in …, the entry corresponding to… portion of the block of memory However, MTE-NPL teaches store a copy of the value in …, the entry corresponding to… portion of the block of memory (MTE-NPL, page 3, last paragraph, details the architectural detail of generating the tag and storing the data for multiple blocks of memory). It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Radovic in view of Vasudevan with that of MTE-NPL because MTE-NPL offers one implementation example of utilizing the unused 4-bit data in the 64-bit pointer in order to detect any memory corruption. Radovic in view of Vasudevan in further view of MTE-NPL fails to teach [a 64 bit pointer pointing to a…] 128-bit block of data However, Kosuke teaches [a 64 bit pointer pointing to a…] 128-bit block of data (page 11, 5 th paragraph, 64 bit pointer used to reference a 128 bit of data) It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Radovic in view of Vasudevan in view of MTE-NPL with the teachings of Kosuke because Kosuke simply shows a detailed description of how a 64-bit architecture may operate. Per claim 33, Radovic in view of Vasudevan in view of MTE-NPL in further view of Kosuke teaches The non-transitory machine-readable storage media of claim 32, wherein the field has a size of 4 bits and wherein the field is not in 3 most significant bits. (Radovic, FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer; any of the bits [63:40] can be used to store metadata, and thus could exclude the 3 most significant bits); Per claim 34, Radovic in view of Vasudevan in view of MTE-NPL in further view of Kosuke teaches The non-transitory machine-readable storage media of claim 32, wherein the field has a size of 4 bits and wherein the field is not in 4 most significant bits. (Radovic, FIG. 2, bits [63:40] is available for storing metadata and bits [39:0] is used to store the memory addresses in the 64-bit pointer; any of the bits [63:40] can be used to store metadata, and thus could exclude the three most significant bits ); Per claim 35, Radovic in view of Vasudevan in view of MTE-NPL in further view of Kosuke teaches The non-transitory machine-readable storage media of claim 32, wherein the table is to be stored separately from the block of memory (Vasudevan, col 12, lines 53- 54, teaches storing the data in a queue which is separate from the data array P which is represented in col 13 lines 8-10. Although the data in the queue in Vasudevan is used differently than that of Radovic’s use, it still teaches the concept of data needed for memory access being stored in a functionally-table-like structure that is separate from the block of memory) Per claim 36, Radovic in view of Vasudevan in view of MTE-NPL in further view of Kosuke teaches The non-transitory machine-readable storage media of claim 32, wherein the table is to have a plurality of different values each corresponding to a different 128-bit portion of the block of memory (MTE-NPL, page 3, last paragraph, details the architectural detail of generating the tag and storing the data for multiple blocks of memory). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYO LISA RUSIN whose telephone number is (703)756-1679. The examiner can normally be reached Monday-Friday 8:30 - 5:00 EST. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.L.R./Examiner, Art Unit 2114 /ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114 Application/Control Number: 19/004,156 Page 2 Art Unit: 2114 Application/Control Number: 19/004,156 Page 3 Art Unit: 2114 Application/Control Number: 19/004,156 Page 4 Art Unit: 2114 Application/Control Number: 19/004,156 Page 5 Art Unit: 2114 Application/Control Number: 19/004,156 Page 6 Art Unit: 2114 Application/Control Number: 19/004,156 Page 7 Art Unit: 2114 Application/Control Number: 19/004,156 Page 8 Art Unit: 2114 Application/Control Number: 19/004,156 Page 9 Art Unit: 2114 Application/Control Number: 19/004,156 Page 10 Art Unit: 2114 Application/Control Number: 19/004,156 Page 11 Art Unit: 2114 Application/Control Number: 19/004,156 Page 12 Art Unit: 2114 Application/Control Number: 19/004,156 Page 13 Art Unit: 2114 Application/Control Number: 19/004,156 Page 14 Art Unit: 2114 Application/Control Number: 19/004,156 Page 15 Art Unit: 2114 Application/Control Number: 19/004,156 Page 16 Art Unit: 2114 Application/Control Number: 19/004,156 Page 17 Art Unit: 2114 Application/Control Number: 19/004,156 Page 18 Art Unit: 2114 Application/Control Number: 19/004,156 Page 19 Art Unit: 2114 Application/Control Number: 19/004,156 Page 20 Art Unit: 2114 Application/Control Number: 19/004,156 Page 21 Art Unit: 2114 Application/Control Number: 19/004,156 Page 22 Art Unit: 2114 Application/Control Number: 19/004,156 Page 23 Art Unit: 2114
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