DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22 and 31-39 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites “loading the plurality of voxels into a memory”. Claim 22, which depends, recites “loading at least a portion of the plurality of subsets into the memory”. As claim 21 requires all of the voxels to be loaded into the memory, it is unclear how one could load only a portion of the subsets of voxels into memory as stated in claim 22. Further clarification is required.
Dependent claims 30-39 do not remedy the deficiency of claim 22 and therefore inherit the 112(b) issue as outlined above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 23 and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akazawa et al. (US 2012/0126125).
Regarding claim 21, Akazawa et al. discloses a method comprising:
obtaining raw data corresponding to radiation rays within a volume (“Specifically, when the patient M is medicated with the radioactive drug, two gamma rays will be generated by annihilation of a positron of a positron-emitting RI. The coincidence counting circuit 9 checks positions of the scintillator blocks 31 (see FIG. 2) and incidence timing of the gamma rays, and determines the inputted event to be proper data only when the gamma rays impinge on two scintillator blocks 31 at opposite side of the patient M at the same time” at paragraph 0055, line 1);
determining, among the radiation rays, a radiation ray passing a plurality of voxels corresponding to a portion of the volume based on the raw data (“As shown in FIG. 6, the direction vector parallel to the LOR is defined as d (d.sub.x, d.sub.y, d.sub.z) (where .parallel.d.parallel.=1, unit vector), and a main direction of the LOR is determined based on the vector d of the LOR and the direction of arrangement of the gamma-ray detectors 3” at paragraph 0067, line 5; “Sections of image space through which the LOR passes are determined based on the main direction determined in step S1. In this embodiment, planes intersected at right angles by the main direction are determined to be sections of image space through which the LOR passes” at paragraph 0069, line 1);
loading the plurality of voxels into a memory (“In this embodiment, data relating to coincidence counting such as values of coincidence counting (counts) given by the coincidence counting circuit 9, detector pairs each consisting of two gamma-ray detectors 3 having counted coincidences, and LORs, and various data resulting from arithmetic processing by the arithmetic processing unit 10, are written to and stored in the RAM and are read from the RAM as necessary” at paragraph 0053, line 3); and
performing a calculation relating to the loaded voxels by a plurality of processing threads in a parallel hardware architecture to generate an image of the volume (“(Step S4) Forward projection process An arithmetic process is carried out in parallel on list data in the calculation areas determined in step S3. Specifically, a system matrix is obtained for each voxel j, and in the range of the determined calculation area, a projection value is updated by multiplying the portion indicated FP in equation (1) noted hereinbefore by the pixel value, followed by addition. The parallel calculations with equation (1) noted hereinbefore are carried out for each LOR. Regarding the memory for substituting the projection value, it is arranged for writing one element per event, per subset, which is written as shown in FIG. 8, for example. "Thread.sub.--0", "Thread.sub.--1", "Thread.sub.--2", "Thread.sub.--3", . . . in FIG. 8 show processing units of parallel data written. Each LOR is in a one-to-one relationship to each thread per subset” at paragraph 0072) to generate an image of the volume (“The arithmetic processing unit 10 carries out image reconstruction by forward projection process and back projection process, and obtains images of the patient M. The images are sent to the output unit 7 through the controller 5” at paragraph 0056, line 2).
Regarding claim 23, Akazawa et al. discloses a method wherein the loading the plurality of voxels into a memory includes: loading the voxels into the memory based on relative locations of the plurality of voxels along a radiation direction of the radiation ray (“Similarly, one of the z coordinates of the starting point and terminal point is a minimum coordinate (indicated "Min.sub.--1" in FIG. 7), and the other is a maximum coordinate (indicated "Max.sub.--1" in FIG. 7). That is, on the sections, the LOR will cross a maximum coordinate position from a minimum coordinate position on the respective sections. Therefore, the calculation area crossed by the LOR is an area marked out by Min.sub.--0, Max.sub.--0, Min.sub.--1 and Max.sub.--1 as shown in FIG. 7” at paragraph 0071, line 16).
Regarding claim 40, Akazawa et al. discloses a system, comprising:
at least one storage medium including a set of instructions (“The ROM stores beforehand programs for imaging, including various types of nuclear medicine diagnosis, for example. The programs are executed by the controller 5 and arithmetic processing unit 10 to carries out nuclear medicine diagnoses corresponding to the programs, respectively. In this embodiment, in particular, in order to cause a parallel computing architecture called "CUDA (provided by NVIDIA Corp.)" to perform parallel calculations using the GPU, programs relating to CUDA are stored beforehand in the ROM, and processes in steps S1-S5 to be described hereinafter are executed by the arithmetic processing unit 10 executing the programs relating to CUDA” at paragraph 0053, line 10); and
at least one processor (“The controller 5 and arithmetic processing unit 10 are formed of a central processing unit (CPU) and the like” at paragraph 0051, line 3) configured to communicate with the at least one storage medium, wherein when executing the set of instructions, the at least one processor is configured to direct the system to perform operations including:
obtaining raw data corresponding to radiation rays within a volume (“Specifically, when the patient M is medicated with the radioactive drug, two gamma rays will be generated by annihilation of a positron of a positron-emitting RI. The coincidence counting circuit 9 checks positions of the scintillator blocks 31 (see FIG. 2) and incidence timing of the gamma rays, and determines the inputted event to be proper data only when the gamma rays impinge on two scintillator blocks 31 at opposite side of the patient M at the same time” at paragraph 0055, line 1);
determining, among the radiation rays, a radiation ray passing a plurality of voxels corresponding to a portion of the volume based on the raw data (“As shown in FIG. 6, the direction vector parallel to the LOR is defined as d (d.sub.x, d.sub.y, d.sub.z) (where .parallel.d.parallel.=1, unit vector), and a main direction of the LOR is determined based on the vector d of the LOR and the direction of arrangement of the gamma-ray detectors 3” at paragraph 0067, line 5; “Sections of image space through which the LOR passes are determined based on the main direction determined in step S1. In this embodiment, planes intersected at right angles by the main direction are determined to be sections of image space through which the LOR passes” at paragraph 0069, line 1);
loading the plurality of voxels into a memory (“In this embodiment, data relating to coincidence counting such as values of coincidence counting (counts) given by the coincidence counting circuit 9, detector pairs each consisting of two gamma-ray detectors 3 having counted coincidences, and LORs, and various data resulting from arithmetic processing by the arithmetic processing unit 10, are written to and stored in the RAM and are read from the RAM as necessary” at paragraph 0053, line 3); and
performing a calculation relating to the loaded voxels by a plurality of processing threads in a parallel hardware architecture to generate an image of the volume (“(Step S4) Forward projection process An arithmetic process is carried out in parallel on list data in the calculation areas determined in step S3. Specifically, a system matrix is obtained for each voxel j, and in the range of the determined calculation area, a projection value is updated by multiplying the portion indicated FP in equation (1) noted hereinbefore by the pixel value, followed by addition. The parallel calculations with equation (1) noted hereinbefore are carried out for each LOR. Regarding the memory for substituting the projection value, it is arranged for writing one element per event, per subset, which is written as shown in FIG. 8, for example. "Thread.sub.--0", "Thread.sub.--1", "Thread.sub.--2", "Thread.sub.--3", . . . in FIG. 8 show processing units of parallel data written. Each LOR is in a one-to-one relationship to each thread per subset” at paragraph 0072) to generate an image of the volume (“The arithmetic processing unit 10 carries out image reconstruction by forward projection process and back projection process, and obtains images of the patient M. The images are sent to the output unit 7 through the controller 5” at paragraph 0056, line 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Akazawa et al. and Szirmay-Kalos et al. (US 2015/0213630).
Regarding claim 24, Akazawa et al. discloses a method wherein the parallel hardware architecture is implemented by a processor (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” At paragraph 0051, line 5).
Akazawa et al. does not explicitly disclose that the parallel hardware architecture is implemented by multiple processors.
However, Szirmay-Kalos et al. teaches a method in the same field of endeavor of SIMD processing, wherein the processor comprising a plurality of scalar processors (“On the other hand, GPGPU (General Purpose GPU) APIs like CUDA (Compute Unified Device Architecture) (NVIDIA, http://developer.nvidia.com/cuda, in: The CUDA Homepage) and OpenCL (Open Computing Language) provide access to the multiprocessors of the GPU where each multiprocessor contains a set of scalar processors sharing the instruction unit, and therefore acting as a SIMD (Single Instruction. Multiple Data) hardware” at paragraph 0011, line 8).
As Akazawa et al. uses this particular SIMD CUDA device, Akazawa et al. demonstrates that the at least one graphic processing unit comprises a plurality of processors.
Regarding claim 25, the Akazawa et al. and Szirmay-Kalos et al. combination discloses that the multiple processors include at least one of a graphic processing unit (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” Akazawa et al. at paragraph 0051, line 5), a central processing unit, a microprocessor unit, a computer, or a cloud processing unit.
Regarding claim 26, Akazawa et al. discloses a method wherein the parallel hardware architecture is implemented by a processor (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” At paragraph 0051, line 5).
Akazawa et al. does not explicitly disclose that he parallel hardware architecture is implemented by multiple processing kernels of one processor.
However, Szirmay-Kalos et al. teaches a method in the same field of endeavor of SIMD processing, wherein the processor comprising a plurality of scalar processors (“On the other hand, GPGPU (General Purpose GPU) APIs like CUDA (Compute Unified Device Architecture) (NVIDIA, http://developer.nvidia.com/cuda, in: The CUDA Homepage) and OpenCL (Open Computing Language) provide access to the multiprocessors of the GPU where each multiprocessor contains a set of scalar processors sharing the instruction unit, and therefore acting as a SIMD (Single Instruction. Multiple Data) hardware” at paragraph 0011, line 8).
As Akazawa et al. uses this particular SIMD CUDA device, Akazawa et al. demonstrates that the at least one graphic processing unit comprises a plurality of processing kernels.
Claim(s) 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Akazawa et al. and Scheins et al. (“Fully-3D PET Image Reconstruction Using Scanner-Independent, Adaptive Projection Data and Highly Rotation-Symmetric Voxel Assemblies”).
Regarding claim 27, Akazawa et al. discloses a method as described in claim 21 above.
Akazawa et al. does not disclose determining an available resource of each of at least one processor in the parallel hardware architecture; and allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction comprising:
determining an available resource of each of at least one processor in the parallel hardware architecture (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5); and
allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor (overall processing time is used to determine which processing node to utilize for data processing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of Akazawa et al. to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 28, Akazawa et al. discloses a method wherein the parallel hardware architecture includes at least one processor (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” At paragraph 0051, line 5).
Akazawa et al. does not disclose that the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction wherein the parallel hardware architecture includes at least one processor, the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5; the fastest processing node therefore is selected for processing the data based upon the processing time exceeding the threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of Akazawa et al. to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 29, Scheins et al. discloses a method wherein the determining the at least one processor from the candidate processors based on the determination result comprises: in response to determining that the amount of computational resources does not exceed the threshold amount, determining one candidate processor from the candidate processors as the at least one processor (given that the time threshold is satisfied, the processing may remain on a particular processing node); or in response to determining that the amount of computational resources exceeds the threshold amount, determining at least two candidate processors from the candidate processors as the at least one processor.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-26 and 30-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 and 14 of U.S. Patent No. 12,182,908. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘908 are an obvious variant of the instant claims.
Regarding claim 21,‘908 discloses a method comprising:
obtaining raw data corresponding to radiation rays within a volume (col. 20, lines 34-35);
determining, among the radiation rays, a radiation ray passing a plurality of voxels corresponding to a portion of the volume based on the raw data (col. 20, lines 36-38);
loading the plurality of voxels into a memory (col. 20, lines 41-43; while the claim states “at least a portion of the plurality of subsets”, it is an obvious variant to include all subsets as all subsets satisfies the condition of “at least a portion”); and
performing a calculation relating to the loaded voxels by a plurality of processing threads in a parallel hardware architecture to generate an image of the volume (col. 20, lines 44-47).
Similar reasoning applies to claim 40 with respect to claim 14.
Claims 27-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,182,908 in view of Scheins et al.
Regarding claim 27, ‘908 et al. discloses a method as described in claim 21 above.
‘908 does not disclose determining an available resource of each of at least one processor in the parallel hardware architecture; and allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction comprising:
determining an available resource of each of at least one processor in the parallel hardware architecture (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5); and
allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor (overall processing time is used to determine which processing node to utilize for data processing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘908 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 28, ‘908 discloses a method wherein the parallel hardware architecture includes at least one processor (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” At paragraph 0051, line 5).
‘908 does not disclose that the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction wherein the parallel hardware architecture includes at least one processor, the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5; the fastest processing node therefore is selected for processing the data based upon the processing time exceeding the threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘908 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 29, Scheins et al. discloses a method wherein the determining the at least one processor from the candidate processors based on the determination result comprises: in response to determining that the amount of computational resources does not exceed the threshold amount, determining one candidate processor from the candidate processors as the at least one processor (given that the time threshold is satisfied, the processing may remain on a particular processing node); or in response to determining that the amount of computational resources exceeds the threshold amount, determining at least two candidate processors from the candidate processors as the at least one processor.
The following is a mapping of the instant invention to ‘908:
Claims of Instant Application
Claims of ‘908
21
1
22
1
23
4 + 5
24
8
25
8
26
8
27
1 + Scheins et al.
28
1 + Scheins et al.
29
1 + Scheins et al.
30
2
31
4 + 5
32
6
33
7
34
9
35
3
36
10
37
10
38
11
39
12
40
14
Claims 21-26, 30-32 and 34-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-7, 9, 11-13, 15, 16, 18 and 20 of U.S. Patent No. 11,704,846. Although the claims at issue are not identical, they are not patentably distinct from each other because they anticipate or render obvious the claims of the instant application.
Regarding claim 21, ‘846 discloses a method comprising:
obtaining raw data corresponding to radiation rays within a volume (col. 20, lines 26-28);
determining, among the radiation rays, a first radiation ray passing a plurality of voxels corresponding to the volume based on the raw data (col. 20, lines 29-31);
loading the plurality of voxels into a memory (col. 20, lines 32-38; while the claim states “at least a portion of the plurality of subsets”, it is an obvious variant to include all subsets as all subsets satisfies the condition of “at least a portion”);
performing a calculation relating to the loaded subsets of voxels by a plurality of processing threads in a parallel hardware architecture to generate an image of the volume (col. 20, lines 39-46).
Similar reasoning applies to claim 40 with respect to claim 11.
Claims 27-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,704,846 in view of Scheins et al.
Regarding claim 27, ‘846 et al. discloses a method as described in claim 21 above.
‘846 does not disclose determining an available resource of each of at least one processor in the parallel hardware architecture; and allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction comprising:
determining an available resource of each of at least one processor in the parallel hardware architecture (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5); and
allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor (overall processing time is used to determine which processing node to utilize for data processing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘846 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 28, ‘846 discloses a method wherein the parallel hardware architecture includes at least one processor (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” At paragraph 0051, line 5).
‘846 does not disclose that the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction wherein the parallel hardware architecture includes at least one processor, the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5; the fastest processing node therefore is selected for processing the data based upon the processing time exceeding the threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘846 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 29, Scheins et al. discloses a method wherein the determining the at least one processor from the candidate processors based on the determination result comprises: in response to determining that the amount of computational resources does not exceed the threshold amount, determining one candidate processor from the candidate processors as the at least one processor (given that the time threshold is satisfied, the processing may remain on a particular processing node); or in response to determining that the amount of computational resources exceeds the threshold amount, determining at least two candidate processors from the candidate processors as the at least one processor.
The following is a mapping of the instant invention to ‘846:
Claims of Instant Application
Claims of ‘846
21
1 or 11 or 20
22
1 or 11 or 20
23
1 or 11 or 20 in view of Akazawa et al.
24
2 or 12
25
2 or 12
26
2 or 12
27
1 + Scheins et al.
28
1 + Scheins et al.
29
1 + Scheins et al.
30
1 or 11 or 20
31
1 or 11 or 20 in view of Akazawa et al.
32
7 or in view of Akazawa et al.
34
3 or 13
35
5
36
1 or 11 or 20
37
6 or 15
38
7 or 16
39
9 or 18
40
11
Claims 21-26, 30-32 and 34-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 5, 9, 10, 12, 13, 17 and 18 of U.S. Patent No. 11,049,292. Although the claims at issue are not identical, they are not patentably distinct from each other because they anticipate or render obvious the claims of the instant application.
Regarding claim 21, ‘292 discloses a method comprising:
obtaining raw data corresponding to radiation rays within a volume (col. 20, lines 26-27);
determining, among the radiation rays, a first radiation ray passing a plurality of voxels corresponding to the volume based on the raw data (col. 20, lines 28-30);
loading the plurality of voxels into a memory (col. 20, lines 31-36; while the claim states “at least a portion of the plurality of subsets”, it is an obvious variant to include all subsets as all subsets satisfies the condition of “at least a portion”);
performing a calculation relating to the loaded subsets of voxels by a plurality of processing threads in a parallel hardware architecture to generate an image of the volume (col. 20, lines 41-48).
Similar reasoning applies to claim 40 with respect to claim 10.
Claims 27-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,049,292 in view of Scheins et al.
Regarding claim 27, ‘292 et al. discloses a method as described in claim 21 above.
‘292 does not disclose determining an available resource of each of at least one processor in the parallel hardware architecture; and allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction comprising:
determining an available resource of each of at least one processor in the parallel hardware architecture (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5); and
allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor (overall processing time is used to determine which processing node to utilize for data processing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘292 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 28, ‘292 discloses a method wherein the parallel hardware architecture includes at least one processor (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” At paragraph 0051, line 5).
‘292 does not disclose that the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction wherein the parallel hardware architecture includes at least one processor, the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5; the fastest processing node therefore is selected for processing the data based upon the processing time exceeding the threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘292 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 29, Scheins et al. discloses a method wherein the determining the at least one processor from the candidate processors based on the determination result comprises: in response to determining that the amount of computational resources does not exceed the threshold amount, determining one candidate processor from the candidate processors as the at least one processor (given that the time threshold is satisfied, the processing may remain on a particular processing node); or in response to determining that the amount of computational resources exceeds the threshold amount, determining at least two candidate processors from the candidate processors as the at least one processor.
The following is a mapping of the instant invention to ‘292:
Claims of Instant Application
Claims of ‘292
21
1 or 10 or 18
22
1 or 10 or 18
23
1 or 10 or 18
24
2
25
2
26
2
27
1 in view of Scheins et al.
28
1 in view of Scheins et al.
29
1 in view of Scheins et al.
30
1 or 10 or 18 in view of Akazawa et al.
31
1 or 10 or 18
32
5 in view of Akazawa et al.
34
1 or 10 or 18 in view of Szirmay-Kalos et al.
35
1 or 10 or 18 in view of Akazawa et al.
36
1 or 10 or 18
37
4 or 12
38
5 or 13
39
9 or 17
40
1 or 10 or 18
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5-16 of U.S. Patent No. 10,176,604. Although the claims at issue are not identical, they are not patentably distinct from each other because they anticipate or render obvious the claims of the instant application.
Regarding claim 21, ‘604 discloses a method comprising:
obtaining raw data corresponding to radiation rays within a volume (col. 20, lines 23-24);
determining, among the radiation rays, a first radiation ray passing a plurality of voxels corresponding to the volume based on the raw data (col. 20, lines 25-27);
loading the plurality of voxels into a memory (col. 20, lines 28-31; while the claim states “at least a portion of the plurality of subsets”, it is an obvious variant to include all subsets as all subsets satisfies the condition of “at least a portion”);
performing a calculation relating to the loaded subsets of voxels by a plurality of processing threads in a parallel hardware architecture to generate an image of the volume (col. 20, lines 33-42).
Similar reasoning applies to claim 40 with respect to claim 9.
Claims 27-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,176,604 in view of Scheins et al.
Regarding claim 27, ‘604 et al. discloses a method as described in claim 21 above.
‘604 does not disclose determining an available resource of each of at least one processor in the parallel hardware architecture; and allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction comprising:
determining an available resource of each of at least one processor in the parallel hardware architecture (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5); and
allocating the plurality of processing threads to the at least one processor based on the available resource of each of the at least one processor (overall processing time is used to determine which processing node to utilize for data processing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘604 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 28, ‘604 discloses a method wherein the parallel hardware architecture includes at least one processor (“Especially, in this embodiment, the arithmetic processing unit 10 is formed of an SIMD type mechanism represented by a GPU, for example.” At paragraph 0051, line 5).
‘604 does not disclose that the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result.
Scheins et al. teaches a method in the same field of endeavor of medical image reconstruction wherein the parallel hardware architecture includes at least one processor, the at least one processor are determined from candidate processors by: determining an amount of computational resources needed for processing the loaded voxels; obtaining a determination result by determining whether the amount of computational resources exceeds a threshold amount; and determining the at least one processor from the candidate processors based on the determination result (“After each iteration a limited fraction of “sparse vectors” is moved from the slowest node to the fastest node if the time difference of finishing exceeds a certain threshold.” At page 883, right column, second paragraph, line 5; the fastest processing node therefore is selected for processing the data based upon the processing time exceeding the threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the load checking as taught by Scheins et al. in the system of ‘604 to optimize processing time and reduce idle time (see Scheins et al. at page 883, right column, second paragraph).
Regarding claim 29, Scheins et al. discloses a method wherein the determining the at least one processor from the candidate processors based on the determination result comprises: in response to determining that the amount of computational resources does not exceed the threshold amount, determining one candidate processor from the candidate processors as the at least one processor (given that the time threshold is satisfied, the processing may remain on a particular processing node); or in response to determining that the amount of computational resources exceeds the threshold amount, determining at least two candidate processors from the candidate processors as the at least one processor.
The following is a mapping of the instant invention to ‘604:
Claims of Instant Application
Claims of ‘604
21
1 or 9
22
1 or 9
23
6 or in view of Akazawa et al.
24
2 or 12
25
2 or 12
26
2 or 12
27
1 in view of Scheins et al.
28
1 in view of Scheins et al.
29
1 in view of Scheins et al.
30
5 or in view of Akazawa et al.
31
6 or in view of Akazawa et al.
32
1 or 9
33
1 or 9
34
3 or 13
35
8 or 16
36
7 or 15
37
10 or 11 or in view of Akazawa et al.
38
1 or 9 in view of Akazawa et al.
39
1 or 9 in view of Akazawa et al.
40
1 or 9
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ha et al. (NPL reference) is relevant as disclosing a GPU-based kernel reconstruction utilizing consideration of chip resources and efficiency.
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/KATRINA R FUJITA/ Primary Examiner, Art Unit 2672
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