DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 19/004,607 filed on 12/30/2024 which is a continuation of application 17/941,587 filed on 9/9/2022 which is a continuation of application 16/882,374 filed on 5/22/2020 which claims priority to provisional application 62/852,494 filed on 5/24/2019.
Claims 1-20 have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kadambi et al (US 2004/0148469), Bhoria et al. (US 2015/0006820), and Creta et al. (US 2003/0126369).
With respect to claim 1, Kadambi teaches of a system, comprising: a first sub-cache (fig. 1, 3; paragraph 22-23, 30; data cache 102); and
a second sub-cache comprising: a first cache line configured to store first data (fig. 1, 3; paragraph 22-23, 30; hot spot cache 104).
Kadambi fails to explicitly teach of a first cache line configured to store first data that corresponds to a write miss in the first sub-cache, a memory configured to store a first value indicating whether the first cache line is half full; and an eviction controller configured to: determine whether the first cache line is half full based on the first value; and based on a determination that the first cache line is half full, evict the first data stored in the first cache line.
However, Bhoria teaches of a first cache line configured to store first data that corresponds to a write miss in the first sub-cache (fig. 3; paragraph 3, 11, 18; where the write command results in a cache miss and the write data is stored into the write miss buffer).
The combination of Kadambi and Bhoria fails to explicitly teach of a memory configured to store a first value indicating whether the first cache line is half full; and an eviction controller configured to: determine whether the first cache line is half full based on the first value; and based on a determination that the first cache line is half full, evict the first data stored in the first cache line.
However, Creta teaches of a first cache line configured to store first data (paragraph 6; where the data is written to a cache line);
a memory configured to store a first value indicating whether the first cache line is half full (paragraph 6, 20; where a 32 byte aligned data is written in to a storage block in the cache line the validity bit for the block is set to “1”, when this is done for two 32 byte data writes, the cache line is half full as indicated by the two validity bits being set to “1”); and
an eviction controller configured to: determine whether the first cache line is half full based on the first value (paragraph 10-11, 17, 20; where the cache operates in a second mode implementing 64-byte cache lines over the 128-byte cache lines. The eviction controller determines if the cache contains 64 bytes of the 128 byte lines based on the valid bits); and
based on a determination that the first cache line is half full, evict the first data stored in the first cache line (paragraph 10-11, 17, 20; where the cache operates in a second mode implementing 64-byt cache lines over the 128-byte cache lines, so that eviction occurs as soon as 64 bytes of data are written into a 128-byte cache line via the valid bits).
Kadambi and Bhoria are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Kadambi and Bhoria before the time of the effective filing of the claimed invention to incorporate the write miss buffer of Bhoria into the hot spot cache of Kadambi. Their motivation would have been to more efficiently handle write misses (Bhoria, paragraph 11-12).
Kadambi, Bhoria, and Creta are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Kadambi, Bhoria, and Creta before the time of the effective filing of the claimed invention to incorporate the eviction policy of Creta into the hot spot cache of the combination of Kadambi and Bhoria. Their motivation would have been to more efficiently operate the cache memory (Creta, paragraph 6).
With respect to claim 8, Kadambi teaches of a method, comprising: receiving, by a caching system including a first sub-cache and a second sub- cache, a first request to write first data (fig. 1, 3; paragraph 22-23, 30; data cache 102 and hot spot cache 104. A memory operation is received to access the data cache);
determining, by the caching system, whether the first request corresponds to a miss in the first sub-cache (fig. 1, 3; paragraph 30; where it is determined if the memory operation produces a hit or a miss in each cache);
Kadambi fails to explicitly teach of (1) receiving a first request to write first data, (2) based on determining that the first request corresponds to a miss in the first sub-cache, storing the first data in a first cache line of the second sub-cache and (3) storing a first value in the second sub-cache to indicate whether the first cache line is half full. (4) receiving a second request to evict a cache line of the second sub-cache; and based on receiving the second request, determining whether the first cache line of the second sub-cache is half full based on the first value; and based on determining that the first cache line is half full, evicting the first data stored in the first cache line.
However, Bhoria teaches of receiving a first request to write first data (paragraph 3, 11; where a write command is received that results in a cache miss),
based on determining that the first request corresponds to a miss in the first sub-cache, storing the first data in a first cache line of the second sub-cache (fig. 3; paragraph 3, 11, 18; where the write command results in a cache miss and the write data is stored into the write miss buffer).
The combination of Kadambi and Bhoria fails to explicitly teach of storing a first value in the second sub-cache to indicate whether the first cache line is half full; receiving a second request to evict a cache line of the second sub-cache; and based on receiving the second request, determining whether the first cache line of the second sub-cache is half full based on the first value; and based on determining that the first cache line is half full, evicting the first data stored in the first cache line.
However, Creta teaches of storing the first data in a first cache line of the second sub-cache (paragraph 6; where the data is written to a cache line); and
storing a first value in the second sub-cache to indicate whether the first cache line is half full (paragraph 6, 20; where a 32 byte aligned data is written in to a storage block in the cache line the validity bit for the block is set to “1”, when this is done for two 32 byte data writes, the cache line is half full as indicated by the two validity bits being set to “1”);
receiving a second request to evict a cache line of the second sub-cache (paragraphs 10-11, 17; where the eviction engine monitors the cache lines to determine if an eviction condition is met. As this occurs within a computer system, this suggests to one of ordinary skill in the art that there are instructions/requests that the eviction engine follows to perform its operations); and
based on receiving the second request, determining whether the first cache line of the second sub-cache is half full based on the first value (paragraph 11, 20; where the cache operates in a second mode implementing 64-byt cache lines over the 128-byte cache lines, so that eviction occurs as soon as 64 bytes of data are written into a 128-byte cache line via the valid bits); and
based on determining that the first cache line is half full, evicting the first data stored in the first cache line (paragraph 11, 20; where the cache operates in a second mode implementing 64-byt cache lines over the 128-byte cache lines, so that eviction occurs as soon as 64 bytes of data are written into a 128-byte cache line via the valid bits).
Kadambi and Bhoria are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Kadambi and Bhoria before the time of the effective filing of the claimed invention to incorporate the write miss buffer of Bhoria into the hot spot cache of Kadambi. Their motivation would have been to more efficiently handle write misses (Bhoria, paragraph 11-12).
Kadambi, Bhoria, and Creta are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Kadambi, Bhoria, and Creta before the time of the effective filing of the claimed invention to incorporate the eviction policy of Creta into the hot spot cache of the combination of Kadambi and Bhoria. Their motivation would have been to more efficiently operate the cache memory (Creta, paragraph 6).
With respect to claim 15, the combination of Kadambi, Bhoria, and Creta teaches of the limitations cited and described above with respect to claims 1 and 8 for the same reasoning as recited with respect to claims 1 and 8.
The combination of Kadambi, Bhoria, and Creta also teaches of a device, comprising: a processor configured to generate a first request to write first data (Kadambi, paragraph 30, Bhoria, paragraph 3, 11; where the CPU issues a write command that results in a write miss).
The reasoning for obviousness is the same as indicated above with respect to claims 1 and 8.
With respect to claims 2, 9, and 16, the combination of Kadambi, Bhoria, and Creta teaches of the second sub-cache further comprises a second cache line configured to store second data that corresponds to a write miss in the first sub-cache (Bhoria, fig. 3; paragraph 3, 11, 18; where the write command results in a cache miss and the write data is stored into the write miss buffer);
the memory is further configured to store a second value indicating whether the second cache line is full (Creta, paragraph 6, 17; where a 32 byte aligned data is written in to a storage block in the cache line the validity bit for the block is set to “1”, when this is done for four 32 byte data writes, the cache line is full as indicated by the four validity bits being set to “1”); and
the eviction controller is further configured to: based on receiving the second request, determine whether the second cache line is full (Creta, paragraph 10-11, 17; where the eviction engine monitors the cache to see if any cache lines have valid bits all set, i.e. full, so that eviction occurs as soon as a cache line is fully written); and
based on a determination that the second cache line is full, evict the second data stored in the second cache line (Creta, paragraph 10-11, 17; where the eviction engine monitors the cache to see if any cache lines have valid bits all set, i.e. full, so that eviction occurs as soon as a cache line is fully written).
The reasoning for obviousness is the same as indicated above with respect to claims 1 and 8.
With respect to claims 3 and 10, Creta teaches of wherein the first value is a one-bit value (paragraph 6; where each validity bit is a bit that can be set to “1” or “0”).
The reasoning for obviousness is the same as indicated above with respect to claims 1 and 8.
With respect to claims 4 and 11, Creta teaches of wherein the second value is a one-bit value (paragraph 6; where each validity bit is a bit that can be set to “1” or “0”).
The reasoning for obviousness is the same as indicated above with respect to claims 1 and 8.
With respect to claim 17, Creta teaches of the limitations cited above with respect to claims 3-4 and 10-11 for the same reasoning as indicated with respect to claims 3-4 and 10-11.
With respect to claims 5, 12, and 18 Kadambi teaches of wherein the second sub-cache is configured to store data evicted from the first sub-cache (paragraph 10; where the hot spot cache stores cache lines evicted from hot spots in the cache memory).
With respect to claims 6, 13, and 19 Kadambi teaches of wherein the first sub-cache is a main cache, and the second sub-cache is a victim cache corresponding to the main cache (paragraph 10, 22-23; where the data cache is a L1 cache and the hot spot cache is in parallel with the L1 cache and thus is also an L1 cache. Since the hot spot cache stores entries that have been evicted from hot spots of the data cache, it is a victim cache).
With respect to claims 7, 14, and 20 Kadambi teaches of wherein the first sub-cache is a level-one (L1) main cache, and the second sub-cache is a level-one (L1) victim cache (paragraph 10, 22-23; where the data cache is a L1 cache and the hot spot cache is in parallel with the L1 cache and thus is also an L1 cache. Since the hot spot cache stores entries that have been evicted from hot spots of the data cache, it is a victim cache).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-4, 8-11, and 15-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5, 8-9, 12, 15-16, and 19 of U.S. Patent No. 12,210,463. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the rejected claims are included in and anticipated by the cited claims of U.S. Patent No. 12,210,463.
Claims 1-4, 8-11, and 15-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4-5, 8-9, 11-12, 15-16, and 18-19 of U.S. Patent No. 11,442,868. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the rejected claims are included in and anticipated by the cited claims of U.S. Patent No. 11,442,868.
Claims 5-7, 12-14, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5, 8-9, 12, 15-16, and 19 of U.S. Patent No. 12,210,463 in view of Kadambi et al. (US 2004/0148469).
Claims 5-7, 12-14, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5, 8-9, 12, 15-16, and 19 of U.S. Patent No. 11,442,868 in view of Kadambi et al. (US 2004/0148469).
US 12,210,463 and US 11,442,868 each fail to explicitly claim (1) wherein the second sub-cache is configured to store data evicted from the first sub-cache, and (2) wherein the first sub-cache is a level-one (L1) main cache, and the second sub-cache is a level-one (L1) victim cache.
However, Kadambi teaches of wherein the second sub-cache is configured to store data evicted from the first sub-cache (paragraph 10; where the hot spot cache stores cache lines evicted from hot spots in the cache memory);
wherein the first sub-cache is a level-one (L1) main cache, and the second sub-cache is a level-one (L1) victim cache (paragraph 10, 22-23; where the data cache is a L1 cache and the hot spot cache is in parallel with the L1 cache and thus is also an L1 cache. Since the hot spot cache stores entries that have been evicted from hot spots of the data cache, it is a victim cache).
US 12,210,463’s claims and Kadambi are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of US 12,210,463’s claims and Kadambi before the time of the effective filing of the claimed invention to incorporate the hot spot cache of Kadambi storing the victim from the L1 data cache in US 12,210,463’s claims as taught in Kadambi. Their motivation would have been to more efficiently utilize the memory as the evicted line can be retrieved without acing lower layers of memory (Kadambi, paragraph 10).
US 11,442,868’s claims and Kadambi are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of US 11,442,868’s claims and Kadambi before the time of the effective filing of the claimed invention to incorporate the hot spot cache of Kadambi storing the victim from the L1 data cache in US 11,442,868’s claims as taught in Kadambi. Their motivation would have been to more efficiently utilize the memory as the evicted line can be retrieved without acing lower layers of memory (Kadambi, paragraph 10).
See the chart below for a mapping of the rejected claims.
Application 19/004,607
US 12,210,463
US 11,442,868
Claim 1: A system, comprising: a first sub-cache; and
Claim 1: A caching system comprising: a first sub-cache; and
Claim 1: A caching system comprising: a first sub-cache; and
a second sub-cache comprising: a first cache line configured to store first data that corresponds to a write miss in the first sub-cache;
a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines… the first cache line of the set of cache lines storing write-miss data…
a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: a set of cache lines; line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data; and
a byte enable memory including a first bit, wherein a value of the first bit indicates whether a first cache line of the set of cache lines is full; and an eviction controller configured to: determine that the first cache line of the set of cache lines storing write-miss data is full based on the value of the first bit; and evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.
an eviction controller configured to: determine that a first cache line of the second sub-cache storing write-miss data is full; and evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.
a memory configured to store a first value indicating whether the first cache line is half full; and
Claim 5: wherein the byte enable memory includes a second bit, wherein a value of the second bit indicates whether the second cache line is half full, and wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.
Claim 5: wherein the byte enable memory includes a second bit, and wherein a value of the second bit indicates whether the second cache line is half full, and wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.
an eviction controller configured to: determine whether the first cache line is half full based on the first value; and
Claim 2: wherein the eviction controller is further configured to: determine that a second cache line of the set of cache lines storing write-miss data is half full; and
Claim 2: wherein the eviction controller is further configured to: determine that a second cache line of the second sub-cache storing write-miss data is half full; and
based on a determination that the first cache line is half full, evict the first data stored in the first cache line.
Claim 2: evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full.
Claim 2: evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full
Claim 2
Claim 1
Claim 1
Claim 3
Claim 5
Claim 5
Claim 4
Claim 1
Claim 4
Claim 5
Claim 6
Claim 7
Claim 8: A method, comprising: receiving, by a caching system including a first sub-cache and a second sub- cache, a first request to write first data;
Claim 8: A method for caching data, comprising: receiving, by a caching system, a write memory request for a memory address, wherein the caching system comprises a first sub-cache, a second sub-cache in parallel with the first sub-cache, and
Claim 8: A method for caching data, comprising: receiving, by a caching system, a write memory request for a memory address; determining, by a first sub-cache of the caching system, … determining, by a second sub-cache of the caching system, …
determining, by the caching system, whether the first request corresponds to a miss in the first sub-cache;
determining, by the caching system, that the memory address is not cached in the caching system;
determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the caching system, that the memory address is not cached in the second sub-cache;
based on determining that the first request corresponds to a miss in the first sub- cache, storing the first data in a first cache line of the second sub-cache; and
responsive to determining that the memory address is not cached in the caching system, storing data associated with the write memory request in the first cache line of the second sub-cache;
responsive to determining that the memory address is not cached in the second sub-cache, storing data associated with the write memory request in a first cache line of the second sub-cache;
a byte enable memory including a first bit, a value of which indicates whether a first cache line of the second sub-cache is full;
responsive to determining that the memory address is not cached in the second sub-cache, storing, in a line type bit of the second sub-cache, an indication that the stored data corresponds to a write-miss;
responsive to determining that the memory address is not cached in the caching system, storing an indication that the stored data corresponds to a write-miss; determining that the first cache line is full based on the value of the first bit of the byte enable memory; and evicting write-miss data stored in the first cache line of the second sub-cache in response to determining that the first cache line is full.
determining that the first cache line is full; and evicting write-miss data stored in the first cache line in response to determining that the first cache line is full.
storing a first value in the second sub-cache to indicate whether the first cache line is half full;
Claim 12: wherein the byte enable memory of the caching system includes a second bit, wherein a value of the second bit indicates whether the second cache line is half full, and wherein determining that the second cache line is half full by at least reading the value of the second bit.
Claim 12: storing a second bit in the byte enable memory of the second sub-cache, wherein a value of the second bit indicates whether the second cache line is half full, and wherein determining that the second cache line is half full by at least reading the value of the second bit.
receiving a second request to evict a cache line of the second sub-cache; and based on receiving the second request, determining whether the first cache line of the second sub-cache is half full based on the first value; and
Claim 9: determining that a second cache line of the caching system storing write-miss data is half full; and
Claim 9: determining that a second cache line of the second sub-cache storing write-miss data is half full; and
based on determining that the first cache line is half full, evicting the first data stored in the first cache line.
Claim 9: evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.
Claim 9: evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.
Claim 9
Claim 8
Claim 8
Claim 10
Claim 12
Claim 12
Claim 11
Claim 8
Claim 11
Claim 12
Claim 13
Claim 14
Claim 15: A device, comprising: a processor configured to generate a first request to write first data;
Claim 15: A device comprising: a processor configured to generate memory requests;
Claim 15: A device comprising: a processor;
a first sub-cache; and a second sub-cache comprising: a first cache line configured to store the first data, wherein the first data corresponds to a write miss in the first sub-cache;
a first sub-cache configured to receive the memory requests; and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines… the first cache line of the set of cache lines storing write-miss data…
a first sub-cache; and a second sub-cache in parallel with the first sub-cache; wherein the second sub-cache includes: a set of cache lines; line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and
a byte enable memory including a first bit, a value of which indicates whether a first cache line of the set of cache lines is full; and an eviction controller configured to: determine that the first cache line of the set of cache lines storing write-miss data is full based on the value of the first bit; and evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.
an eviction controller configured to: determine that a first cache line of the second sub-cache storing write-miss data is full; and
evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.
a memory configured to store a first value indicating whether the first cache line is half full; and
Claim 19: wherein the byte enable memory includes a second bit, wherein a value of the second bit indicates whether the second cache line is half full, and wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.
Claim 19: wherein the byte enable memory includes a second bit, wherein a value of the second bit indicates whether the second cache line is half full, and wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.
an eviction controller configured to: based on receiving a second request to evict a cache line of the second sub-cache, determine whether the first cache line is half full based on the first value; and
Claim 16: wherein the eviction controller is further configured to: determine that a second cache line of the set of cache lines storing write-miss data is half full; and
Claim 16: wherein the eviction controller is further configured to: determine that a second cache line of the second sub-cache storing write-miss data is half full; and
based on a determination that the first cache line is half full, evict the first data stored in the first cache line.
Claim 16: evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full.
Claim 16: evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full.
Claim 16
Claim 15
Claim 15
Claim 17
Claim 15, 19
Claim 18, 19
Claim 18
Claim 19
Claim 20
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Busaba et al. (US 2015/0089155) discloses that cache lines are managed in either full line granularity or sub-cache line granularity including when casting out the cache line.
Morrow (US 2005/0204099) discloses cache lines that are divided in half, where each half has its own dirty bit, valid bit, and write back bit to indicate the status of each half of the cache line.
Van Huben et al. (US 2002/0083299) discloses determining that only half of a cache line has been updated and casting out only the updated half of the cache line to main memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138