FINAL OFFICE ACTION
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4, 10, 11, 13, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2016/0365876 to Greenspan et al. (hereinafter Greenspan) in view of U.S. Patent Pub. No. 2024/0380415 to Dakshinamoorthy (hereinafter Dakshinamoorthy).
Greenspan discloses:
1. A data processing system comprising:
a memory accessing agent (para. [0029] and Fig. 1A, data decoding circuit 130); and
a memory controller coupled to the memory accessing agent and comprising an error correcting code (ECC) check circuit for detecting errors in a data element and extracting metadata from an error correcting code, the detecting and extracting comprising forming a plurality of error statuses based on the data element and the error correcting code for different combinations of metadata, and picking a final status and final metadata based on the plurality of error statuses (paras. [0030], [0036]-[0037], and [0041]-[0046]).
Greenspan does not disclose expressly forming a plurality of error statuses based on a plurality of data sub-elements of the data element.
Dakshinamoorthy teaches forming a plurality of error statuses based on a plurality of data sub-elements of the data element (paras. [0016], [0017], [0020]).
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Greenspan by forming error statuses based on a plurality of data sub-elements, as taught by Dakshinamoorthy. A person of ordinary skill in the art would have been motivated to do so in order to “achieve minimal latency as well as lower power,” as discussed by Dakshinamoorthy (para. [0014]).
Modified Greenspan discloses:
2. The data processing system of claim 1, wherein the memory controller further comprises:
an ECC generation circuit operable to bias a virtual symbol based on at least one metadata bit, and to generate a corresponding error correcting code in response to the data element and a biased virtual symbol (Greenspan - paras. [0023], [0039]).
4. The data processing system of claim 1, wherein the ECC check circuit comprises:
an optimized-logic decoder circuit (Greenspan - para. [0030] and Fig. 1A, data decoding circuit 130).
9. The data processing system of claim 1, further comprising:
a memory coupled to the memory controller, wherein the memory stores the data element and the error correcting code (Greenspan - Fig. 1, memory 115).
10. A memory controller comprising:
an error correcting code (ECC) generation circuit operable to bias a virtual symbol based on at least one metadata bit associated with a data element having a plurality of data sub-elements (Dakshinamoorthy – paras. [0016], [0017], [0020]), and to generate an error correcting code in response to the data sub-elements and a biased virtual symbol (Greenspan - paras. [0026], [0032]-[0033], [0039]-[0040]); and
an ECC check circuit operable to detect errors in the data element and extract metadata from the error correcting code read from memory by forming a plurality of error statuses based on the data element and the error correcting code for different combinations of metadata, and picking a final status and final metadata based on the plurality of error statuses (Greenspan - paras. [0036]-[0037], and [0041]-[0046]).
11. The memory controller of claim 10, further comprising:
a command queue for storing memory access requests, the memory access requests including read requests and write requests (Greenspan - para. [0093]); and
an arbiter for picking memory commands from among the memory access requests for dispatch to the memory (Greenspan - para. [0095]),
wherein in response to picking a write memory access request, the arbiter activates the ECC generation circuit to generate the error correcting code in response to the data element and the biased virtual symbol (Greenspan - paras. [0032]-[0033]), and
wherein in response to picking a read memory access request, the arbiter activates the ECC check circuit to generate the error correcting code and to extract the metadata bit in response to the data element and the biased virtual symbol (Greenspan - paras. [0036]-[0037]).
13. The memory controller of claim 11, wherein the ECC check circuit comprises:
an optimized-logic decoder circuit (Greenspan - para. [0030] and Fig. 1A, data decoding circuit 130).
18. A method comprising:
generating an error correcting code for a plurality of sub-elements of a data element (Dakshinamoorthy – paras. [0016], [0017], [0020]), comprising:
biasing a virtual symbol based on at least one metadata bit associated with the data element (Greenspan - paras. [0026], [0032]), and
generating the error correcting code in response to the data element and a biased virtual symbol (Greenspan - paras. [0026], [0032]); and
extracting metadata from the error correcting code, comprising:
forming a plurality of error statuses based on the plurality of sub-elements and the error correcting code for different combinations of metadata (Greenspan - paras. [0036]-[0037], and [0041]-[0046]); and
picking a final status and final metadata based on the plurality of error statuses (Greenspan - paras. [0036]-[0037], and [0041]-[0046]).
19. The method of claim 18, further comprising:
writing the data element and the error correcting code to a memory in response to a write command (Greenspan - para. [0029]); and
reading the data element and the error correcting code from the memory in response to a read command (Greenspan - para. [0029]).
Claims 3, 5-7, 12, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Greenspan in view of Dakshinamoorthy, and further in view of U.S. Patent Pub. No. 2022/0091936 to La Fetra.
Greenspan does not disclose expressly:
3. The data processing system of claim 1, wherein ECC check circuit comprises:
a plurality of decoder circuits for each of the different combinations of metadata, each having a first input for receiving the data element, a second input for receiving a corresponding one of a plurality of metadata states, a third input for receiving a corresponding error correcting code, and an output for providing an error syndrome and a corresponding error locator.
La Fetra teaches wherein ECC check circuit comprises:
a plurality of decoder circuits for each of the different combinations of metadata, each having a first input for receiving the data element, a second input for receiving a corresponding one of a plurality of metadata states, a third input for receiving a corresponding error correcting code, and an output for providing an error syndrome and a corresponding error locator (paras. [0037]-[0039] and Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Greenspan by using a plurality of decoder circuits, as taught by La Fetra. A person of ordinary skill in the art would have been motivated to do so in order to process code words in parallel, as described by La Fetra (para. [0013]), which leads to increased performance.
Modified Greenspan discloses:
5. The data processing system of claim 4, wherein the optimized-logic decoder circuit comprises:
a base syndrome generation circuit for providing a base syndrome in response to a corresponding error correcting code and the data element (Greenspan – paras. [0043]-[0044] and La Fetra – paras. [0038]-[0039]);
a plurality of syndrome derivation circuits for inverting predetermined bits of the base syndrome corresponding to each of the different combinations of metadata while keeping other bits un-inverted, and forming metadata-specific syndromes in response thereto (Greenspan – paras. [0043]-[0044] and La Fetra – paras. [0038]-[0039]); and
a plurality of error locator circuits for providing a bit number of error bits for corresponding ones of the different combinations of metadata in response to corresponding metadata-specific syndromes and the data element (Greenspan – paras. [0043]-[0044] and La Fetra – paras. [0038]-[0039]).
6. The data processing system of claim 3, wherein the ECC check circuit further comprises:
an error status analysis circuit, for reporting an error status of each of the different combinations of metadata as one of: no error, a correctable error, and an uncorrectable error (Greenspan – para. [0044] and La Fetra – para. [0039]); and
a decoder pick circuit, for determining a final error status and picking a decoded metadata value in response to the error status of each of the different combinations of metadata (Greenspan – para. [0043] and La Fetra – para. [0039]).
7. The data processing system of claim 6, wherein the ECC check circuit further comprises:
a data correction circuit for generating corrected data based on the data element and an error locator corresponding to the decoded metadata value when the final error status indicates a correctable error (Greenspan – paras. [0037], [0044] and La Fetra – para. [0041]).
12. The memory controller of claim 11, wherein the ECC check circuit comprises:
a plurality of decoder circuits for each of the different combinations of metadata, each having a first input for receiving a corresponding data sub-element, a second input for receiving a corresponding one of a plurality of metadata states, a third input for receiving the error correcting code, and an output for providing an error syndrome and a corresponding error locator (La Fetra - paras. [0037]-[0039] and Fig. 4).
14. The memory controller of claim 13, wherein the optimized-logic decoder circuit comprises:
a base syndrome generation circuit for providing a base syndrome in response to the error correcting code and the data element (Greenspan – paras. [0043]-[0044] and La Fetra – paras. [0038]-[0039]);
a plurality of syndrome derivation circuits for inverting predetermined bits of the base syndrome corresponding to each of the different combinations of metadata while keeping other bits un-inverted, and forming metadata-specific syndromes in response thereto (Greenspan – paras. [0043]-[0044] and La Fetra – paras. [0038]-[0039]); and
a plurality of error locator circuits for providing a bit number of error bits for corresponding ones of the different combinations of metadata in response to corresponding metadata-specific syndromes and the data element (Greenspan – paras. [0043]-[0044] and La Fetra – paras. [0038]-[0039]).
15. The memory controller of claim 12, wherein the ECC check circuit further comprises:
an error status analysis circuit, for reporting an error status of each of the different combinations of metadata as one of: no error, a correctable error, and an uncorrectable error (Greenspan – para. [0044] and La Fetra – para. [0039]); and
a decoder pick circuit, for determining a final error status and picking a decoded metadata value in response to the error status of each of the different combinations of metadata (Greenspan – para. [0043] and La Fetra – para. [0039]).
16. The memory controller of claim 15, wherein the ECC check circuit further comprises:
a data correction circuit for generating corrected data based on the data element and an error locator corresponding to the decoded metadata value when the final error status indicates a correctable error (Greenspan – paras. [0037], [0044] and La Fetra – para. [0041]).
20. The method of claim 18, further comprising:
decoding each of the different combinations of metadata in a plurality of decoder circuits, each having a first input for receiving the data element, a second input for receiving a corresponding one of a plurality of metadata states, a third input for receiving the error correcting code, and an output for providing an error syndrome and a corresponding error locator (La Fetra - paras. [0037]-[0039] and Fig. 4).
Allowable Subject Matter
Claims 8 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PHILIP GUYTON/Primary Examiner, Art Unit 2113
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