CTNF 19/004,697 CTNF 80213 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority The present application is a continuation of Application Serial No. 18/480,815, filed 04 October 2023 and issued 01 May 2025 as US Patent 12223100, which is a continuation of Application Serial No. 14/305,713, filed 16 June 2014 and issued 07 November 2023 as US Patent 11809610. Information Disclosure Statement The information disclosure statement filed 30 December 2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. No copy of the search report document (non-patent literature citation no. 1) has been provided. The IDS has been placed in the application file, and the information referred to therein has been considered, with the exception of the lined-through documents. Claim Objections 07-29-01 AIA Claim s 1, 9, and 17 are objected to because of the following informalities: In Claim 1, line 8, “the plurality cores” should read “the plurality of cores”. In Claim 1, line 20, it appears that “determines” should read “determine” for parallel structure with the “scheduler configured to”. In Claim 9, line 4, it appears that “is to be performed” should read “are to be performed” for agreement with the subject “the one or more cryptographic operations”. In Claim 17, line 3, it appears that “is to be performed” should read “are to be performed” for agreement with the subject “the one or more cryptographic operations” . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-01 The following is a quotation of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. 07-30-01 The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-02 AIA Claim s 9 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. A determination of a failure to comply with the enablement requirement is made considering the undue experimentation factors set forth in MPEP § 2164.01(a). The factors that appear to weigh most heavily in the present application are the breadth of the claims (MPEP § 2163.08), the amount of direction provided by the inventor (MPEP § 2163.03), and the existence of working examples (MPEP § 2163.02). Claims 9 and 17 each recite determining “whether the one or more cryptographic operations determined for the read command [are] to be performed before the read command is sent to the memory”. The specification only describes starting an early crypto operation before the command is sent to the memory and before the read data is returned to the memory based on “this information” (see page 10, lines 7-10), where the antecedent of “this information” is generally unclear but may be intended to refer to the type of operation determined previously (see page 10, lines 4-6). However, in general, it is not clear how a decryption operation could be started without having the data that is to be decrypted (i.e. the data that is an input to the decryption operation). Applicant provides no examples of an algorithm that may allow such early crypto operations and provides no other details of how the operation could be started before receiving the read data (i.e. the data to be decrypted). This lack of description and working examples suggests that there is little direction provided by the inventor. Combined with the broad scope of the claims, this suggests that the enablement of the disclosure is not commensurate with the scope of the claims (MPEP § 2163.08) and that undue experimentation would be required to make or use the invention based on the disclosure (MPEP § 2163.06) . 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “determine, for a write command, that a write address for the write command specifies an encrypted region of the encrypted regions of the memory, and in response thereto…” in lines 10-12 and “determine, for a read command, that a read address for the read command specifies an encrypted region of the encrypted regions of the memory, and in response thereto…” in lines 17-19. In the phrase “in response thereto”, it is not clear what these are in response to. In particular, it is not clear if this is in response to the determinations that the write or read address specifies an encrypted region, or if this is in response to the write or read commands themselves. The claim further recites “an encrypted region” in line 18. It is not clear whether this is intended to refer to the same encrypted region of the plural encrypted regions as in line 11 or to a distinct region. If these are potentially distinct regions, then it is recommended to refer to them as first and second encrypted regions or similar. The claim additionally recites “one or more of the cryptographic operations” in line 20. It is not clear if these operations are the same as those determined in line 13 or if they are distinct operations. If these are potentially distinct operations, then it is recommended to refer to them as first and second operations or similar. The above ambiguities render the claim indefinite. Claim 5 recites “determine the one or more cryptographic operations to be performed in response to the write command based on an authentication mode” in lines 3-5 and “determine the one or more cryptographic operations to be performed in response to the read command based on an authentication mode” in lines 7-9. It is not clear if these are intended to be separate determinations from the determinations of the operations as in Claim 1, lines 13 and 20 respectively, or if the determinations in Claim 5 are intended to be further limitations on the determinations in Claim 1 (i.e. the determinations are based on both the encryption mode and authentication mode for the respective specified encrypted regions). Claim 12 recites “an encrypted region” in lines 16-17. It is not clear whether this is intended to refer to the same encrypted region of the plural encrypted regions as in lines 8-9 or to a distinct region. If these are potentially distinct regions, then it is recommended to refer to them as first and second encrypted regions or similar. The claim additionally recites “one or more of the cryptographic operations” in line 18. It is not clear if these operations are the same as those determined in line 10 or if they are distinct operations. If these are potentially distinct operations, then it is recommended to refer to them as first and second operations or similar. The above ambiguities render the claim indefinite. Claims not explicitly referred to above are rejected due to their dependence on a rejected base claim. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-18 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Hussain et al, US Patent 7337314 . In reference to Claim 1, Hussain discloses a system comprising: a plurality of cores for performing cryptographic operations (Figure 9, cores 916; see column 14, lines 51-60 and column 18, lines 30-64; see also column 5, lines 13-29, for example); a memory interface configured to write encrypted data received from one or more of the plurality of cores to a memory having encrypted regions and unencrypted regions, and further configured to provide encrypted data received from the memory to one or more of the plurality cores (Figure 9, memory interface 940 and memory 920; see column 15, lines 31-40; see also column 22, lines 26-30, describing memory blocks defining the different types of queues as described at column 19, line 43-column 22, line 25, where these correspond to the encrypted and unencrypted regions); and a scheduler (Figure 10, schedulers 1002, 1008, 1016, for example, see also column 17, line 37-column 18, line 29) configured to: determine, for a write command, that a write address for the write command specifies an encrypted region of the encrypted regions of the memory, and in response thereto, determine one or more of the cryptographic operations to be performed in response to the write command based on an encryption mode for the encrypted region specified by the write command (see column 18, line 30-column 19, line 6, where cryptographic operations are determined based on the encryption algorithm corresponding to the claimed encryption mode, where the input queue allocation module 561 allocates for input to the memory, i.e. write commands; see also column 4, lines 16-22, and column 5, lines 13-29); and determine, for a read command, that a read address for the read command specifies an encrypted region of the encrypted regions of the memory, and in response thereto, determines one or more of the cryptographic operations to be performed in response to the read command based on an encryption mode for the encrypted region specified by the read command (see column 18, line 30-column 19, line 6, where cryptographic operations are determined based on the encryption algorithm corresponding to the claimed encryption mode, where the output queue allocation module 563 allocates for output from the memory, i.e. read commands; see also column 4, lines 16-22, and column 5, lines 13-29). In reference to Claim 2, Hussain further discloses that a first subset of one or more cores of the plurality of cores is configured to perform the one or more cryptographic operations determined in response to the write command; and a second subset of one or more cores of the plurality of cores is configured to perform the one or more cryptographic operations determined in response to the read command (see column 18, lines 42-56, for example; see also column 4, lines 16-22, and column 5, lines 13-29). In reference to Claim 3, Hussain further discloses that at least one of the plurality of cores is an Advanced Encryption Standard (AES) core (see column 14, lines 51-60, AES). In reference to Claim 4, Hussain further discloses at least one logic circuit respectively associated with the at least one AES core (see column 16, lines 12-26, layers of logic). In reference to Claim 5, Hussain further discloses that the scheduler is further configured to: determine the one or more cryptographic operations to be performed in response to the write command based on an authentication mode for the encrypted region specified by the write command; and determine the one or more cryptographic operations to be performed in response to the read command based on an authentication mode for the encrypted region specified by the read command (see column 4, lines 16-22, and column 5, lines 13-29). In reference to Claim 6, Hussain further that, for each of the write command and the read command, the scheduler is further configured to determine a data path (see Figure 10, queues and scheduling; see also column 19, line 43-column 22, line 25). In reference to Claim 7, Hussain further discloses that a first subset of the plurality of cores is associated with write commands and a second subset of the plurality of cores is associated with read commands (column 18, line 30-column 19, line 6, input and output queue allocation). In reference to Claim 8, Hussain further discloses that the scheduler is further configured to dynamically adjust a number of cores in the first subset and a number of cores in the second subset based on write command traffic and read command traffic (column 19, lines 40-50 et seq describing dynamic reallocation of processing resources). In reference to Claim 9, Hussain further discloses that, for the read command, the scheduler is further configured to determine whether the one or more cryptographic operations determined for the read command is to be performed before the read command is sent to the memory (column 18, line 30-column 19, line 6, determining timing of read command). In reference to Claim 10, Hussain further discloses a command buffer configured to associate the read command with data read from the memory in response to the read command (column 12, lines 51-56; column 15, lines 31-40; column 16, line 54-column 17, line 5). In reference to Claim 11, Hussain further discloses that the memory interface includes a data bus with encryption functionality (see Figure 9; column 14, lines 51-60). Claims 12-17 are directed to methods corresponding substantially to the functions of the systems of Claims 1, 2, 6, and 8-10, and are rejected by a similar rationale, mutatis mutandis . In reference to Claim 18, Hussain further discloses receiving configuration data (column 18, line 30-column 19, line 6) . 07-15 AIA Claim s 1-18 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Mundra et al, US Patent Application Publication 2012/0008768 . In reference to Claim 1, Mundra discloses a system comprising: a plurality of cores for performing cryptographic operations (Figure 1, encryption modules; see also Figure 11); a memory interface configured to write encrypted data received from one or more of the plurality of cores to a memory having encrypted regions and unencrypted regions, and further configured to provide encrypted data received from the memory to one or more of the plurality cores (Figure 20, EMIF SDRC 3552.1, and SDRAM 3550, for example); and a scheduler (Figure 1, scheduler 260; see also Figure 11, crypto core scheduler) configured to: determine, for a write command, that a write address for the write command specifies an encrypted region of the encrypted regions of the memory, and in response thereto, determine one or more of the cryptographic operations to be performed in response to the write command based on an encryption mode for the encrypted region specified by the write command (paragraphs 0154-0155, operations performed for various encryption operation modes); and determine, for a read command, that a read address for the read command specifies an encrypted region of the encrypted regions of the memory, and in response thereto, determines one or more of the cryptographic operations to be performed in response to the read command based on an encryption mode for the encrypted region specified by the read command (paragraphs 0154-0155, operations performed for various encryption operation modes). In reference to Claim 2, Mundra further discloses that a first subset of one or more cores of the plurality of cores is configured to perform the one or more cryptographic operations determined in response to the write command; and a second subset of one or more cores of the plurality of cores is configured to perform the one or more cryptographic operations determined in response to the read command (see Figure 4, separate inbound and outbound processing). In reference to Claim 3, Mundra further discloses that at least one of the plurality of cores is an Advanced Encryption Standard (AES) core (see Figure 11, crypto core 1 AES). In reference to Claim 4, Mundra further discloses at least one logic circuit respectively associated with the at least one AES core (Figure 11, logic 680). In reference to Claim 5, Mundra further discloses that the scheduler is further configured to: determine the one or more cryptographic operations to be performed in response to the write command based on an authentication mode for the encrypted region specified by the write command; and determine the one or more cryptographic operations to be performed in response to the read command based on an authentication mode for the encrypted region specified by the read command (paragraphs 0154-0155). In reference to Claim 6, Mundra further that, for each of the write command and the read command, the scheduler is further configured to determine a data path (see paragraph 0244, data paths). In reference to Claim 7, Mundra further discloses that a first subset of the plurality of cores is associated with write commands and a second subset of the plurality of cores is associated with read commands (Figure 4, separate inbound and outbound processing). In reference to Claim 8, Mundra further discloses that the scheduler is further configured to dynamically adjust a number of cores in the first subset and a number of cores in the second subset based on write command traffic and read command traffic (paragraph 0137, describing allocation of resources). In reference to Claim 9, Mundra further discloses that, for the read command, the scheduler is further configured to determine whether the one or more cryptographic operations determined for the read command is to be performed before the read command is sent to the memory (paragraph 0154, processing before cores used). In reference to Claim 10, Mundra further discloses a command buffer configured to associate the read command with data read from the memory in response to the read command (paragraphs 0077-0078). In reference to Claim 11, Mundra further discloses that the memory interface includes a data bus with encryption functionality (see Figure 20; see also Figures 1 and 11, and paragraph 0159, for example). Claims 12-17 are directed to methods corresponding substantially to the functions of the systems of Claims 1, 2, 6, and 8-10, and are rejected by a similar rationale, mutatis mutandis . In reference to Claim 18, Mundra further discloses receiving configuration data (paragraphs 0154-0155) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kershaw et al, US Patent 7966466, discloses a system where modes of operation for regions of memory are selected. Case et al, US Patent 9954681, discloses a method for selecting keys based on encryption mode of a region. Chhabra et al, US Patent 10372628, discloses a system in which different memory regions are encrypted using different keys or algorithms. Koufaty et al, US Patent 10489309, discloses a system in which encryption operations are determined based on a mode. Van Antwerpen et al, US Patent 10192062, discloses techniques for encryption that include determining a mode for an encrypted region. Koga, US Patent Application Publication 2010/0177889, discloses an apparatus with an operation mode using specific encryption processing. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Zachary A Davis whose telephone number is (571)272-3870. The examiner can normally be reached Monday-Friday, 9:00am-5:30pm, Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rupal D Dharia can be reached at (571) 272-3880. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Zachary A. Davis/Primary Examiner, Art Unit 2492 Application/Control Number: 19/004,697 Page 2 Art Unit: 2492 Application/Control Number: 19/004,697 Page 3 Art Unit: 2492 Application/Control Number: 19/004,697 Page 4 Art Unit: 2492 Application/Control Number: 19/004,697 Page 5 Art Unit: 2492 Application/Control Number: 19/004,697 Page 6 Art Unit: 2492 Application/Control Number: 19/004,697 Page 7 Art Unit: 2492 Application/Control Number: 19/004,697 Page 8 Art Unit: 2492 Application/Control Number: 19/004,697 Page 9 Art Unit: 2492 Application/Control Number: 19/004,697 Page 10 Art Unit: 2492 Application/Control Number: 19/004,697 Page 11 Art Unit: 2492 Application/Control Number: 19/004,697 Page 12 Art Unit: 2492 Application/Control Number: 19/004,697 Page 13 Art Unit: 2492 Application/Control Number: 19/004,697 Page 14 Art Unit: 2492 Application/Control Number: 19/004,697 Page 15 Art Unit: 2492
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