DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (US Pat. App. Pub. No. 20220165508).
With respect to claim 1, Nakamura discloses a solid electrolytic capacitor (see abstract) comprising: an anode plate (see FIG. 1, element 3a, and paragraph [0041]) including a porous layer at least on at least one a main surface thereof (see FIG. 1, element 3b, and paragraph [0041]); a dielectric layer on a surface of the porous layer (see paragraph [0042], noting that the dielectric layer, while not shown in the figures, but is formed on the surfaces of the porous portions 3b); a solid electrolyte layer on a surface of the dielectric layer (see FIG.1, element 7a, and paragraph [0043]); a conductor layer on a surface of the solid electrolyte layer (see FIG. 1, elements 7b/7c, and paragraph [0045]); and an insulating layer on the surface of the dielectric layer (see FIG. 1, element 52, and paragraph [0087]), wherein the insulating layer covers at least a part of an end portion of the solid electrolyte layer in a region surrounding the solid electrolyte layer (see FIG. 1, noting that insulating layer 52 covers the ends of solid electrolyte layer 7a and is in contact with porous portion (and by extension dielectric layer) 3b.
With respect to claim 2, Nakamura discloses that, in a plan view in a thickness direction of the solid electrolytic capacitor, the part of the end portion of the solid electrolyte layer covered by the insulating layer has a shortest length from the end portion of the solid electrolyte layer to an end portion of the conductor layer among all end portions of the solid electrolyte layer. See FIG. 1, where the insulating layer 52 covers the edges of all four sides of the solid electrolyte layer 7a.
With respect to claim 3, Nakamura discloses that, wherein the solid electrolyte layer has a quadrilateral shape when viewed in a thickness direction of the solid electrolytic capacitor (see paragraph [0052]), and, in a plan view in the thickness direction, the insulating layer covers at least one side of the solid electrolyte layer that includes a part at which a length from the end portion of the solid electrolyte layer to an end portion of the conductor layer is the shortest among all end portions of the solid electrolyte layer (see FIG. 1, where the insulating layer 52 covers the edges of all four sides of the solid electrolyte layer 7a).
With respect to claim 4, Nakamura discloses that, in a plan view in a thickness direction of the solid electrolytic capacitor, the insulating layer covers all end portions of the solid electrolyte layer. See FIG. 1, where the insulating layer 52 covers the edges of all four sides of the solid electrolyte layer 7a.
With respect to claim 5, Nakamura discloses that the conductor layer covers at least a part of an end portion of the insulating layer. See FIG. 1, noting that layer 7b prevents the end face of the end portion of insulating layer 52 from being exposed.
With respect to claim 6, Nakamura discloses that, in a plan view in a thickness direction of the solid electrolytic capacitor, an end portion of the conductor layer on an opposite side thereof from the solid electrolyte layer is on an outer side relative to the end portion of the solid electrolyte layer. See FIG. 1, element 7b.
With respect to claim 8, Nakamura discloses a sealing layer covering the conductor layer. See FIG. 1, element 53.
With respect to claim 9, Nakamura discloses a through hole conductor passing through the sealing layer in a thickness direction of the solid electrolytic capacitor. See FIG. 1, element 40, and paragraph [0035].
With respect to claim 10, Nakamura discloses a capacitor array comprising: a plurality of the solid electrolytic capacitors according to Claim 1. See FIG. 1, noting that at least 3 capacitors are formed.
With respect to claim 11, Nakamura discloses that in at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors, in a plan view in a thickness direction of the capacitor array, the part of the end portion of the solid electrolyte layer covered by the insulating layer has a shortest length from the end portion of the solid electrolyte layer to an end portion of the conductor layer among all end portions of the solid electrolyte layer. See FIG. 1, where the insulating layer 52 covers the edges of all four sides of the solid electrolyte layer 7a.
With respect to claim 12, Nakamura discloses that in at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors: the solid electrolyte layer has a quadrilateral shape when viewed in a thickness direction of the solid electrolytic capacitor (see paragraph [0052]), and, in a plan view in the thickness direction, the insulating layer covers at least one side of the solid electrolyte layer that includes a part at which a length from the end portion of the solid electrolyte layer to an end portion of the conductor layer is the shortest among all end portions of the solid electrolyte layer (see FIG. 1, where the insulating layer 52 covers the edges of all four sides of the solid electrolyte layer 7a).
With respect to claim 13, Nakamura discloses that, wherein in at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors, in a plan view in a thickness direction of the solid electrolytic capacitor, the insulating layer covers all end portions of the solid electrolyte layer. See FIG. 1, where the insulating layer 52 covers the edges of all four sides of the solid electrolyte layer 7a.
With respect to claim 14, Nakamura discloses that in at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors, the conductor layer covers at least a part of an end portion of the insulating layer. See FIG. 1, noting that layer 7b prevents the end face of the end portion of insulating layer 52 from being exposed.
With respect to claim 15, Nakamura discloses that in at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors, in a plan view in a thickness direction of the solid electrolytic capacitor, an end portion of the conductor layer on an opposite side thereof from the solid electrolyte layer is on an outer side relative to the end portion of the solid electrolyte layer. See FIG. 1, element 7b.
With respect to claim 17, Nakamura discloses that at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors further comprises a sealing layer covering the conductor layer. See FIG. 1, element 53.
With respect to claim 18, Nakamura discloses that wherein at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors further comprises a through hole conductor passing through the sealing layer in a thickness direction of the solid electrolytic capacitor. See FIG. 1, element 40, and paragraph [0035].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US Pat. App. Pub. No. 20220165508) in view of Furukawa (using US Pat. App. Pub. No. 2020/0312576).
With respect to claim 7, Nakamura fails to teach that the insulating layer includes a first insulating layer on the surface of the dielectric layer in a region surrounding the solid electrolyte layer and a second insulating layer on a surface of the first insulating layer, and the second insulating layer covers at least the part of the end portion of the solid electrolyte layer.
Furukawa, on the other hand, teaches disposing a first insulating layer to surround the solid electrolyte layer, with a thickness the same thereof, and then layering a second insulating layer on top of the first insulating layer. See FIG. 1, elements 30 and 12. Such an arrangement provides an effective demarcation between the capacitor elements. See paragraph [0095].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Nakamura, as taught by Furukawa, in order to effectively demarcate and insulate the capacitor elements.
With respect to claim 16, Nakamura fails to teach wherein in at least one solid electrolytic capacitor of the plurality of solid electrolytic capacitors: the insulating layer includes a first insulating layer on the surface of the dielectric layer in a region surrounding the solid electrolyte layer and a second insulating layer on a surface of the first insulating layer, and the second insulating layer covers at least the part of the end portion of the solid electrolyte layer.
Furukawa, on the other hand, teaches disposing a first insulating layer to surround the solid electrolyte layer, with a thickness the same thereof, and then layering a second insulating layer on top of the first insulating layer. See FIG. 1, elements 30 and 12. Such an arrangement provides an effective demarcation between the capacitor elements. See paragraph [0095].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Nakamura, as taught by Furukawa, in order to effectively demarcate and insulate the capacitor elements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Suzuki et al. (US 2023/0062760), Kumakawa et al. (US 2020/0194187), and Tsutsumi (US 2019/0237266) each disclose solid electrolytic capacitors having insulating layers disposed on the dielectric layers, but fail to teach the specific details recited in claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole, can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DION R. FERGUSON/Primary Examiner, Art Unit 2847
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