Prosecution Insights
Last updated: July 17, 2026
Application No. 19/004,920

METHOD AND SYSTEM FOR OPERATING MULTIPLE ANALOG-TO-DIGITAL CONVERTORS POSITIONED ON A SINGLE SEMICONDUCTOR DIE

Non-Final OA §DP
Filed
Dec 30, 2024
Priority
Oct 28, 2022 — continuation of 12/212,331
Examiner
JEAN PIERRE, PEGUY
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
984 granted / 1044 resolved
+26.3% vs TC avg
Minimal -1% lift
Without
With
+-0.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
9 currently pending
Career history
1051
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1044 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 1/7/25 and 12/30/24are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 12 of U.S. Patent No. 12,212,331. Although the claims at issue are not identical, they are not patentably distinct from each other because both sets of claims recite the same subject matter with colorable differences. Claim 1 of the patent recites: A device, comprising: a first analog-to-digital converter (ADC) configured to: receive a first analog signal; and perform sampling and conversion of the first analog signal during a first period of time to generate a first digital value; a second ADC configured to: receive a second analog signal; and perform sampling and conversion of the second analog signal during a second period of time to generate a second digital value; and circuitry coupled to the first ADC and the second ADC and configured to: determine whether the first period of time overlaps with the second period of time; and determine whether to generate a first indication or a second indication for the first digital value based on determining whether the first period of time overlaps with the second period of time. This limitation is quasi-identical to claim 1 of the patent. Claim 1 of the application recites a “device” whereas claim 1 of the patent recites an “integrated circuit”. It is well known that devices are built on integrated circuit. Both sets of claims recite that the period laps with the second period of time, the patent call the limitation noisy, the same name can be attributed to the present application. Claim 11 of the patent recites: 11. A method, comprising: performing, by a first ADC, sampling and conversion of a first analog signal during a first period of time to generate a first digital value; performing, by a second ADC, sampling and conversion of a second analog signal during a second period of time to generate a second digital value; determining, by circuitry, whether the first period of time overlaps with the second period of time; and determining, by the circuitry, whether to generate a first indication or a second indication for the first digital value based on determining whether the first period of time overlaps with the second period of time. This limitation is quasi- identical to claim 1 of the patent. Claim 12 of the application recites a “device” whereas claim 11 of the patent recites an “integrated circuit”. It is well known that devices are built on integrated circuit. Both sets of claims recite that the period of time overlaps with the second period of time. The patent calls the limitation noisy, the same can be attributed to the present application. Allowable Subject Matter Claims 2-10 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105. /PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Dec 30, 2024
Application Filed
Jul 07, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12683624
DUAL ARBITRATION AND INTERLEAVED SAMPLING ANALOG-TO-DIGITAL CONVERTER (ADC)
2y 3m to grant Granted Jul 14, 2026
Patent 12683618
CURRENT-OUTPUT DIGITAL-TO-ANALOG CONVERTER
1y 9m to grant Granted Jul 14, 2026
Patent 12676627
ANALOG-TO-DIGITAL CONVERTER AND SEMICONDUCTOR DEVICE HAVING THE SAME
2y 6m to grant Granted Jul 07, 2026
Patent 12676626
ANALOG-TO-DIGITAL CONVERTER
2y 3m to grant Granted Jul 07, 2026
Patent 12676630
DIGITAL-TO-ANALOG CONVERTER AND APPARATUS INCLUDING THE SAME
1y 11m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
94%
With Interview (-0.7%)
1y 8m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1044 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month