DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed on 07/09/2026, with respect to the Examiner’s restriction requirement of 04/09/2026, have been fully considered and are persuasive. Therefore, the restriction requirement has been withdrawn and the clams 1-20 are searched and examined.
Claim Objections
Claims 1-12 are objected to because of the following informalities:
In claim 1, line 15, it is suggested that “the discrete time filter” be replaced with “the discrete time equalizer” to be consistent with prior description in this claim.
Claims 2-12 are depending on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5, 10, 11, 13, 14, 16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2021/0281449 A1).
Consider claim 1:
Wang discloses a receiver (see Fig. 1 and paragraph 0013, where Wang describes a receiving integrated circuit) comprising:
an adaptable continuous time equalizer (CTE) having a CTE signal input, a CTE control input, and a CTE output, the CTE configured to filter an input signal received at the CTE signal input according to an adaptable filter characteristic, the adaptable filter characteristic based on a CTE setting received at the CTE control input (see Fig. 1 and paragraph 0013, where Wang describes that the receiving integrated circuit includes a Continuous Time Linear Equalizer (CTLE) circuitry 120 which is adaptively adjusted by a Parameter Adjustment 150);
an adaptable discrete time equalizer (DTE) having a DTE signal input and a DTE control input, the DTE signal input coupled to the CTE output (see Fig. 1 and paragraph 0020, where Wang describes that the output of the CTLE circuitry 120 is provided to a gain circuitry 125 followed by a Digital Equalizer circuitry 145; see Fig. 1 and paragraph 0034, where Wang describes that the gain circuitry 125 has a gain g(k) at discrete time k, and that the gain g(k) is adjusted by a Parameter Adjustment 150); and
logic circuitry coupled to the CTE control input and to the DTE (see Fig. 1 and paragraphs 0019-0020, where Wang describes that the Parameter Adjustment 150 is connected to the CTLE circuitry 120 and the gain circuitry 125 of the Digital Equalizer circuitry 145), the logic circuitry configured to:
determine a frequency response of the DTE (see paragraph 0020, where Wang describes that the gain of the gain circuitry 125 amplifies both high-frequency and low-frequency components of received signals; see paragraph 0034, where Wang describes that the gain circuitry 125 provides amplitudes of symbols of the amplified frequencies);
determine that the frequency response has changed by more than a threshold amount (see Fig. 1 and paragraph 0034, where Wang describes a process that determines data samples whose amplitudes are above or below a target amplitude threshold);
sequentially configure the CTE for multiple CTE settings based on the change in the frequency response of the discrete time filter (see paragraph 0034, where Wang describes that the Parameter Adjustment 150 obtains information about data samples whose amplitudes are above or below the target threshold; see paragraph 0019, where Wang describes that the Parameter Adjustment 150 adjusts the gains of the CTLE circuitry 120 to provide both the low-frequency gain and the high-frequency boost);
determine a separate figure of merit (FOM) for each of the multiple CTE settings (see paragraph 0012, where Wang describes that a figure of merit is calculated for current CTLE parameter settings);
select a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings (see paragraph 0012, where Wang describes that a set of CTLE parameter settings are found from various CTLE parameter settings based on the figure of merit for the various CTLE parameter settings); and
provide the new CTE setting to the CTE control input (see Fig. 1 and paragraph 0015, where Wang describes that the Parameter Adjustment 150 may control one or more parameters of the CTLE circuitry 120).
Consider claims 13 and 18:
Wang discloses a retimer (see Fig. 1 and paragraph 0013, where Wang describes a receiving integrated circuit) comprising:
an adaptable continuous time equalizer (CTE) having a CTE signal input, a CTE control input, and a CTE output, the CTE configured to filter an input signal received at the CTE signal input according to an adaptable filter characteristic, the adaptable filter characteristic based on a CTE setting received at the CTE control input (see Fig. 1 and paragraph 0013, where Wang describes that the receiving integrated circuit includes a Continuous Time Linear Equalizer (CTLE) circuitry 120 which is adaptively adjusted by a Parameter Adjustment 150);
an adaptable discrete time equalizer (DTE) having a DTE signal input and a DTE control input, the DTE signal input coupled to the CTE output (see Fig. 1 and paragraph 0020, where Wang describes that the output of the CTLE circuitry 120 is provided to a gain circuitry 125 followed by a Digital Equalizer circuitry 145; see Fig. 1 and paragraph 0034, where Wang describes that the gain circuitry 125 has a gain g(k) at discrete time k, and that the gain g(k) is adjusted by a Parameter Adjustment 150); and
logic circuitry coupled to the CTE control input and to the DTE (see Fig. 1 and paragraphs 0019-0020, where Wang describes that the Parameter Adjustment 150 is connected to the CTLE circuitry 120 and the gain circuitry 125 of the Digital Equalizer circuitry 145), the logic circuitry configured to:
determine a gain of the DTE (see Fig. 1 and paragraph 0034, where Wang describes that a gain g(k) of the gain circuitry 125 is determined for the Digital Equalizer circuitry 145);
determine whether the gain has increased or decreased by more than a threshold amount (see Fig. 1 and paragraph 0034, where Wang describes that an error function e(k) is calculated to determine a change of gain, the e(k) is calculated based on thresholds Tneg, Tpos and Ttarget);
responsive to a determination that the gain has increased or decreased by more than the threshold amount, sequentially configure the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE (see paragraph 0034, where Wang describes that the Parameter Adjustment 150 adjusts the gains of the gain circuitry 125 based on the error function e(k); see paragraph 0020, where Wang describes that both high-frequency and low-frequency components of the received signals are amplified by the gain circuitry 125, based on a series of digital samples; see paragraph 0019, where Wang describes that the Parameter Adjustment 150 also adjusts the gains of the CTLE circuitry 120 to provide both the low-frequency gain and the high-frequency boost);
determine a separate figure of merit (FOM) for each of the multiple CTE settings (see paragraph 0012, where Wang describes that a figure of merit is calculated for current CTLE parameter settings);
select a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings (see paragraph 0012, where Wang describes that a set of CTLE parameter settings are found from various CTLE parameter settings based on the figure of merit for the various CTLE parameter settings); and
provide the new CTE setting to the CTE control input (see Fig. 1 and paragraph 0015, where Wang describes that the Parameter Adjustment 150 may control one or more parameters of the CTLE circuitry 120).
Consider claims 3 and 14:
Wang discloses the invention of claims 1 and 13 above. Wang discloses: the discrete time filter is a feed-forward equalizer (FFE) (see Fig. 1 and paragraph 0042, where Wang describes that the Digital Equalizer circuitry 145 includes one or more feed-forward equalization circuits).
Consider claim 5:
Wang discloses the receiver of claim 1 above. Wang discloses: the frequency response includes a gain value (see Fig. 1 and paragraph 0020, where Wang describes that a gain of the gain circuitry 125 is used to amplify both high-frequency and low-frequency components of received signals), and the logic circuitry is configured to determine that the frequency response has changed by more than the threshold amount by determining that the gain value has increased by more than a first threshold amount or that the gain value has decreased by more than a second threshold amount (see paragraph 0034, where Wang describes that the Parameter Adjustment 150 obtains information about data samples whose amplitudes are above or below the target threshold; see paragraph 0019, where Wang describes that the Parameter Adjustment 150 adjusts the gains of the CTLE circuitry 120 to provide both the low-frequency gain and the high-frequency boost).
Consider claims 10 and 16:
Wang discloses the receiver of claim 1 above. Wang discloses: the adaptable CTE is an adaptable continuous time linear equalizer (CTLE) (see Fig. 1 and paragraph 0013, where Wang describes a Continuous Time Linear Equalizer (CTLE) circuitry 120).
Consider claim 11:
Wang discloses the receiver of claim 1 above. Wang discloses: the logic circuitry includes a microcontroller (see Fig. 9 and paragraph 0061, where Wang describes that the receiving integrated circuit includes processors 902).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0281449 A1), as applied to claim 1 above, and further in view of Chappell (US 2002/0141494 A1).
Consider claim 2:
Wang discloses the receiver of claim 1 above. Wang discloses: the DTE includes a discrete time filter having a plurality of adaptable tap weights (see Fig. 1 and paragraph 0042, where Wang describes that the Digital Equalizer circuitry 145 uses tap weights).
Wang does not specifically disclose: the logic circuitry is configured to determine the frequency response by determining a Fourier transform of the adaptable tap weights.
Chappell teaches: a logic circuitry is configured to determine a frequency response by determining a Fourier transform of adaptable tap weights (see Figure 2 and paragraph 0054, where Chappell describes a processor 100 which transforms the tap weights into a relative frequency response by performing a Fast Fourier Transform (FFT)).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the logic circuitry is configured to determine the frequency response by determining a Fourier transform of the adaptable tap weights, as taught by Chappell to modify the method of Wang in order to generate the absolute level frequency response, as discussed by Chappell (see paragraph 0054).
Claims 4, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0281449 A1), as applied to claims 1 and 3 above, and further in view of Zhong (US 2014/0254655 A1).
Consider claim 4:
Wang discloses the receiver of claim 3 above. Wang does not specifically disclose: the DTE includes a decision-feedback equalizer (DFE).
Zhong teaches: a DTE includes a decision-feedback equalizer (DFE) (see Fig. 4 and paragraphs 0041-0042, where Zhong describes a receiver circuit 150 which includes a discrete decision feedback equalizer (DFE) 158 that receives the signal Y(T) provided by CT-LE 152, the DFE 158 is controlled by a signal DFE from the adaptation circuit 162).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the DTE includes a decision-feedback equalizer (DFE), as taught by Zhong to modify the method of Wang in order to adjust equalizer setting based on error samples, as discussed by Zhong (see paragraph 0004).
Consider claim 7:
Wang discloses the receiver of claim 1 above. Wang discloses: the frequency response includes a gain value (see Fig. 1 and paragraph 0020, where Wang describes that a gain of the gain circuitry 125 is used to amplify both high-frequency and low-frequency components of received signals).
Wang does not specifically disclose: determine that the gain value has increased by more than the threshold amount, and sequentially configure the CTE for the multiple new CTE settings such that a gain of the CTE also increases.
Zhong teaches: determine that a gain value has increased by more than a threshold amount (see Fig. 4 and paragraphs 0043-0044, where Zhong describes that the adaptation circuit 162 determines adjustment of the gain of the DFE 158 using error samples EK1, …, EKQ which are generated in response to a predetermined threshold), and sequentially configure a CTE for multiple new CTE settings such that a gain of the CTE also increases (see Fig. 4 and paragraph 0044, where Zhong describes that the gain of the CT-LE 152 and the gain of the DFE 158 are adjusted using the same error samples EK1, …, EKQ).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: determine that the gain value has increased by more than the threshold amount, and sequentially configure the CTE for the multiple new CTE settings such that a gain of the CTE also increases, as taught by Zhong to modify the method of Wang in order to adjust equalizer setting based on error samples, as discussed by Zhong (see paragraph 0004).
Consider claim 8:
Wang discloses the receiver of claim 1 above. Wang discloses: the frequency response includes a gain value (see Fig. 1 and paragraph 0020, where Wang describes that a gain of the gain circuitry 125 is used to amplify both high-frequency and low-frequency components of received signals).
Wang does not specifically disclose: determine that the gain value has decreased by more than the threshold amount, and sequentially configure the CTE for the multiple new CTE settings such that a gain of the CTE also decreases.
Zhong teaches: determine that a gain value has decreased by more than a threshold amount (see Fig. 4 and paragraphs 0043-0044, where Zhong describes that the adaptation circuit 162 determines adjustment of the gain of the DFE 158 using error samples EK1, …, EKQ which are generated in response to a predetermined threshold); and sequentially configure a CTE for multiple new CTE settings such that a gain of the CTE also decreases (see Fig. 4 and paragraph 0044, where Zhong describes that the gain of the CT-LE 152 and the gain of the DFE 158 are adjusted using the same error samples EK1, …, EKQ).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: determine that the gain value has decreased by more than the threshold amount, and sequentially configure the CTE for the multiple new CTE settings such that a gain of the CTE also decreases, as taught by Zhong to modify the method of Wang in order to adjust equalizer setting based on error samples, as discussed by Zhong (see paragraph 0004).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0281449 A1), as applied to claims 5 and 13 above, and further in view of Perisetty et al. (US 11,665,031 B1).
Consider claims 6 and 15:
Wang discloses the invention of claims 5 and 13 above. Wang does not specifically disclose: the gain value is a gain value at a Nyquist frequency of the receiver.
Perisetty teaches: a gain value at a Nyquist frequency of a receiver (see col. 2, lines 49-54, where Perisetty describes a control which adjust a peaking gain of a frequency response around a system Nyquist frequency during receiver adaptation).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the gain value is a gain value at a Nyquist frequency of the receiver, as taught by Perisetty to modify the method of Wang in order to have an improved gain/bandwidth trade-off, as discussed by Perisetty (see col. 2, lines 49-54).
Claims 9, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0281449 A1), as applied to claims 1, 13 and 18 above, and further in view of Wang et al. (US 2012/0300829 A1), hereafter Wang-II.
Consider claims 9, 17 and 20:
Wang discloses the invention of claims 1, 13 and 18 above. Wang does not specifically disclose: the logic circuitry is configured to determine a ratio of a current gain value of the discrete time equalizer to a previous gain value of the discrete time equalizer, and to determine that the frequency response has changed by more than the threshold amount by determining that the ratio has increased by more than a first threshold amount or that the ratio has decreased by more than a second threshold amount.
Wang-II teaches: a logic circuitry is configured to determine a ratio of a current gain value of the discrete time equalizer to a previous gain value of the discrete time equalizer (see Fig. 3 and paragraph 0041, where Wang describes an equalizer that switches its gain between gain γT and gain γM; see Fig. 7 and paragraphs 0047-0048, where Wang describes a controller which calculates a gain ratio GT = γT / γM ), and to determine that the frequency response has changed by more than the threshold amount by determining that the ratio has increased by more than a first threshold amount or that the ratio has decreased by more than a second threshold amount (see Fig. 7 and paragraphs 0047-0048, where Wang describes that the gain ratio GT is compared with a threshold GMIN).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the logic circuitry is configured to determine a ratio of a current gain value of the discrete time equalizer to a previous gain value of the discrete time equalizer, and to determine that the frequency response has changed by more than the threshold amount by determining that the ratio has increased by more than a first threshold amount or that the ratio has decreased by more than a second threshold amount, as taught by Wang-II to modify the method of Wang in order to improve performance, as discussed by Wang-II (see paragraphs 0005-0006).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0281449 A1), as applied to claim 1 above, and further in view of Chen (US 2019/0068397 A1).
Consider claim 12:
Wang discloses the receiver of claim 1 above. Wang does not specifically disclose: the receiver is a retimer.
Chen teaches: a receiver is a retimer (see Fig. 1 and paragraph 0023, where Chen describes a retimer 107 that is a repeater).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the receiver is a retimer, as taught by Chen to modify the method of Wang in order to restore weakened signal, as discussed by Chen (see paragraph 0024).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0281449 A1), as applied to claim 18 above, and further in view of Guzik et al. (US 2015/0349983 A1).
Consider claim 19:
Wang discloses the method of claim 18 above. Wang does not specifically disclose: determining a Fourier transform of a frequency response of the discrete time filter.
Guzik teaches: determining a Fourier transform of a frequency response of a discrete time filter (see Fig. 2 and paragraph 0019, where Guzik describes a pre-equalizer coefficients calculator 27 which calculates the frequency responses for a digital pre-equalizer 21, and determines desired pre-equalizer coefficients by applying a direct Fourier transform to the frequency responses).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: determining a Fourier transform of a frequency response of the discrete time filter, as taught by Guzik to modify the method of Wang in order to have a significant reduction of required computation resources, as discussed by Guzik (see paragraph 0010).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIHONG YU whose telephone number is (571)270-5147. The examiner can normally be reached 10:00 am-6:00 pm EST Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hannah S. Wang can be reached at (571)272-9018. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LIHONG YU/Primary Examiner, Art Unit 2631
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