DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rha et al (US 2019/0147796 A1).
Regarding claim 1, Rha discloses a display panel, comprising:
a light-emitting element [e.g., Fig. 7: OLED];
a driving transistor [e.g., Fig. 7: DT] for driving the light-emitting element;
a first switching transistor [e.g., Fig. 7: T4, T5] configured to be switched to apply an initialization voltage [e.g., Fig. 7: Vinit] to each of a first electrode [e.g., Fig. 9B: N4] of the light-emitting element and a gate electrode [e.g., Fig. 9A: DT’s gate connected to N2] of the driving transistor;
a second switching transistor [e.g., Fig. 7: T1] configured to be switched to apply a sampling voltage [e.g., Fig. 7: Vdata] different from a data voltage [e.g., Fig. 7: EVDD voltage] to a first electrode [e.g., Fig. 9B: DT’s drain connected to N3] of the driving transistor; and
a third switching transistor [e.g., Fig. 7: T3] and a sampling capacitor [e.g., Fig. 7: Cst] directly connected to each other [e.g., Fig. 7: T3 and Cst are directly connected to each other at N2] between the gate electrode and the first electrode of the driving transistor [e.g., Fig. 7: wherein T3’s and Cst’s direct connection (at N2) is “between” DT’s gate (through direct connection) and drain (through T3, N3), wherein T3 is “between” is between DT’s gate (through N2) and drain (through N3), and wherein Cst is “between” DT’s gate and drain (e.g., the bottom plate of Cst is connected to the DT’s gate (through N2) and the top plate of Cst is connected to DT’s drain (through T2, N1, DT, N3)] (e.g., see Paragraphs 80-113).
Regarding claim 2, Rha discloses the first switching transistor is an N-type thin-film transistor (e.g., see Paragraph 81),
wherein the first switching transistor is configured to receive the initialization voltage at a first electrode [e.g., Fig. 7: source T4, T5] of the first switching transistor,
wherein the first electrode of the light-emitting element is connected to a second electrode [e.g., Fig. 7: drain T4, T5] of the first switching transistor,
wherein the first switching transistor is configured to receive an (n−2)-th light-emission signal [e.g., Fig. 7: SC(n-1)] at a gate electrode [e.g., Fig. 7: gate T4] of the first switching transistor, and wherein n is a natural number (e.g., see Paragraphs 42-113).
Regarding claim 3, Rha discloses the second switching transistor is a P-type thin-film transistor (e.g., see Paragraph 81),
wherein the second switching transistor is configured to receive the sampling voltage at a first electrode [e.g., Fig. 7: source T1] of the second switching transistor,
wherein the first electrode of the driving transistor is connected to a second electrode [e.g., Fig. 7: drain T1] of the second switching transistor,
wherein the second switching transistor is configured to receive an (n−1)-th scan signal [e.g., Fig. 7: SC(n)] at a gate electrode [e.g., Fig. 7: gate T1] of the second switching transistor, and wherein n is a natural number (e.g., see Paragraphs 42-113).
Regarding claim 4, Rha discloses the sampling capacitor connected to the first electrode of the driving transistor, is configured to store the sampling voltage (e.g., see Figs. 9BC; Paragraph 104).
Regarding claim 5, Rha discloses the first electrode of the driving transistor is connected to a first electrode [e.g., Fig. 7: Cst top plate] of the sampling capacitor,
wherein a first electrode [e.g., Fig. 7: source T3] of the third switching transistor is connected to a second electrode [e.g., Fig. 7: Cst bottom plate] of the sampling capacitor, wherein the third switching transistor is an N-type thin-film transistor (e.g., see Paragraph 81),
wherein a second electrode [e.g., Fig. 7: drain T4, T5] of the first switching transistor is connected to a second electrode [e.g., Fig. 7: drain T3] of the third switching transistor,
wherein the third switching transistor is configured to receive an (n−2)-th light-emission signal [e.g., Fig. 7: SC(n)] at a gate electrode [e.g., Fig. 7: gate T3] of the third switching transistor, and wherein n is a natural number (e.g., see Paragraphs 42-113).
Regarding claim 6, Rha discloses a fourth switching transistor [e.g., Fig. 7: T3] is connected to and disposed between the gate electrode and a second electrode [e.g., Fig. 9B: DT’s source connected to N1] of the driving transistor, and
wherein a fifth switching transistor [e.g., Fig. 7: T2] is connected to the second electrode of the driving transistor (e.g., see Paragraphs 42-113).
Regarding claim 7, Rha discloses the fourth switching transistor is an N-type thin-film transistor (e.g., see Paragraph 81),
wherein the second electrode of the driving transistor is connected to a first electrode [e.g., Fig. 7: source T3] of the fourth switching transistor,
wherein the gate electrode of the driving transistor is connected to a second electrode [e.g., Fig. 7: drain T3] of the fourth switching transistor,
wherein the fourth switching transistor is configured to receive a first scan signal [e.g., Fig. 7: SC(n)] at a gate electrode [e.g., Fig. 7: gate T3] of the fourth switching transistor,
wherein the fifth switching transistor is a P-type thin-film transistor (e.g., see Paragraph 81),
wherein a potential driving voltage line [e.g., Fig. 7: 17] is connected to a first electrode [e.g., Fig. 7: source T2] of the fifth switching transistor,
wherein the second electrode of the driving transistor is connected to a second electrode [e.g., Fig. 7: drain T2] of the fifth switching transistor,
wherein the fifth switching transistor is configured to receive an n-th light-emission signal [e.g., Fig. 7: EM(n)] at a gate electrode [e.g., Fig. 7: gate T2] of the fifth switching transistor, and wherein n is a natural number (e.g., see Paragraphs 42-113).
Regarding claim 8, Rha discloses a sixth switching transistor [e.g., Fig. 7: ET] is connected to and disposed between the light-emitting element and the driving transistor, and
wherein a seventh switching transistor [e.g., Fig. 7: T2] is connected to and disposed between the sixth switching transistor and the driving transistor (e.g., see Paragraphs 42-113).
Regarding claim 9, Rha discloses the seventh switching transistor is configured to receive the data voltage at a first electrode [e.g., Fig. 7: source T2] of the seventh switching transistor,
wherein a first electrode [e.g., Fig. 7: source ET] of the sixth switching transistor is connected to a second electrode [e.g., Fig. 7: drain T2] of the seventh switching transistor,
wherein the seventh switching transistor is configured to receive an n-th second scan signal [e.g., Fig. 7: 3rd EM(n)] at a gate electrode [e.g., Fig. 7: gate T2] of the seventh switching transistor,
wherein the sixth switching transistor is configured to receive an (n−2)-th light-emission signal [e.g., Fig. 7: 1st EM(n)] at a gate electrode [e.g., Fig. 7: gate ET] of the sixth switching transistor,
wherein the first electrode of the light-emitting element is connected to a second electrode [e.g., Fig. 7: drain ET] of the sixth switching transistor, and wherein each n is a natural number (e.g., see Paragraphs 42-113).
Regarding claim 10, this claim is rejected by claim 1; furthermore, Rha discloses a display device, comprising:
a display panel including:
a light-emitting element [e.g., Fig. 7: OLED];
a driving transistor [e.g., Fig. 7: DT] for driving the light-emitting element;
a first switching transistor [e.g., Fig. 7: T4, T5] configured to be switched to apply an initialization voltage [e.g., Fig. 7: Vinit] to each of a first electrode [e.g., Fig. 9B: N4] of the light-emitting element and a gate electrode [e.g., Fig. 9A: DT’s gate connected to N2] of the driving transistor; and
a second switching transistor [e.g., Fig. 7: T1] configured to be switched to apply a sampling voltage [e.g., Fig. 7: Vdata] to a first electrode [e.g., Fig. 9B: DT’s drain connected to N3] of the driving transistor; and
a third switching transistor [e.g., Fig. 7: T3] and a sampling capacitor [e.g., Fig. 7: Cst] directly connected to each other [e.g., Fig. 7: T3 and Cst are directly connected to each other at N2] between the gate electrode and the first electrode of the driving transistor [e.g., Fig. 7: wherein T3’s and Cst’s direct connection (at N2) is “between” DT’s gate (through direct connection) and drain (through T3, N3), wherein T3 is “between” is between DT’s gate (through N2) and drain (through N3), and wherein Cst is “between” DT’s gate and drain (e.g., the bottom plate of Cst is connected to the DT’s gate (through N2) and the top plate of Cst is connected to DT’s drain (through T2, N1, DT, N3)];
a light-emission driver [e.g., Fig. 1: 13 for Fig. 7: SC(n-1)] configured to supply a light-emission signal [e.g., Fig. 7: SC(n-1)] to the first switching transistor;
a scan driver [e.g., Fig. 1: 13 for Fig. 7: SC(n)] configured to supply a scan signal [e.g., Fig. 7: SC(n)] to the second switching transistor;
a data driver [e.g., Fig. 1: 12, EVDD source] configured to supply a data voltage [e.g., Fig. 7: EVDD voltage] to a connection node [e.g., Fig. 9C: N1, N3, N4] of the light-emitting element and the driving transistor; and
a controller [e.g., Fig. 1: 11] configured to control the light-emission driver, the scan driver, and the data driver (e.g., see Paragraphs 42-113).
Regarding claim 11, Rha discloses during a first period [e.g., Fig. 8: IP1, SP1], the light-emission driver is configured to apply an (n−2)-th light-emission signal [e.g., Fig. 8: SC(n-1) on, SC(n) on] to the first switching transistor to turn on the first switching transistor, wherein responsive to the first switching transistor being turned on, the first switching transistor is configured to apply the initialization voltage to each of the light-emitting element and the driving transistor to cause the first electrode of the light-emitting element and the gate electrode of the driving transistor to be initialized, and wherein n is a natural number (e.g., see Paragraphs 42-113).
Regarding claim 12, Rha discloses during a second period [e.g., Fig. 8: SP1], the scan driver is configured to apply an (n−1)-th second scan signal [e.g., Fig. 8: SC(n) on] to the second switching transistor to turn on the second switching transistor, wherein responsive to the second switching transistor being turned on, the second switching transistor is configured to apply the sampling voltage to the first electrode of the driving transistor to cause the gate electrode of the driving transistor to be sampled based on a voltage obtained by adding the sampling voltage to a threshold voltage [e.g., Paragraph 99: Vth] of the driving transistor, and wherein n is a natural number (e.g., see Paragraphs 42-113).
Regarding claim 13, this claim is rejected by claim 4; furthermore, Rha discloses the sampling capacitor connected to the first electrode of the driving transistor, is configured to store the sampling voltage (e.g., see Figs. 9BC; Paragraph 104).
Regarding claim 14, Rha discloses a fourth switching transistor [e.g., Fig. 7: T2] is connected to the first electrode of the driving transistor,
wherein during a third period [e.g., Fig. 8: EP],
the scan driver is configured to apply an n-th second scan signal [e.g., Fig. 8: EM(n) on] to the fourth switching transistor to turn on the fourth switching transistor, and
wherein responsive to the fourth switching transistor being turned on,
the driving transistor is configured to receive the data voltage at the first electrode of the driving transistor (e.g., see Fig. 9C; Paragraphs 42-113).
Regarding claim 15, Rha discloses the driving transistor is configured to receive, at the gate electrode of the driving transistor, a voltage obtained by subtracting the sampling voltage from the data voltage (e.g., see Paragraph 104).
Response to Arguments
Applicant's arguments filed on 13 February 2026 have been fully considered but they are not persuasive.
The Applicant contends, “a distinction exists in that the claimed second switching transistor (e.g., T6) applies a sampling voltage (e.g., Vsam) to the first electrode of the driving transistor (e.g., DT), whereas T1 of Rha applies a data voltage Vdata to the first electrode of the driving transistor DT. The sampling voltage (e.g., Vsam) is a distinct voltage that is entirely different from the data voltage Vdata. Furthermore, Rha contains no disclosure of a sampling voltage Vsam. Therefore, T1 of Rha cannot correspond to the claimed second switching transistor (e.g., T6)” (see Page 10 of the Response filed on 13 February 2026). However, the Office respectfully disagrees.
Rha discloses a second switching transistor [e.g., Fig. 7: T1] configured to be switched to apply a sampling voltage [e.g., Fig. 7: Vdata] different from a data voltage [e.g., Fig. 7: EVDD voltage] to a first electrode [e.g., Fig. 9B: DT’s drain connected to N3] of the driving transistor. Calling one voltage “a sampling voltage” and another “a data voltage” is merely a labeling convention.
The Applicant contends, “the claimed third switching transistor (e.g., T7) and the claimed sampling capacitor (e.g., Csam) are directly connected to each other between the gate electrode and the first electrode of the driving transistor (e.g., DT). In contrast, in Rha, only T3 is connected between the gate electrode and the first electrode of the driving transistor DT, while Cst is not connected between the gate electrode and the first electrode of the driving transistor DT” (see Pages 10-11 of the Response filed on 13 February 2026). However, the Office respectfully disagrees.
Firstly, from the way claims 1 and 10 are presently written, it isn’t at all clear that the sampling capacitor (or the third switching transistor) must be “between” the gate electrode and the first electrode of the driving transistor.
If anything, an artisan might reasonably read the claim language as saying the direct connection/point itself (between the third switching transistor and sampling capacitor) is “between” the gate electrode and the first electrode of the driving transistor.
Regardless, Rha discloses each of the third switching transistor, the sampling capacitor, and the direct connection (between the two of them) are “between” the gate electrode and the first electrode of the driving transistor.
Rha discloses a third switching transistor [e.g., Fig. 7: T3] and a sampling capacitor [e.g., Fig. 7: Cst] directly connected to each other [e.g., Fig. 7: T3 and Cst are directly connected to each other at N2] between the gate electrode and the first electrode of the driving transistor [e.g., Fig. 7: wherein T3’s and Cst’s direct connection (at N2) is “between” DT’s gate (through direct connection) and drain (through T3, N3), wherein T3 is “between” is between DT’s gate (through N2) and drain (through N3), and wherein Cst is “between” DT’s gate and drain (e.g., the bottom plate of Cst is connected to the DT’s gate (through N2) and the top plate of Cst is connected to DT’s drain (through T2, N1, DT, N3)].
Additionally, the Applicant is reminded that the instant application states, “it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present” (Instant Specification Paragraph 48, Page 11).
The Applicant contends, “Rha does not disclose or teach at least the features of: "a second switching transistor configured to be switched to apply a sampling voltage different from a data voltage to a first electrode of the driving transistor; and a third switching transistor and a sampling capacitor directly connected to each other between the gate electrode and the first electrode of the driving transistor," as recited in amended claim 1” (see Page 11 of the Response filed on 13 February 2026). However, the Office respectfully disagrees.
Rha discloses a second switching transistor [e.g., Fig. 7: T1] configured to be switched to apply a sampling voltage [e.g., Fig. 7: Vdata] different from a data voltage [e.g., Fig. 7: EVDD voltage] to a first electrode [e.g., Fig. 9B: DT’s drain connected to N3] of the driving transistor; and
a third switching transistor [e.g., Fig. 7: T3] and a sampling capacitor [e.g., Fig. 7: Cst] directly connected to each other [e.g., Fig. 7: T3 and Cst are directly connected to each other at N2] between the gate electrode and the first electrode of the driving transistor [e.g., Fig. 7: wherein T3’s and Cst’s direct connection (at N2) is “between” DT’s gate (through direct connection) and drain (through T3, N3), wherein T3 is “between” is between DT’s gate (through N2) and drain (through N3), and wherein Cst is “between” DT’s gate and drain (e.g., the bottom plate of Cst is connected to the DT’s gate (through N2) and the top plate of Cst is connected to DT’s drain (through T2, N1, DT, N3)] (e.g., see Paragraphs 80-113).
Applicant's arguments with respect to claims 1-15 have been considered but are moot in view of any new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated any new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
29 May 2026
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