Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application (on 2 September 2026) after final rejection (mailed 3 June 2026). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2 September 2026 has been entered.
Response to Arguments
Applicant’s arguments filed 2 September 2026 with respect to claims 1-15 have been considered but are moot in view of the new grounds of rejection set forth below, which do not rely on the mapping applied in the 3 June 2026 action.
Applicant’s sole argument is that Rha’s third switching TFT T3 and storage capacitor Cst are connected to each other at the second node N2, which is the gate node of the driving TFT, so that Rha does not disclose the newly added limitation that the third switching transistor and the sampling capacitor are directly connected to each other at a node that is not directly connected to the gate electrode (Remarks, pages 8-11).
The rejections below rely on Yu, Choi, Kim, Park and, in a separate ground, on a different reading of Rha in which the second switching TFT T2 and the storage capacitor Cst -- connected to each other at the high potential power line 17, a node connected to the gate electrode N2 only through Cst -- are the claimed third switching transistor and sampling capacitor [e.g., Rha Paragraph 87: a first electrode of the second switching TFT T2 is connected to the high potential power line 17, and a second electrode of the second switching TFT T2 is connected to the first node N1; Paragraph 91: The storage capacitor Cst is connected between the high potential power line 17 and the second node N2].
The argument addressed to the T3/Cst junction at N2 therefore does not reach any rejection made below.
Claim Interpretation
The claims are given their broadest reasonable interpretation in light of the specification. As set out in the constructions stated with each ground, the instant specification provides that when an element is referred to as being between two elements, [e.g., Instant Specification Paragraph 48: it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present -- see also instant Specification Paragraph 40], and that [e.g., Instant Specification Paragraph 277: a first electrode may denote a second electrode, and, similarly, a second electrode may denote a first electrode].
Applicant has not contested either definition.
Claim Rejections - 35 USC § 102 / 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 6, 8 and 9 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Yu et al (US 2023/0010040 A1);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Yu in view of Choi (US 2009/0219232 A1).
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Construction stated for this ground.
Under the instant specification’s definitions of between and of the electrode designations (Instant Specification Paragraphs 40, 48 and 277, quoted above), Yu’s node designations are read as follows: the first electrode of the driving transistor is the electrode at Yu’s third node n3 (the electrode to which the reference voltage is applied), and the second electrode is the electrode at Yu’s first node n1.
The seventh switch element T7 and the second capacitor C2 are read as the claimed third switching transistor and sampling capacitor; they are directly connected to each other at Yu’s fifth node n5, a node connected to the gate electrode only through C2, n1 and T1.
Claim 1
Regarding claim 1, Yu discloses a display panel [e.g., Paragraph 45: The display panel 100 includes a pixel array that displays an input image on a screen; Fig. 1: 100; Fig. 5: pixel circuit], comprising:
a light-emitting element [e.g., Fig. 5: EL; Paragraph 94: The light emitting element EL may be implemented as an OLED];
a driving transistor [e.g., Fig. 5: DT; Paragraph 96: The driving element DT includes a first gate electrode connected to the second node n2, a second gate electrode connected to the fourth node n4, a first electrode connected to the first node n1, and a second electrode connected to the third node n3] for driving the light-emitting element [e.g., Paragraph 117: current is supplied to the light emitting element EL according to the gate-source voltage Vgs of the driving element DT];
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a first switching transistor [e.g., Fig. 5: T3] configured to be switched to apply an initialization voltage [e.g., Fig. 5: Vinit] to each of
a first electrode of the light-emitting element [e.g., Fig. 5: n4; Paragraph 94: The anode electrode of the light emitting element EL may be connected to a fourth node n4; Paragraph 99: The third switch element T3 is turned on in response to the gate-on voltage VGH of the first scan pulse SC1 and supplies the initialization voltage Vinit to the fourth node n4] and
a gate electrode of the driving transistor [e.g., Fig. 5: n2; Paragraph 106: in the initialization step IN1T, the initialization voltage Vinit is applied to the first gate of the driving element DT through the anode electrode of the light emitting element EL and the first capacitor C1];
a second switching transistor [e.g., Fig. 5: T6] configured to be switched to apply a sampling voltage [e.g., Fig. 5: Vref; Paragraph 104: the threshold voltage Vth’ of the driving element DT is sampled by applying the reference voltage Vref to the third node n3 in the sampling step SMPL] different from a data voltage [e.g., Fig. 5: Vdata; Paragraph 88: A voltage relationship commonly applied to the pixels may be set as
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VDD>Vref>Vinit>VSS. The data voltage Vdata may be generated as a gamma compensation voltage selected according to the gray scale of the pixel data from the data driver 110 in a voltage range lower than the pixel driving voltage VDD and higher than the low-potential power supply voltage VSS; Paragraph 104: the data voltage Vdata is applied to the first node n1 in the addressing step ADDR, so that the sampling step SMPL and the addressing step ADDR can be separated] to a first electrode of the driving transistor [e.g., Fig. 5: n3; Paragraph 102: The sixth switch element T6 is turned on in response to the gate-on voltage VGH of the second scan pulse SC2 and supplies the reference voltage Vref to the third node n3, in the sampling step SMPL; Paragraph 106: In the sampling step SMPL, the reference voltage Vref lower than the pixel driving voltage VDD is applied to the second electrode of the driving element DT]; and
a third switching transistor [e.g., Fig. 5: T7] and
a sampling capacitor [e.g., Fig. 5: C2; Paragraph 95: A second capacitor C2 is connected between a first node n1 and a fifth node n5. The second capacitor C2 transfers the reference voltage Vref and the data voltage Vdata to the first node n1] directly connected to each other [e.g., Fig. 5: n5; Paragraph 103: The seventh switch element T7 includes a first electrode connected to the fifth node n5, a second electrode connected to the third node n3, and a gate electrode to which the second scan pulse SC2 is applied] between the gate electrode and the first electrode of the driving transistor [e.g., Fig. 5: n2, T1, n1, C2, n5, T7, n3; Paragraph 97: The first switch element T1 includes a first electrode connected to the first node n1, a second electrode connected to the second node n2; Paragraph 103: When the seventh switch element T7 is turned on, the reference voltage Vref is applied to the fifth node n5, and the reference voltage Vref is applied to the first node n1 through the second capacitor C2],
wherein the third switching transistor and the sampling capacitor are directly connected to each other at a given node [e.g., Fig. 5: 115] that is not directly connected to the gate electrode of the driving transistor [e.g., Fig. 5: n5 reaches n2 only through C2, n1 and T1; Paragraph 95: A second capacitor C2 is connected between a first node n1 and a fifth node n5; Paragraph 97: The first switch element T1 is turned on in response to the gate-on voltage VGH of the first scan pulse SC1 and connects the first node n1 and the second node n2] (e.g., see Paragraphs 87-118).
In the alternative: should it be shown that Yu discloses a third switching transistor and a sampling capacitor directly connected to each other between the gate electrode and the first electrode of the driving transistor, wherein the third switching transistor and the sampling capacitor are directly connected to each other at a given node that is not directly connected to the gate electrode of the driving transistor with insufficient specificity -- that is, if Yu’s T7 and C2 are held not to lie between the gate electrode and the first electrode because Yu’s T1 intervenes on that path –
Choi discloses a third switching transistor and a sampling capacitor directly connected to each other between the gate electrode and the first electrode of the driving transistor: a compensation transistor M5 and a capacitor C2 disposed in series between the gate electrode N1 and the first electrode N2 of the drive transistor M2 [e.g., Choi, Fig. 3: 144, M5, C2, N1, N3, N2; Paragraph 51: The compensation unit 144 includes a fifth transistor (M5) (e.g., a compensation transistor) and a second capacitor (C2), which are disposed in series between the first node (N1) and the second node (N2); Paragraph 52: A first electrode of the fifth transistor (M5) is coupled to the first node (N1), and its second electrode is coupled to a terminal (i.e., a third node (N3)) of the second capacitor (C2); Paragraph 53: The second capacitor (C2) is formed between the third node (N3) and the second node (N2)] [e.g., Choi, Paragraph 47: The gate
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electrode of the second transistor (M2) is coupled to the first node (N1), and its first electrode is coupled to a second electrode (i.e., a second node (N2)) of the third transistor (M3)],
wherein the third switching transistor and the sampling capacitor are directly connected to each other at a given node N3 that is not directly connected to the gate electrode of the driving transistor -- the compensation transistor M5 lies between N3 and the gate node N1 [e.g., Choi, Fig. 3: N3 between M5 and C2; Paragraph 52: its second electrode is coupled to a terminal (i.e., a third node (N3)) of the second capacitor (C2)].
Choi is analogous art: the same field of endeavor as the claimed invention and as Yu (active-matrix organic light-emitting pixel circuits with in-pixel compensation), and reasonably pertinent to controlling the gate voltage of the driving transistor relative to the voltage at its first electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add Choi’s compensation unit -- a compensation transistor and a capacitor directly connected in series between the gate electrode and the first electrode of the driving transistor -- to Yu’s pixel circuit between Yu’s second node n2 and third node n3, because Choi teaches that such a unit controls the voltage of the gate electrode through charge sharing between the storage and compensation capacitors [e.g., Choi, Paragraph 61: When the fifth transistor (M5) is turned on, charges stored at the first capacitor (C1) and the second capacitor (C2) are shared between the capacitors] so that the pixel compensates for the deterioration of the OLED and supplies more current for the same data signal as the OLED ages [e.g., Choi, Paragraph 63: it is possible to compensate for the deterioration of the OLED since a voltage of the gate electrode of the second transistor (M2) decreases to correspond to the deterioration of the OLED].
Yu’s pixel already provides the OLED, the driving transistor, the gate node n2 and the first-electrode node n3 between which Choi’s unit is inserted, and the unit performs the same function in the combination as it does in Choi.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Claim 4
Regarding claim 4, Yu discloses the sampling capacitor [e.g., Fig. 5: C2] connected to the first electrode of the driving transistor [e.g., Fig. 5: n5-T7-n3; Paragraph 103: The seventh switch element T7 is turned on in response to the gate-on voltage VGH of the second scan pulse SC2 and connects the fifth node n5 to the third node n3, in the sampling step SMPL], is configured to store the sampling voltage [e.g., Paragraph 95: The second capacitor C2 transfers the reference voltage Vref and the data voltage Vdata to the first node n1; Paragraph 113: the sixth and seventh switch elements T6 and T7 are turned on and thereby the reference voltage Vref is applied to the third and fifth nodes n3 and n5].
In the alternative (Yu in view of Choi as applied to claim 1): the sampling capacitor is Choi’s second capacitor C2 as combined, which is connected to the first electrode of the driving transistor [e.g., Choi, Fig. 3: C2, N2; Paragraph 53: The second capacitor (C2) is formed between the third node (N3) and the second node (N2)] -- in the combination, to Yu’s third node n3, the electrode to which Yu applies the reference voltage [e.g., Yu, Paragraph 102: supplies the reference voltage Vref to the third node n3, in the sampling step SMPL] -- and is configured to store the voltage at its node [e.g., Choi, Paragraph 53: The second capacitor (C2) is charged with a voltage (e.g., a predetermined voltage) to compensate for the deterioration of the OLED]; same rationale as claim 1.
Claim 6
Regarding claim 6, Yu discloses a fourth switching transistor [e.g., Fig. 5: T1] is connected to and disposed between the gate electrode and a second electrode of the driving transistor [e.g., Fig. 5: n2, n1; Paragraph 97: The first switch element T1 includes a first electrode connected to the first node n1, a second electrode connected to the second node n2], and
wherein a fifth switching transistor [e.g., Fig. 5: T5] is connected to the second electrode of the driving transistor [e.g., Fig. 5: n1; Paragraph 101: The fifth switch element T5 includes a first electrode connected to the first power line VDDL to which the pixel driving voltage VDD is applied, a second electrode connected to the first node n1].
The alternative ground (Yu in view of Choi) does not alter this mapping: in it the third switching transistor and sampling capacitor are Choi’s M5 and C2 as combined, so Yu’s T1 and T5 remain distinct from the third switching transistor.
Claim 8
Regarding claim 8, Yu discloses a sixth switching transistor [e.g., Fig. 5: T2] is connected to and disposed between the light-emitting element and the driving transistor [e.g., Fig. 5: n3, n4; Paragraph 98: The second switch element T2 includes a first electrode connected to the third node n3, a second electrode connected to the fourth node n4; Paragraph 98: forms a current path between the driving element DT and the light emitting element EL], and
wherein a seventh switching transistor [e.g., Fig. 5: T7] is connected to and disposed between the sixth switching transistor and the driving transistor [e.g.,
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Fig. 5: T7 at n3, the node joining T2 and DT; Paragraph 103: The seventh switch element T7 includes a first electrode connected to the fifth node n5, a second electrode connected to the third node n3].
The alternative ground does not alter this mapping (Yu’s T2 and T7 remain distinct from Choi’s M5 as combined).
Claim 9
Regarding claim 9, Yu discloses the seventh switching transistor is configured to receive the data voltage at a first electrode of the seventh switching transistor [e.g., Fig. 5: n5; Paragraph 100: The fourth switch element T4 is turned on in response to the gate-on voltage VGH of the third scan pulse SC3 and supplies the data voltage Vdata to the fifth node n5, in the addressing step ADDR; Paragraph 103: The seventh switch element T7 includes a first electrode connected to the fifth node n5],
wherein a first electrode of the sixth switching transistor is connected to a second electrode of the seventh switching transistor [e.g., Fig. 5: n3; Paragraph 98: The second switch element T2 includes a first electrode connected to the third node n3; Paragraph 103: a second electrode connected to the third node n3],
wherein the seventh switching transistor is configured to receive an n-th second scan signal at a gate electrode of the seventh switching transistor [e.g., Fig. 5: SC2; Paragraph 103: a gate electrode to which the second scan pulse SC2 is applied],
wherein the sixth switching transistor is configured to receive an (n-2)-th light-emission signal at a gate electrode of the sixth switching transistor [e.g., Fig. 5: EM2; Paragraph 98: a gate electrode to which the second EM pulse EM2 is applied],
wherein the first electrode of the light-emitting element is connected to a second electrode of the sixth switching transistor [e.g., Fig. 5: n4; Paragraph 98: a second electrode connected to the fourth node n4], and wherein each n is a natural number. The alternative ground does not alter this mapping.
Claim Rejections - 35 USC § 103
Claim 2 is rejected under 35 U.S.C. § 103 as being unpatentable over Yu in view of Kim (US 10,964,264 B1);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Yu in view of Choi as applied to claim 1 above, and further in view of Kim.
Claim 2
Regarding claim 2, Yu discloses the first switching transistor is an N-type thin-film transistor [e.g., Paragraph 39: the transistors of the pixel circuit and the gate driving circuit are implemented as the n-channel oxide TFTs],
wherein the first switching transistor is configured to receive the initialization voltage at a first electrode of the first switching transistor [e.g., Fig. 5: T3, INL; Paragraph 99: The third switch element T3 includes a first electrode connected to the second power line INL to which the initialization voltage Vinit is applied],
wherein the first electrode of the light-emitting element is connected to a second electrode of the first switching transistor [e.g., Fig. 5: n4; Paragraph 99: a second electrode connected to the fourth node n4; Paragraph 94: The anode electrode of the light emitting element EL may be connected to a fourth node n4],
wherein the first switching transistor is configured to receive at a gate electrode of the first switching transistor [e.g., Paragraph 99: a gate electrode to which the first scan pulse SC1 is applied], and wherein n is a natural number.
Yu does not expressly disclose that the signal applied to the gate electrode of the first switching transistor is a light-emission signal of another row rather than a scan pulse.
Nor does Choi, in the alternative branch: Choi’s resetting transistor M4 is gated by the first control line CS1n [e.g., Choi, Paragraph 49: A gate electrode of the fourth transistor (M4) (e.g., a resetting transistor) is coupled to a first control line (CS1n)] or by the (n-1)th scan line [e.g., Choi, Paragraph 72: coupled to the (n-1)th scan line (Sn-1) and the (n+1)th light emitting control line (En+1)], not by a light-emission signal, and Choi is applied only for its compensation unit.
Kim teaches a pixel driving circuit whose initialization switching circuit is turned on by the emission signal of the preceding row to initialize the driving transistor [e.g., Kim, Column 24, lines 18-23: A first switching circuit of the pixel driving circuit according to an aspect of the present disclosure is turned on by the emission signal EM(n-1) applied to the (n-1)th subpixel to initialize the gate and drain of the driving transistor DT5 and compensate for the threshold voltage of the driving transistor DT5] [e.g., Kim, Column 24, lines 31-33: The fifty-first transistor T51 is turned on by the emission signal EM(n-1) applied to the (n-1)th subpixel to provide the initialization voltage Vini to the first node A].
Kim is analogous art: the same field of endeavor (electroluminescent pixel driving circuits with initialization and threshold-voltage compensation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to gate Yu’s initialization switch element T3 -- in either branch -- with the emission signal of a preceding row, as Kim teaches for its initialization transistors, because Kim teaches that reusing the emission signal of the preceding row for initialization reduces the bezel by simplifying the gate driving circuitry and improving the integration of the pixel driving circuit [e.g., Kim, Column 2, lines 10-15: The present disclosure provides an electroluminescent display panel including a pixel driving circuit having reduced bezel BZ by at least one of improving the degree of integration of the pixel driving circuit composed of a plurality of transistors, diversifying the types of the transistors, and simplifying circuits included in a gate driving circuit]; substituting one known gate-timing source for another yields the predictable result of turning on T3 during the initialization period.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claims 3 and 7 are rejected under 35 U.S.C. § 103 as being unpatentable over Yu in view of Rha et al (US 2019/0147796 A1);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Yu in view of Choi as applied to claims 1 and 6 above, and further in view of Rha.
Claim 3
Regarding claim 3, Yu discloses the second switching transistor is a P-type thin-film transistor [e.g., Paragraph 39: Transistors may be implemented as oxide thin film transistors (oxide TFTs) including an oxide semiconductor, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, or the like],
wherein the second switching transistor is configured to receive the sampling voltage at a first electrode of the second switching transistor [e.g., Fig. 5: T6, REFL; Paragraph 102: The sixth switch element T6 includes a first electrode connected to the third power line REFL to which the reference voltage Vref is applied],
wherein the first electrode of the driving transistor is connected to a second electrode of the second switching transistor [e.g., Fig. 5: n3; Paragraph 102: a second electrode connected to the third node n3],
wherein the second switching transistor is configured to receive an (n-1)-th scan signal at a gate electrode of the second switching transistor [e.g., Fig. 5: SC2; Paragraph 102: a
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gate electrode to which the second scan pulse SC2 is applied], and wherein n is a natural number.
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Yu does not expressly disclose that the second switching transistor is a P-type thin-film transistor; Yu describes its pixel transistors as n-channel oxide TFTS while stating that the disclosure is not limited to that example and that LTPS TFTS may be used [e.g., Yu, Paragraph 39: the transistors of the pixel circuit and the gate driving circuit are implemented as the n-channel oxide TFTs, but the present disclosure is not limited thereto].
Nor does Choi, in the alternative branch: Choi does not state the conductivity type of its transistors, has no reference-voltage switch, and is applied only for its compensation unit.
Rha teaches, in an OLED pixel of the same kind, implementing the switching TFTs that are not connected to the gate of the driving TFT as LTPS TFTs of a PMOS type, and the gate-connected switching TFTS as oxide NMOS TFTS [e.g., Rha, Paragraph 81: some TFTS connected to the gate electrode of the driving TFT DT among switching TFTs (T1-T5) may be implemented by oxide TFTS of a NMOS type having good off-current characteristics, and the remaining TFTS may be implemented as LTPS TFTS of a PMOS type having good response characteristics].
Rha is analogous art (the same field of endeavor -- electroluminescent pixel circuits with threshold-voltage sampling).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Yu’s reference-voltage switch element T6, which is connected to the source node n3 and not to the gate of the driving transistor, as a P-type LTPS TFT while retaining oxide NMOS TFTS for the gate-connected switch elements -- in either branch -- because Rha teaches that the PMOS LTPS TFTS provide good response characteristics and the oxide NMOS TFTs provide good off-current characteristics at the gate node: a known division of transistor types applied according to each switch’s position in the pixel, with predictable results.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claim 7
Regarding claim 7, Yu discloses the fourth switching transistor is an N-type thin-film transistor [e.g., Paragraph 39: the transistors of the pixel circuit and the gate driving circuit are implemented as the n-channel oxide TFTs],
wherein the second electrode of the driving transistor is connected to a first electrode of the fourth switching transistor [e.g., Fig. 5: n1, T1; Paragraph 97: The first switch element T1 includes a first electrode connected to the first node n1],
wherein the gate electrode of the driving transistor is connected to a second electrode of the fourth switching transistor [e.g., Fig. 5: n2; Paragraph 97: a second electrode connected to the second node n2],
wherein the fourth switching transistor is configured to receive a first scan signal at a gate electrode of the fourth switching transistor [e.g., Fig. 5: SC1; Paragraph 97: a gate electrode to which the first scan pulse SC1 is applied],
wherein the fifth switching transistor is thin-film transistor [e.g.,
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Paragraph 39: Transistors may be implemented as oxide thin film transistors (oxide TFTs) including an oxide semiconductor, low temperature polysilicon (LTPS) TFTs including low
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temperature polysilicon, or the like],
wherein a potential driving voltage line is connected to a first electrode of the fifth switching transistor [e.g., Fig. 5: VDDL, T5; Paragraph 101: The fifth switch element T5 includes a first electrode connected to the first power line VDDL to which the pixel driving voltage VDD is applied],
wherein the second electrode of the driving transistor is connected to a second electrode of the fifth switching transistor [e.g., Fig. 5: n1; Paragraph 101: a second electrode connected to the first node n1],
wherein the fifth switching transistor is configured to receive an n-th light-emission signal at a gate electrode of the fifth switching transistor [e.g., Fig. 5: EMI; Paragraph 101: a gate electrode to which the first EM pulse EMI is applied], and wherein n is a natural number.
Yu does not expressly disclose that the fifth switching transistor is a P-type thin-film transistor.
Nor does Choi, in the alternative branch: Choi does not state the conductivity type of its transistors and is applied only for its compensation unit, which does not touch Yu’s fifth switch element T5.
Rha teaches implementing the switching TFTS not connected to the driving TFT’s gate -- including the emission-controlled switching TFT T2 between the high-potential power line and the driving TFT -- as PMOS LTPS TFTs [e.g., Rha, Paragraph 81: some TFTS connected to the gate electrode of the driving TFT DT among switching TFTs (T1-T5) may be implemented by oxide TFTs of a NMOS type having good off-current characteristics, and the remaining TFTs may be implemented as LTPS TFTs of a PMOS type having good response characteristics; Paragraph 87: The second switching TFT T2 is connected between the high potential power line 17 and the first node N1 and switched according to the nth emission signal EM(n)].
It would have been obvious, for the reasons given for claim 3, to implement Yu’s T5 -- the VDD switch on the first EM pulse, connected to n1 and not to the gate -- as a P-type LTPS TFT in either branch. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claim 5 is rejected under 35 U.S.C. § 103 as being unpatentable over Yu in view of Choi.
Claim 5
Regarding claim 5, Yu discloses the first electrode of the driving transistor is connected to a first electrode of the sampling capacitor [e.g., Fig. 5: n3-T7-n5 (C2); Paragraph 103: The seventh switch element T7 includes a first electrode connected to the fifth node n5, a second electrode connected to the third node n3; Paragraph 95: A second capacitor C2 is connected between a first node n1 and a fifth node n5],
wherein a first electrode of the third switching transistor is connected to a second electrode of the sampling capacitor [e.g., Fig. 5: n5; Paragraph 103: The seventh switch element T7 includes a first electrode connected to the fifth node n5],
wherein the third switching transistor is an N-type thin-film transistor [e.g., Paragraph 39: the transistors of the pixel circuit and the gate driving circuit are implemented as the n-channel oxide TFTs; Paragraph 52: All transistors formed in the circuit layer 12 may be implemented as n-channel oxide TFTs],
wherein a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor [e.g., Fig. 5: n4-T2-n3; Paragraph 99: a second electrode connected to the fourth node n4; Paragraph 98: The second switch element T2 includes a first electrode connected to the third node n3, a second electrode connected to the fourth node n4],
wherein the third switching transistor is configured to receive at a gate electrode of the third switching transistor [e.g., Fig. 5: SC2; Paragraph 103: a gate electrode to which the second scan pulse SC2 is applied], and wherein n is a natural number.
Yu does not expressly disclose that the signal applied to the gate electrode of the third switching transistor is a light-emission signal of another row; Yu gates its seventh switch element T7 with the second scan pulse SC2.
Choi teaches, in a pixel whose compensation unit is a compensation transistor and a capacitor in series between the gate electrode and the first electrode of the drive transistor [e.g., Choi, Paragraph 51: The compensation unit 144 includes a fifth transistor (M5) (e.g., a compensation transistor) and a second capacitor (C2), which are disposed in series between the first node (N1) and the second node (N2)],
that the compensation transistor is gated by the light emitting control line of an adjacent row [e.g., Choi, Fig. 6: M5, En+1; Paragraph 69: a fifth transistor (M5) is coupled to an (n+1)th light emitting control line (En+1)], and
that this arrangement drives the transistor stably and dispenses with dedicated control lines [e.g., Choi, Paragraph 71: the fifth transistor (M5) may be stably driven when it is coupled to the (n+1)th light emitting control line (En+1); Paragraph 72: can be driven without using the control lines (CS11 to CS1n, CS21 to CS2n), compared to the pixel 140 as shown in FIG. 3].
Choi is analogous art for the reasons given for claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to gate Yu’s seventh switch element T7 -- the switch in series with the second capacitor C2 on the gate-to-first-electrode path -- with a light-emission signal of another row, as Choi gates its series compensation transistor M5 with the light emitting control line En+1, because Choi teaches that doing so drives the transistor stably and eliminates a dedicated control line and its driver; the ordinal of the light-emission signal is a labeling convention (n is any natural number), so a light-emission signal of an adjacent row is the (n-2)-th light-emission signal for the appropriate n.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Where claim 1 is read on Yu in view of Choi (the alternative branch above), the third switching transistor is Choi’s compensation transistor M5 as combined, which Choi itself gates by the light emitting control line En+1 for the same reasons;
its first electrode is coupled to the second capacitor C2 at N3 [e.g., Choi, Paragraph 52: its second electrode is coupled to a terminal (i.e., a third node (N3)) of the second capacitor (C2)],
C2 is coupled to the first electrode of the drive transistor at N2 [e.g., Choi, Paragraph 53: The second capacitor (C2) is formed between the third node (N3) and the second node (N2)],
its gate-side electrode sits at Yu’s n2, which is connected to Yu’s T3 through the first capacitor C1 [e.g., Yu, Paragraph 95: A first capacitor C1 is connected between a second node n2 and the fourth node n4], and
it is formed as an N-type TFT in Yu’s all-n-channel oxide circuit layer [e.g., Yu, Paragraph 52: All transistors formed in the circuit layer 12 may be implemented as n-channel oxide TFTs].
Claims 10-13 are rejected under 35 U.S.C. § 103 as being unpatentable over Yu in view of Kim;
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Yu in view of Choi and Kim.
Claim 10
Regarding claim 10, Yu discloses a display device [e.g., Fig. 1; Paragraph 44: a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100], comprising:
a display panel including: a light-emitting element; a driving transistor for driving the light-emitting element; a first switching transistor configured to be switched to apply an initialization voltage to each of a first electrode of the light-emitting element and a gate electrode of the driving transistor; a second switching transistor configured to be switched to apply a sampling voltage to a first electrode of the driving transistor; and a third switching transistor and a sampling capacitor directly connected to each other between the gate electrode and the first electrode of the driving transistor [e.g., Fig. 5: EL, DT, T3, T6, T7, C2, n2, n3, n5; Paragraph 94: The light emitting element EL may be implemented as an OLED; Paragraph 99: supplies the initialization voltage Vinit to the fourth node n4; Paragraph 106: the initialization voltage Vinit is applied to the first gate of the driving element DT through the anode electrode of the light emitting element EL and the first capacitor C1; Paragraph 102: supplies the reference voltage Vref to the third node n3, in the sampling step SMPL; Paragraph 103: The seventh switch element T7 includes a first electrode connected to the fifth node n5, a second electrode connected to the third node n3; Paragraph 95: A second capacitor C2 is connected between a first node n1 and a fifth node n5] (each element exactly as applied to claim 1 above, the disclosure of which is incorporated here);
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a light-emission driver [e.g., Fig. 1: 120; Paragraph 63: The second gate driver 122 outputs the EM pulse in response to the start pulse and the shift clock from the timing controller 130, and sequentially shifts the EM pulse according to the shift clock] configured to supply a light-emission signal [e.g., Paragraph 99: a gate electrode to which the first scan pulse SC1 is applied];
a scan driver [e.g., Paragraph 63: The first gate driver 121 outputs the scan pulse in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan pulse according to the shift clock] configured to supply a scan signal to the second switching transistor [e.g., Fig. 5: SC2, T6; Paragraph 102: a gate electrode to which the second scan pulse SC2 is applied];
a data driver [e.g., Fig. 1: 110; Paragraph 60: The data driver 110 generates a data voltage by converting pixel data of an input image received as a digital signal from the timing controller 130] configured to supply a data voltage to a connection node of the light-emitting element and the driving transistor [e.g., Fig. 5: DL, T4, n5, T7, n3; Paragraph 93: The data voltage Vdata of the pixel data is supplied to the pixel circuit through a data line DL in synchronization with the third scan pulse SC3, in the addressing step ADDR; Paragraph 100: supplies the data voltage Vdata to the fifth node n5, in the addressing step ADDR; Paragraph 103: connects the fifth node n5 to the third node n3]; and
a controller [e.g., Fig. 1: 130; Paragraph 67: the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, MUX signals MUXI and MUX2 for controlling the operation timing of the de-multiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120] configured to control the light-emission driver, the scan driver, and the data driver,
wherein the third switching transistor and the sampling capacitor are directly connected to each other at a given node that is not directly connected to the gate electrode of the driving transistor [e.g., Fig. 5: n5; Paragraph 95: A second capacitor C2 is connected between a first node n1 and a fifth node n5; Paragraph 97: The first switch element T1 is turned on in response to the gate-on voltage VGH of the first scan pulse SC1 and connects the first node n1 and the second node n2] (as applied to claim 1) (e.g., see Paragraphs 44-118).
Yu does not expressly disclose that the light-emission driver supplies a light-emission signal to the first switching transistor: Yu’s third switch element T3 is gated by the first scan pulse SC1 from the first gate driver 121, not by an EM pulse from the second gate driver 122.
Nor does Choi, in the alternative branch: Choi’s resetting transistor M4 is gated by the first control line CS1n [e.g., Choi, Paragraph 49: A gate electrode of the fourth transistor (M4) (e.g., a resetting transistor) is coupled to a first control line (CS1n)] or by the (n-1)th scan line [e.g., Choi, Paragraph 72: coupled to the (n-1)th scan line (Sn-1) and the (n+1)th light emitting control line (En+1)], not by a light emitting control line, and Choi is applied only for its compensation unit.
Kim teaches gating the initialization switching circuit with the emission signal of the preceding row [e.g., Kim, Column 24, lines 18-23: A first switching circuit of the pixel driving circuit according to an aspect of the present disclosure is turned on by the emission signal EM(n-1) applied to the (n-1)th subpixel to initialize the gate and drain of the driving transistor DT5 and compensate for the threshold voltage of the driving transistor DT5] [e.g., Kim, Column 24, lines 31-33: The fifty-first transistor T51 is turned on by the emission signal EM(n-1) applied to the (n-1)th subpixel to provide the initialization voltage Vini to the first node A], for the reduced bezel that follows from simplified gate driving circuitry and improved integration [e.g., Kim, Column 2, lines 10-15: The present disclosure provides an electroluminescent display panel including a pixel driving circuit having reduced bezel BZ by at least one of improving the degree of integration of the pixel driving circuit composed of a plurality of transistors, diversifying the types of the transistors, and simplifying circuits included in a gate driving circuit].
Kim is analogous art for the reasons given for claim 2.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, in either branch, to supply Yu’s T3 from the second gate driver 122 -- the light-emission driver -- with the emission signal of a preceding row, for the reasons given for claim 2. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
In the alternative (Yu in view of Choi and Kim): should it be shown that Yu discloses the third switching transistor and sampling capacitor of claim 10 with insufficient specificity,
Choi discloses a compensation transistor and a capacitor disposed in series between the gate electrode and the first electrode of the drive transistor, directly connected to each other at a node N3 that is not directly connected to the gate electrode [e.g., Choi, Fig. 3: 144, M5, C2, N1, N3, N2; Paragraph 51: The compensation unit 144 includes a fifth transistor (M5) (e.g., a compensation transistor) and a second capacitor (C2), which are disposed in series between the first node (N1) and the second node (N2); Paragraph 52: A first electrode of the fifth transistor (M5) is coupled to the first node (N1), and its second electrode is coupled to a terminal (i.e., a third node (N3)) of the second capacitor (C2); Paragraph 53: The second capacitor (C2) is formed between the third node (N3) and the second node (N2)], for the reasons and with the motivation given for claim 1 above.
Claim 11
Regarding claim 11, Yu discloses during a first period [e.g., Fig. 6: IN1T; Paragraph 111: in the initialization step IN1T, the first switch element T1 and the fifth switch element T5 are turned on], to turn on the first switching transistor [e.g., Paragraph 111: In the initialization step IN1T, the third switch element T3 is also turned on],
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wherein responsive to the first switching transistor being turned on, the first switching transistor is configured to apply the initialization voltage to each of the light-emitting element and the driving transistor to cause the first electrode of the light-emitting element and the gate electrode of the driving transistor to be initialized [e.g., Paragraph 111: the light emitting element EL is turned off because the initialization voltage Vinit lower than its threshold voltage is applied to the anode electrode; Paragraph 106: the initialization voltage Vinit is applied to the first gate of the driving element DT through the anode electrode of the light emitting element EL and the first capacitor C1], and wherein n is a natural number.
Yu does not expressly disclose that the first switching transistor is turned on by an (n-2)-th light-emission signal applied by the light-emission driver (Yu turns T3 on with the first scan pulse SC1), and neither does Choi, for the reasons given for claim 10. Kim teaches turning the initialization transistor on with the emission signal of the (n-1)th subpixel to provide the initialization voltage during the initialization period [e.g., Kim, Column 24, lines 31-33: The fifty-first transistor T51 is turned on by the emission signal EM(n-1) applied to the (n-1)th subpixel to provide the initialization voltage Vini to the first node A].
It would have been obvious, for the reasons given for claims 2 and 10, to turn Yu’s T3 on during Yu’s initialization step with the emission signal of a preceding row supplied by the second gate driver 122; the ordinal is a labeling convention.
KSR, 550 U.S.
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398; Graham, 383 U.S. 1.
Claim 12
Regarding claim 12, Yu discloses during a second period [e.g., Fig. 6: SMPL], the scan driver is configured to apply an (n-1)-th second scan signal to the second switching transistor to turn on the second switching transistor [e.g., Fig. 5: SC2, T6; Paragraph 113: In the sampling step SMPL, the sixth and seventh switch elements T6 and T7 are turned on and thereby the reference voltage Vref is applied to the third and fifth nodes n3 and n5],
wherein responsive to the second switching transistor being turned on, the second switching transistor is configured to apply the sampling voltage to the first electrode of the driving transistor [e.g., Paragraph 102: supplies the reference voltage Vref to the third node n3, in the sampling step SMPL] to cause the gate electrode of the driving transistor to be sampled based on a voltage obtained by adding the sampling voltage to a threshold voltage of the driving transistor [e.g., Paragraph 113: At this time, the voltage of the first node n1 is changed to Vref+Vth’, and the fourth node n4 maintains the initialization voltage Vinit. In the sampling step SMPL, the threshold voltage Vth’ of the driving element DT is sampled and stored in the first capacitor C1; Paragraph 97: When the first switch element T1 is turned on, the driving element DT operates as a diode because the first gate electrode G1 and the first electrode are connected], and wherein n is a natural number.
Neither Kim nor, in the alternative branch, Choi is relied upon for any feature of this claim; the rejection of claim 12 rests on Yu’s disclosure and on the rejection of claim 10 from which it depends.
Claim 13
Regarding claim 13, Yu discloses the sampling capacitor connected to the first electrode of the driving transistor, is configured to store the sampling voltage [e.g., Fig. 5: C2, n5, T7, n3; Paragraph 103: When the seventh switch element T7 is turned on, the reference voltage Vref is applied to the fifth node n5, and the reference voltage Vref is applied to the first node n1 through the second capacitor C2; Paragraph 95: The second capacitor C2 transfers the reference voltage Vref and the data voltage Vdata to the first node n1] (as applied to claim 4).
In the alternative branch the sampling capacitor is Choi’s second capacitor C2 as combined, connected to the first electrode of the drive transistor [e.g., Choi, Paragraph 53: The second capacitor (C2) is formed between the third node (N3) and the second node (N2)] and charged with the voltage at its node [e.g., Choi, Paragraph 53: The second capacitor (C2) is charged with a voltage (e.g., a predetermined voltage) to compensate for the deterioration of the OLED], as applied to claim 4.
Claims 14 and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over Yu in view of Kim as applied to claim 13 above, and further in view of Park et al (US 2023/0116559 A1);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Yu in view of Choi and Kim as applied to claim 13 above, and further in view of Park.
Claim 14
Regarding claim 14, Yu discloses a fourth switching transistor [e.g., Fig. 5: T4] is connected to the first electrode of the driving transistor [e.g., Fig. 5: n5-T7-n3; Paragraph 100: The fourth switch element T4 includes a first electrode connected to the fifth node n5, a second electrode connected to the data line DL to which the data voltage Vdata of pixel data is applied, and a gate electrode to which the third scan pulse SC3 is applied],
wherein during a third period [e.g., Fig. 6: ADDR], the scan driver is configured to apply an n-th second scan signal to the fourth switching transistor to turn on the fourth switching transistor [e.g., Fig. 5: SC3; Paragraph 100: The fourth switch element T4 is turned on in response to the gate-on voltage VGH of the third scan pulse SC3 and supplies the data voltage Vdata to the fifth node n5, in the addressing step ADDR], and
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wherein responsive to the fourth switching transistor being turned on, the driving transistor is configured to receive the data voltage [e.g., Paragraph 104: the data voltage Vdata is applied to the first node n1 in the addressing step ADDR; Paragraph 106: In the sampling step SMPL, the reference voltage Vref lower than the pixel driving voltage VDD is applied to the second electrode of the driving element DT and applied to the first electrode of the driving element DT through the second capacitor C2].
Yu does not expressly disclose that the driving transistor receives the data voltage at the first electrode of the driving transistor: Yu applies the data voltage, through the fourth switch element T4 and the second capacitor C2, to the first node n1 rather than to the electrode at the third node n3 that receives the reference voltage.
Kim, applied to claims 10-13 for the emission-gated initialization switch, does not teach it either -- Kim’s data voltage Vdata is applied through a scan-gated transistor to a capacitor node rather than to the electrode that receives a separate sampling voltage; and, in the alternative branch, Choi does not teach it -- Choi’s data signal is supplied to the gate node N1 through the first transistor M1 [e.g., Choi, Paragraph 46: A second electrode of the first transistor (M1) is coupled to a gate electrode (i.e., a first node (N1)) of the second transistor (M2)], and Choi is applied only for its compensation unit.
Park teaches a pixel in which the data signal and a second, different voltage are each applied to the same electrode of the driving transistor through separate switching transistors: the write transistor T2 supplies the data signal DS to the first node N1, which is the source of the driving transistor T1 [e.g., Park, Fig. 4: T2, N1; Paragraph 81: A source of the driving transistor T1 may be connected to the first node N1; Paragraph 83: A source of the write transistor T2 may receive the data signal DS, a drain of the write transistor T2 may be connected to the first node N1], and
the bias transistor T8 supplies the bias voltage VEH to that same first node N1 [e.g., Park, Fig. 4: T8, N1; Paragraph 90: A source of the bias transistor T8 may receive the bias voltage VEH, a drain of the bias transistor T8 may be connected to the first node N1; Paragraph 91: The bias transistor T8 may be turned on when the bypass gate signal GB is provided so as to transmit the bias voltage VEH to the source of the driving transistor T1].
Park is analogous art (the same field -- OLED pixel circuits applying a bias voltage to the source of the driving transistor to compensate hysteresis).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, in either branch, to connect Yu’s data switch element T4 so that the data voltage is delivered to the third node n3 -- the same electrode that receives the reference voltage from T6 -- as Park delivers both its data signal and its bias voltage to the single source node N1 through separate switches, because Park teaches that applying both voltages to the source electrode of the driving transistor through separate transistors on-biases the driving transistor and compensates its hysteresis [e.g., Park, Paragraph 91: As the bias voltage VEH is applied to the source of the driving transistor T1, the driving transistor T1 may be on-biased, and a hysteresis of the driving transistor T1 may be compensated for], and because delivering the data voltage to the node already provided with a switched voltage path is a known arrangement yielding the predictable result of writing the data voltage onto the same electrode.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claim 15
Regarding claim 15, Yu discloses the driving transistor is configured to receive, at the gate electrode of the driving transistor, a voltage obtained by subtracting the sampling voltage from the data voltage [e.g., Paragraph 117: the voltage of the second node n2 applied to the first gate electrode of the driving element DT is Vref+Vth’+C’(Vdata-Vref) +Vel; Paragraph 118: In the light emission step EMIS, current Ioled flowing through the light emitting element EL is] (the gate voltage includes the term (Vdata-Vref), the data voltage less the reference voltage, scaled by the capacitance ratio C’; Paragraph 118 gives the emission current as a function of the same (Vdata-Vref) term).
Claim Rejections - 35 USC § 102
Claims 1, 3, 6, 10, 12 and 13 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Rha.
Construction stated for this ground. Rha’s own designations are followed: the first electrode of the driving transistor is the electrode at Rha’s first node N1 [e.g.,
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Paragraph 84: The driving TFT DT includes a gate electrode connected to a second node N2, a first electrode connected to a first node N1, and a second electrode connected to a third node N3].
The data voltage is Rha’s data voltage Vx; the sampling voltage is the different data voltage Vy applied in Rha’s second sampling period.
The second switching TFT T2 and the storage capacitor Cst are read as the claimed third switching
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transistor and sampling capacitor; they are directly connected to each other at the node
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of the high potential power line 17, a node connected to the gate electrode N2 only
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through Cst. This ground does not rely on the mapping of the final rejection (T3 and Cst
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at N2), which Applicant’s remarks address; it is a separate and independent ground
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from the rejections over Yu above.
Claim 1
Regarding claim 1, Rha discloses a display panel [e.g., Fig. 1; Fig. 2; Fig. 7], comprising:
a light-emitting element [e.g., Fig. 7: OLED; Paragraph 83: The OLED is a device which emits light according to the driving current input from the driving TFT DT];
a driving transistor [e.g., Fig. 7: DT; Paragraph 84: The driving TFT DT is a device which generates the driving current flowing through the OLED according to a first gate-source voltage within a first period] for driving the light-emitting element;
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a first switching transistor [e.g., Fig. 7: T4, T5] configured to be switched to apply an initialization voltage [e.g., Fig. 7: Vinit] to each of a first electrode of the light-emitting element [e.g., Fig. 7: N4; Paragraph 90: The fifth switching TFT T5 is connected between the fourth node N4 and the initializing power line 16] and a gate electrode of the driving transistor [e.g., Fig. 7: N2; Paragraph 89: The fourth switching TFT T4 is connected between the second node N2 and the initializing power line 16];
a second switching transistor [e.g., Fig. 7: T1] configured to be switched to apply a sampling voltage [e.g., Fig. 9E: Vy; Paragraph 111: The second sampling period SP2 is for setting the second gate-source voltage Vgs2 of the driving TFT DT based on a data voltage Vx and another data voltage Vy (which is the data voltage applied to another pixel), in order to compensate for the hysteresis phenomenon of the driving TFT DT; Paragraph 112: the threshold voltage of the driving TFT DT is sampled and stored at the second node N2 and the third node N3. That is, the potential of the second node N2 and the third node N3 becomes (Vy-Vth)] different from a data voltage [e.g., Fig. 9B: Vx; Paragraph 99: The potential of the first node N1 is changed into a data voltage Vx due to the turning on of the first switching TFT T1] to a first electrode of the driving transistor [e.g., Fig. 7: N1; Paragraph 86: a second electrode of the first switch T1 is connected to the first node N1; Paragraph 112: The potential of the first node N1 is changed intro a data voltage Vy owing to the turning on of the first switching TFT T1]; and
a third switching transistor [e.g., Fig. 7: T2] and a sampling capacitor [e.g., Fig. 7: Cst] directly connected to each other [e.g., Fig. 7: 17; Paragraph 87: a first electrode of the second switching TFT T2 is connected to the high potential power line 17, and a second electrode of the second switching TFT T2 is connected to the first node N1; Paragraph 91: The storage capacitor Cst is connected between the high potential power line 17 and the second node N2] between the gate electrode and the first electrode of the driving transistor [e.g., Fig. 7: N2, Cst, 17, T2, N1],
wherein the third switching transistor and the sampling capacitor are directly connected to each other at a given node [e.g., Fig. 7: the node of power line 17] that is not directly connected to the gate electrode of the driving transistor [e.g., Fig. 7: Cst intervenes between line 17 and N2; Paragraph 91: The storage capacitor Cst is connected between the high potential power line 17 and the second node N2] (e.g., see Paragraphs 80-114).
Claim 3
Regarding claim 3, Rha discloses the second switching transistor is a P-type thin-film transistor [e.g., Paragraph 81: The TFTs (T1-T5, ET, DT) may be implemented by low-temperature polycrystalline silicon (LTPS) TFTs of a PMOS type having good response characteristics],
wherein the second switching transistor is configured to receive the sampling voltage at a first electrode of the second switching transistor [e.g., Paragraph 86: a first electrode of the first switch T1 is connected to the data line 14],
wherein the first electrode of the driving transistor is connected to a second electrode of the second switching transistor [e.g., Paragraph 86: a second electrode of the first switch T1 is connected to the first node N1],
wherein the second switching transistor is configured to receive an (n-1)-th scan signal at a gate electrode of the second switching transistor [e.g., Paragraph 86: The gate electrode of the first switch T1 is connected to the nth first gate line 15a(n) to which the nth scan signal SC(n) is applied], and wherein n is a natural number.
Claim 6
Regarding claim 6, Rha discloses a fourth switching transistor [e.g., Fig. 7: T3] is connected to and disposed between the gate electrode and a second electrode of the driving transistor [e.g., Fig. 7: N2, N3; Paragraph 88: The third switching TFT T3 is connected between the second node N2 and the third node N3 and switched according to the nth scan signal SC(n)], and
wherein a fifth switching transistor [e.g., Fig. 7: ET] is connected to the second electrode of the driving transistor [e.g., Paragraph 85: a first electrode of the emission controlling TFT ET is connected to the third node N3].
Claim 10
Regarding claim 10, this claim is rejected for the reasons given for claim 1 of this ground; furthermore, Rha discloses a display device [e.g., Fig. 1] comprising the display panel;
a light-emission driver [e.g., Fig. 1: 13; Paragraph 44: a gate driver 13 for driving the gate lines 15 connected to the pixels PXL] configured to supply a light-emission signal to the first switching transistor [e.g., Fig. 7: SC(n-1) to T4; SC(n) to T5; Paragraph 89: switched according to an (n-1)th scan signal SC(n-1)] (the gate signal driving the initialization TFTs, read as the light-emission signal);
a scan driver [e.g., Fig. 1: 13] configured to supply a scan signal to the second switching transistor [e.g., Paragraph 86: The gate electrode of the first switch T1 is connected to the nth first gate line 15a(n) to which the nth scan signal SC(n) is applied]; a data driver [e.g., Fig. 1: 12; Paragraph 44: a source driver 12 for driving the data lines 14 connected to the pixels PXL] configured to supply a data voltage to a connection node of the light-emitting element and the driving transistor [e.g., Fig. 7: 14, T1, N1]; and
a controller [e.g., Fig. 1: 11; Paragraph 43: a timing controller 11 for controlling the driving circuits 12 and 13] configured to control the light-emission driver, the scan driver, and the data driver,
wherein the third switching transistor and the sampling capacitor are directly connected to each other at a given node that is not directly connected to the gate electrode of the driving transistor (as applied to claim 1 of this ground) (e.g., see Paragraphs 40-114).
Claim 12
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Regarding claim 12, Rha discloses during a second period [e.g., Fig. 8: SP2],
the scan driver is configured to apply an (n-1)-th second scan signal to the second switching transistor to turn on the second switching transistor [e.g., Paragraph 112: during the second sampling period SP2, the first, third and fifth switching TFTS T1, T3 and T5 are turned on in response to the nth scan signal SC(n) of the on level ON],
wherein responsive to the second switching transistor being turned on, the second switching transistor is configured to apply the sampling voltage to the first electrode of the driving transistor to cause the gate electrode of the driving transistor to be sampled based on a voltage obtained by adding the sampling voltage to a threshold voltage of the driving transistor [e.g., Paragraph 112: the threshold voltage of the driving TFT DT is sampled and stored at the second node N2 and the third node N3. That is, the potential of the second node N2 and the third node N3 becomes (Vy-Vth)] (the driving TFT is a PMOS device whose threshold voltage is negative, so Vy-Vth is Vy plus the magnitude of the threshold voltage), and wherein n is a natural number.
Claim 13
Regarding claim 13, Rha discloses the sampling capacitor connected to the first electrode of the driving transistor [e.g., Paragraph 87: a first electrode of the second switching TFT T2 is connected to the high potential power line 17, and a second electrode of the second switching TFT T2 is connected to the first node N1; Paragraph 91: The storage capacitor Cst is connected between the high potential power line 17 and the second node N2], is configured to store the sampling voltage [e.g., Paragraph 112: the threshold voltage of the driving TFT DT is sampled and stored at the second node N2 and the third node N3. That is, the potential of the second node N2 and the third node N3 becomes (Vy-Vth)].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
3 September 2026
Prosecution Insights