DETAILED ACTION
The Amendment filed August 27, 2026 has been entered. Claims 1-20 are pending. Claims 1, 13 and 20 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 9 rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2012/0033503) in view of Yu et al. (US 9,922,714).
Regarding independent claim 1, Kim et al. teach a method of operating a nonvolatile memory device that includes a plurality of memory blocks (FIG. 1 and para. 0050: the memory cell array 100 … a plurality of memory blocks MB), each of the plurality of memory blocks including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor which are connected in series and arranged in a vertical direction between each of a plurality of bit-lines and a common source line (see FIGS. 1-2) on and/or in a substrate (see FIGS. 14-15, and para. 0106: … a semiconductor substrate), the method comprising:
receiving an erase command and a block address designating a target memory block among the plurality of memory blocks (e.g., FIG. 3: S1000);
sensing an operating temperature of the nonvolatile memory device (S1100 and e.g., para. 0124: … the temperature detection …); and
adjusting an effective erase execution time interval of each of word-lines of the target memory block, respectively, based on the sensed operating temperature (see FIG. 4: Normal Erase and Modified Erase (Cold Temp), and accompanying disclosure, e.g., para. 0075-0078, i.e., adjusted erase loop based on Cold Temp),
wherein the vertical direction is perpendicular to an upper surface of the substrate (see FIGS. 14-15).
Kim’s erase execution time interval, which is adjusted based on temperature, does not clearly express the effective erase execution time.
However, erase pulse magnitude (claimed erase execution time interval) adjusted based on temperature is a well-known technology for a type of memory for its purpose1.
For support, of the above asserted facts, see for example, Yu et al. teach the deficiencies in e.g., FIGS. 12A-B: 1202: Generate erase pulse having a duration that depends on temperature; and FIGS. 13A-E, and accompanying disclosure, e.g., col. 25, line 31 through col. 26, line 63: … In one embodiment, the longer duration pulse is applied when the temperature is colder …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Yu et al. to the teaching of Kim et al. such that a flash memory, as taught by Kim et al., utilizes erase pulse magnitude, as taught by Yu et al., for the purpose of utilizing compensated erase pulse width based on temperature, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 2, Kim et al. and Yu et al. as combined, teach the limitations of claim 1.
Yu et al. teach erase distribution width of ones of the plurality of memory cells connected to the word-lines of the target memory block, generated by a change of the operating temperature is configured to be reduced by adjusting the effective erase execution time interval of each of the word-lines of the target memory block, respectively (e.g., FIGS. 12A-B and FIGS. 13A-E, and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Yu et al. for the same purpose of compensated erase pulse width based on temperature.
Regarding claim 9, Kim et al. and Yu et al. as combined, teach the limitations of claim 1.
Kim et al. further teach determining a temperature range of the sensed operating temperature among a plurality of temperature ranges (e.g., para. 0089: …the temperature detection … to a room temperature or a hot temperature).
Claims 13-14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2012/0033503) in view of Yu et al. (US 9,922,714).
Regarding independent claim 13, the device claim 13 is rejected for the same reason set forth above as applied to the method claim 1 as being unpatentable over Kim et al. and Yu et al. except for a digital temperature sensor configure to sense an operating temperature of the nonvolatile memory device, i.e., Kim’s temperature detecting sensors (e.g., para. 0061) do not explicitly disclose a digital temperature sensor.
However, a digital temperature sensor is a well-known technology for a type of flash memory for its purpose.
For support, of the above asserted facts, see for example, Chin et al. (US 11,705,203), e.g., col. 25, lines 43-52: … a digital temperature code ….
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Chin et al. to the teaching of Kim et al. such that a flash memory, as taught by Kim et al., utilizes a digital temperature sensor, as taught by Chin et al., for the purpose of utilizing digital value to the storage region, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 14, Kim et al. and Yu et al., as combined, teach the limitations of claim 13.
Kim et al. further teach a voltage generator configured to generate word-line voltages including an erase voltage, a word-line erase voltage, and an erase inhibit voltage based on control signals; and an address decoder configured to provide the word-line voltages to the target memory block based on a row address (FIG. 1 and accompanying disclosure; further it’s an inherent characteristic of memory device).
Allowable Subject Matter
Claims 3-8, 10-12 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
Response to Arguments
Applicant’s amendment filed 08/27/2026, with respect to the rejection(s) of claims under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection. Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Further see Oh et al. (US 9,437,310), FIGS. 21-22 and accompanying disclosure.
