Prosecution Insights
Last updated: October 02, 2026
Application No. 19/005,417

IMAGING ELEMENT

Non-Final OA §DP
Filed
Dec 30, 2024
Priority
Dec 27, 2017 — provisional 62/610,806 +5 more
Examiner
YODER III, CHRISS S
Art Unit
2638
Tech Center
2600 — Communications
Assignee
Sony Group Corporation
OA Round
2 (Non-Final)
75%
Grant Probability
Favorable
2-3
OA Rounds
11m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
520 granted / 692 resolved
+13.1% vs TC avg
Strong +22% interview lift
Without
With
+21.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
15 currently pending
Career history
708
Total Applications
across all art units

Statute-Specific Performance

§101
4.6%
-35.4% vs TC avg
§103
49.3%
+9.3% vs TC avg
§102
24.0%
-16.0% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 692 resolved cases

Office Action

§DP
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 29, 2026 has been entered. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Applicant's remarks with respect to claims 21-40 have been considered but are moot in view of the new ground(s) of rejection. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 21-25 and 28-35 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-5, 8-13, and 16 of U.S. Patent No. 11,798,972. Although the claims at issue are not identical, they are not patentably distinct from each other because: Application Patent 11,798,972 Claim 21 Claim 1 21. A light detecting device, comprising: a first substrate section including a first semiconductor substrate having a sensor pixel; a second substrate section including a second semiconductor substrate having a first circuit for outputting a pixel signal and a first through wiring line penetrating the second semiconductor substrate; and 1. A light detecting device, comprising: a first substrate section including a first semiconductor substrate having a sensor pixel; a second substrate section including a second semiconductor substrate having a first circuit for outputting a pixel signal; … an interlayer insulating film disposed between the first semiconductor substrate and the second semiconductor substrate, wherein a first through wiring line electrically coupling the first substrate section and the second substrate section is provided in the interlayer insulating film, … a third substrate section including a third semiconductor substrate having a second circuit for processing the pixel signal, … a third substrate section including a third semiconductor substrate having a second circuit for processing the pixel signal; and … wherein the first through wiring line electrically couples the first substrate section and the second substrate section, … wherein a first through wiring line electrically coupling the first substrate section and the second substrate section is provided in the interlayer insulating film, … wherein a first electrode in the second substrate section and a second electrode in the third substrate section are bonded to each other for electrically coupling the second substrate section and the third substrate section, and wherein, in a cross-sectional view, a width of the first through wiring line is narrower than at least one of a width of the first electrode or a width of the second electrode. … wherein a first electrode in the second substrate section and a second electrode in the third substrate section are bonded to each other for electrically coupling the second substrate section and the third substrate section, and wherein, in a cross-sectional view, a width of the first through wiring line is narrower than at least one of a width of the first electrode or a width of the second electrode. Claim 22 Claim 2 22. The light detecting device according to claim 21, wherein the sensor pixel includes a photoelectric converter, a transfer transistor, and a floating diffusion, the transfer transistor being electrically coupled to the photoelectric converter, and wherein the floating diffusion temporarily holds an electric charge output from the photoelectric converter via the transfer transistor. 2. The light detecting device according to claim 1, wherein the first substrate section includes a photoelectric converter, a transfer transistor, and a floating diffusion, the transfer transistor being electrically coupled to the photoelectric converter, and wherein the floating diffusion temporarily holds an electric charge outputted from the photoelectric converter via the transfer transistor. Claim 23 Claim 3 23. The light detecting device according to claim 22, wherein the sensor pixel is part of a plurality of sensor pixels, wherein the first substrate section includes the photoelectric converter, the transfer transistor, and the floating diffusion for each sensor pixel of the plurality of sensor pixels, and wherein the second substrate section includes the first circuit for each sensor pixel of the plurality of sensor pixels. 3. The light detecting device according to claim 2, wherein the sensor pixel is part of a plurality of sensor pixels, wherein the first substrate section includes the photoelectric converter, the transfer transistor, and the floating diffusion for each sensor pixel of the plurality of sensor pixels, and wherein the second substrate section includes the first circuit for each sensor pixel of the plurality of sensor pixels. Claim 24 Claim 4 24. The light detecting device according to claim 23, further comprising: isolation material that separates respective sensor pixels of the plurality of sensor pixels, wherein the isolation material penetrates through the first semiconductor substrate. 4. The light detecting device according to claim 3, further comprising isolation material that separates respective sensor pixels of the plurality of sensor pixels, wherein the isolation material penetrates through the first semiconductor substrate. Claim 25 Claim 5 25. The light detecting device according to claim 22, wherein the first through wiring line is electrically coupled to the floating diffusion. 5. The light detecting device according to claim 3, wherein the interlayer insulating film includes at least two of the first through wiring lines for each sensor pixel of the plurality of sensor pixels, … wherein, for each sensor pixel, a second one of the first through wiring lines is electrically coupled to the floating diffusion. Claim 28 Claim 8 28. The light detecting device according to claim 22, wherein the first substrate section further includes a gate wiring line that electrically couples a gate of the transfer transistor to the second circuit. 8. The light detecting device according to claim 3, wherein the first substrate section further includes a gate wiring line extending in a direction parallel to the first substrate section, and wherein a gate of the transfer transistor is electrically coupled to the second circuit via the gate wiring line. Claim 29 Claim 9 29. The light detecting device according to claim 23, wherein the first through wiring line is provided for each sensor pixel of the plurality of sensor pixels. 9. The light detecting device according to claim 3, wherein the first through wiring line is provided for each sensor pixel of the plurality of sensor pixels. Claim 30 Claim 10 30. The light detecting device according to claim 22, wherein the sensor pixel is part of a plurality of sensor pixels arranged in groups, wherein the first substrate section includes the photoelectric converter, the transfer transistor, and the floating diffusion for each sensor pixel of the plurality of sensor pixels, and wherein the second substrate section includes the first circuit for each group of sensor pixels. 10. The light detecting device according to claim 2, wherein the sensor pixel is part of a plurality of sensor pixels arranged in groups, wherein the first substrate section includes the photoelectric converter, the transfer transistor, and the floating diffusion for each sensor pixel of the plurality of sensor pixels, and wherein the second substrate section includes the first circuit for each group of sensor pixels. Claim 31 Claim 11 31. The light detecting device according to claim 30, wherein sensor pixels in each group of sensor pixels share their floating diffusions. 11. The light detecting device according to claim 10, wherein sensor pixels in each group of sensor pixels share their floating diffusions. Claim 32 Claim 12 32. The light detecting device according to claim 22, wherein a gate of the transfer transistor is electrically coupled to the second circuit via the first and second electrodes. 12. The light detecting device according to claim 2, wherein a gate of the transfer transistor is electrically coupled to the second circuit via the first and second electrodes. Claim 33 Claim 13 33. The light detecting device according to claim 21, wherein the second circuit includes silicide disposed in an impurity diffusion region in contact with a source electrode or a drain electrode. 13. The light detecting device according to claim 1, wherein the second circuit includes a silicide disposed in an impurity diffusion region in contact with a source electrode or a drain electrode. Claim 34 Claim 16 34. The light detecting device according to claim 21, wherein the first and second electrodes are formed of copper or aluminum. 16. The light detecting device according to claim 1, wherein the first and second electrodes are formed of copper or aluminum. Claim 35 Claim 1 35. An electronic apparatus, comprising: a signal processing circuit; and a light detecting device, comprising: a first substrate section including a first semiconductor substrate having a sensor pixel; a second substrate section including a second semiconductor substrate having a first circuit for outputting a pixel signal and a first through wiring line penetrating the second semiconductor substrate; and 1. A light detecting device, comprising: a first substrate section including a first semiconductor substrate having a sensor pixel; a second substrate section including a second semiconductor substrate having a first circuit for outputting a pixel signal; … an interlayer insulating film disposed between the first semiconductor substrate and the second semiconductor substrate, wherein a first through wiring line electrically coupling the first substrate section and the second substrate section is provided in the interlayer insulating film, … a third substrate section including a third semiconductor substrate having a second circuit for processing the pixel signal, … a third substrate section including a third semiconductor substrate having a second circuit for processing the pixel signal; and … wherein the first through wiring line electrically couples the first substrate section and the second substrate section, … wherein a first through wiring line electrically coupling the first substrate section and the second substrate section is provided in the interlayer insulating film, … wherein a first electrode in the second substrate section and a second electrode in the third substrate section are bonded to each other for electrically coupling the second substrate section and the third substrate section, and wherein, in a cross-sectional view, a width of the first through wiring line is narrower than at least one of a width of the first electrode or a width of the second electrode. … wherein a first electrode in the second substrate section and a second electrode in the third substrate section are bonded to each other for electrically coupling the second substrate section and the third substrate section, and wherein, in a cross-sectional view, a width of the first through wiring line is narrower than at least one of a width of the first electrode or a width of the second electrode. In view of the foregoing, claims 21-25 and 28-35 of the instant application are substantially identical claims 1-5, 8-13, and 16 of U.S. Patent No. 11,798,972, as indicated above, with the exception that claim 35 of the instant application further include limitations of “a signal processing circuit”. However, the Examiner notes that the use of a signal processing circuit that performs image processing for image storage and/or reproduction are routinely used, and within the knowledge of one of ordinary skill in the art. Allowable Subject Matter Claims 26-27 would be allowable if rewritten to overcome the Double Patenting rejection(s) set forth in this Office action, and to include all of the limitations of the base claim and any intervening claims. Claims 36-40 are allowed. The following is a statement of reasons for the indication of allowable subject matter: As for claim 36, the prior art does not teach or fairly suggest the use of a light detecting device, comprising a first substrate section including a first semiconductor substrate having a sensor pixel, a second substrate section including a second semiconductor substrate having a first circuit for outputting a pixel signal and a first through wiring line penetrating the second semiconductor substrate, and a third substrate section including a third semiconductor substrate having a second circuit for processing the pixel signal, wherein the first through wiring line electrically couples the first substrate section and the second substrate section, wherein a first electrode in the second substrate section and a second electrode in the third substrate section are bonded to each other for electrically coupling the second substrate section and the third substrate section, wherein, in a cross-sectional view, a width of the first through wiring line is narrower than at least one of a width of the first electrode or a width of the second electrode, and wherein, in the cross-sectional view, the first through wiring line is offset from the first and second electrodes in a lateral direction, in conjunction with the other limitations of the claims. As for claims 37-40, the reasons for allowance of these claims is due at least to their dependency upon allowable claims 36. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISS S YODER III whose telephone number is (571)272-7323. The examiner can normally be reached M-F 9:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at (571) 272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISS S YODER III/Examiner, Art Unit 2638
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Prosecution Timeline

Dec 30, 2024
Application Filed
Mar 31, 2026
Final Rejection mailed — §DP
May 29, 2026
Request for Continued Examination
Jun 01, 2026
Response after Non-Final Action
Sep 01, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
75%
Grant Probability
97%
With Interview (+21.7%)
2y 8m (~11m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 692 resolved cases by this examiner. Grant probability derived from career allowance rate.

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