DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 7, 8 and 15 are objected to because of the following informalities:
In Claim 1, line 5, the phrase “an LED driver” should be changed to -- an
microLED driver -- .
In Claim 1, line 6, the phrase “an LED driver” should be changed to -- an
microLED driver -- .
In Claim 1, line 15, the phrase “the intermediate region being dope” should
be changed to -- the intermediate region being doped -- .
In Claim 7, line 4, the phrase “an LED driver” should be changed to -- an microLED driver -- .
In Claim 8, line 1, the phrase “the optical waveguide” should be changed to
– the multimode optical waveguide -- .
In Claim 8, line 2, the phrase “the further LED” should be changed to – the
further microLED driver -- .
In Claim 15, line 5, the phrase “10 micrometers by 10 micrometers” should
be changed to – 10 micrometers -- .
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 6-8 and 12-15 are rejected on the ground of nonstatutory
double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 12,184,331 (Pezeshki et al). Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited by claims 1-4, 6-8 and 12-15 of the instant application are encompassed by claims 1-11 of US Patent No. 12,184,331 (Pezeshki et al).
Instant Application No. 19/005,433 (Claim 1)
US Patent No. 12,184,331 (Claim 1)
An optical communication system for communicating information
provided by a processor to another chip, comprising:
a microLED associated with the processor;
An optical communication system for communicating information
provided by a processor to another chip, comprising:
a microLED associated with the processor (i.e., see Claim 1 of US Patent No. 12,184,331);
an microLED driver to modulate optical output power of the microLED, such that the microLED will generate light based on data from the processor provided to the microLED driver ;
an microLED driver to modulate optical output power of the microLED, such that the microLED will generate light based on data from the processor provided to the microLED driver (i.e., see Claim 1 of US Patent No. 12,184,331);
a detector for performing optical-electrical conversion using the light; and
a detector for performing optical-electrical conversion using the light (i.e., see Claim 1 of US Patent No. 12,184,331); and
a multimode optical waveguide comprising a fiber optically coupling light from the microLED to the detector;
a multimode optical waveguide comprising a fiber optically coupling light from the microLED to the detector (i.e., see Claim 1 of US Patent No. 12,184,331);
wherein the microLED is mounted on a surface, the micro LED having a structure comprising comprising:
a p type layer having a p contact for electrical contacting;
an n type layer having an n contact for electrical contacting;
an intermediate region between the p type layer and the n type layer, the intermediate region being dope and including at least one quantum well, the at least one quantum well located physically closer to the p
type layer than the n type layer;
wherein the structure of the microLED is a lateral structure such that the p contact and the n contact both contact the surface that the microLED is mounted on.
wherein the microLED is mounted on a surface, the micro LED having a structure comprising comprising:
a p type layer having a p contact for electrical contacting;
an n type layer having an n contact for electrical contacting;
an intermediate region between the p type layer and the n type layer, the intermediate region being dope and including at least one quantum well, the at least one quantum well located physically closer to the p
type layer than the n type layer;
wherein the structure of the microLED is a lateral structure such that the p contact and the n contact both contact the surface that the microLED is mounted on (i.e., see Claim 1 of US Patent No. 12,184,331).
Regarding claim 2, as similarity described above, Pezeshki et al discloses wherein the intermediate region comprises p- doping (i.e., see Claim 2 of US Patent No. 12,184,331).
Regarding claim 3, as similarity described above, Pezeshki et al discloses
wherein the p- doping is in the range of 10¹⁶/cm³ to 10¹⁷/cm³ (i.e., see Claim 3 of US Patent No. 12,184,331).
Regarding claim 4, as similarity described above, Pezeshki et al discloses wherein the intermediate region comprises n- doping (i.e., see Claim 4 of US Patent No. 12,184,331).
Regarding claim 6, as similarity described above, Pezeshki et al discloses
wherein the p type layer and the n type layer are comprised of GaN and the at least one quantum well comprises InGaN (i.e., see Claim 8 of US Patent No. 12,184,331).
Regarding claim 7, as similarity described above, Pezeshki et al discloses
further comprising: a further microLED associated with other chip; a further LED driver to modulate optical output power of the further microLED, such that the further microLED will generate light based on data provided to the further microLED driver from the other chip; and a further detector for performing optical-electrical conversion using the light from the further microLED; wherein the further microLED comprises: a p type layer; an n type layer; an intermediate region between the p type layer and the n type layer, the intermediate region being doped and including at least one quantum well, the at least one quantum well located physically closer to the p type layer than the n type layer (i.e., see Claim 9 of US Patent No. 12,184,331).
Regarding claim 8, as similarity described above, Pezeshki et al discloses
wherein the multimode optical waveguide optically couples light from the further microLED to the further detector (i.e., see Claim 10 of US Patent No. 12,184,331).
Regarding claim 12, as similarity described above, Pezeshki et al discloses
wherein the at least one quantum well has a width ranging between 1 nanometer to 3 nanometers (i.e., see Claim 6 of US Patent No. 12,184,331).
Regarding claim 13, as similarity described above, Pezeshki et al discloses
wherein the microLED has a diameter size ranging between .3 micrometers to 2 micrometers (i.e., see Claim 7 of US Patent No. 12,184,331).
Regarding claim 14, as similarity described above, Pezeshki et al discloses
wherein the at least one quantum well is between 1 and 3 quantum wells (i.e., see Claim 11 of US Patent No. 12,184,331).
Regarding claim 15, as similarity described above, Pezeshki et al discloses
wherein the microLED has an intermediate region of less than 10 micrometers (i.e., see Claim 7 of US Patent No. 12,184,331).
Allowable Subject Matter
Claims 1-4, 6-8 and 12-15 are allowed (if overcome the double patenting
above).
The following is an examiner’s statement of reasons for allowance:
Claims 1-4, 6-8 and 12-15 are allowable because Krishnamoorthy et al (US
Patent No. 7,961,990 cited by appicant), Yin et al (US Patent No. 10,840,408 cited by applicant), and Moon et al (US Patent No. 8,779,425 cited by applicant), takes alone or in combination, fails to teach wherein the microLED comprising: a p type layer having a p contact for electrical contacting; an n type layer having an n contact for electrical contacting; an intermediate region between the p type layer and the n type layer, the intermediate region being doped and including at least one quantum well, the at least one quantum well located physically closer to the p type layer than the n type layer; wherein the structure of the microLED is a lateral structure such that the p contact and the n contact both contact the surface that the microLED is mounted on.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure.
Krishnamoorthy et al (US Patent No. 7,961,990 cited by applicant) discloses multi-chip system including capacitively coupled and optical communication.
Yin et al (US Patent No. 10,840,408 cited by applicant) discloses enhanced efficiency of LED structure with n-doped quantum barriers.
Moon et al (US Patent No. 8,779,425 cited by applicant) discloses light emitting device, light emitting device package.
8. Any inquiry concerning this communication or earlier communications from
the examiner should be directed to Hanh Phan whose telephone number is
(571)272-3035. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kenneth Vanderpuye, can be reached on (571)272 -3078. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (703)305-4700.
/HANH PHAN/Primary Examiner, Art Unit 2634
