DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 30 December 2024.
Claims 1-11 are pending and have been presented for examination.
Claim Objections
Claim 6 objected to because of the following informalities: claim 6 recites “the memory of the first nFE_SAN” in line 20. The claim had previously recited “a cache memory of the first nFE_SAN”. The Examiner recommends amending the limitation to read “the memory of the first nFE_SAN” to be consistent.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second write lock request" in line 20. There is insufficient antecedent basis for this limitation in the claim. There is no previous mention of a second write lock request. For purposes of examination, the Examiner will interpret the limitation as “where a second write lock request is transmitted….”
Claim 2 is also rejected based on the claims’ dependency to claim 1.
Claim 3 recites the limitation "the memory of the nBE_SAN" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 1 had recited copying the first write data to the nBE_SAN, but does not mention any memory as part of the nBE_SAN. Therefore, “the memory” lacks antecedent basis.
Claim 4 recites the limitation "the nFE_SAN" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 1 previously set forth a first nFE_SAN, second nFE_SAN and third nFE_SAN. Therefore, it is not clear which one of the nFE_SAN elements previously set forth is begin referred to by “the nFE_SAN” in claim 4.
Claim 5 recites the limitation "the memory of the nBE_SAN" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 1 had recited copying the first write data to the nBE_SAN, but does not mention any memory as part of the nBE_SAN. Therefore, “the memory” lacks antecedent basis.
Claim 6 recites the limitation "upon completing the receiving the first write data into the memory of the first nFE_SAN" in line 20. There is insufficient antecedent basis for this limitation in the claim. There was no previously recited step of “receiving the first write data into the memory of the first nFE_SAN”, therefore, it is not clear when the completion of a step that hasn’t started would occur. For purposes of examination, the Examiner will interpret the limitation “a first write data into the cache memory of the first nFE_SAN” in line 15 as reading “receiving a first write data into the cache memory of the first nFE_SAN” as that will resolve the antecedent basis issue.
Claims 8 and 10 are also rejected based on their dependency to claim 6.
Claim 7 recites the limitation "the first write complete signal" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 6 previously set forth “a write complete signal” not “a first write complete signal”.
Claim 9 recites the limitation "the write data" in line 3. There is insufficient antecedent basis for this limitation in the claim. The claim previously set forth “first write data” not “write data”. It is not clear if “the write data” is referring to “the first write data” or different data.
Claim 11 recites the limitation "the nFE_SANs" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 6 previously set forth a first, second and third nFE_SAN, so it is not clear which of the first, second and third nFE_SAN’s are being referenced.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over JIBBE (U.S. Patent Application Publication #2017/0220249) in view of RADOVANOVIC (U.S. Patent Application Publication #2013/0145064).
1. JIBBE discloses A method of writing write data to at least one storage device in a multiple computer system comprising: generating, using a first host computer (see [0029]: Host 104), a first write request (see [0031]: data transactions performed by a host include write and read requests); passing the first write request to a first front-end storage controller (nFESAN) of the first host computer (see [0029]-[0031]: host sends a transaction to the storage controller over the HBA interface, the network connection of the storage controller that interfaces with the HBA would be the nFE_SAN; [0024]: storage controllers operate in pairs, a first host can interface with controller 108.a and a second host can interface with controller 108.b); generating, using a second host computer (see [0029]: host 104; [0016]: there are multiple hosts), a second write request (see [0031]: data transactions performed by a host include write and read requests); passing the second write request to a second nFE_SAN of the second host computer (see [0029]-[0031]: host sends a transaction to the storage controller over the HBA interface, the network connection of the storage controller that interfaces with the HBA would be the nFE_SAN; [0024]: storage controllers operate in pairs, a first host can interface with controller 108.a and a second host can interface with controller 108.b); copying a first write data to a memory of the first nFE_SAN (see [0087]: the controllers perform write-back caching, write data associated with a write request is stored in the cache of the controller); copying the first write data to a memory of an nFE_SAN selected from a third nFESAN and the second nFESAN (see [0087]: the controller that received the write request sends a copy of the request to a mirror target controller, this could be a second nFE_SAN; [0053]: the controller can designated multiple mirror targets, this second mirror target would be the third nFE_SAN); generating a first write lock request and transmitting the first write lock request from the first nFE_SAN to a back-end storage controller (nBESAN); transmitting a first write lock grant from the nBE_SAN to the first nFE_SAN (see RADOVANOVIC below); upon completing copying the first write data to the memory of the first nFE_SAN and the memory of the nFE_SAN selected from the third nFE_SAN and the second nFE_SAN, and receiving the first write lock grant from the nBE_SAN (see RADOVANOVIC below), the first nFESAN providing a write complete signal to the first host computer (see [0087]: once the write is mirrored to the second storage controller, a status confirmation is sent back to the host); copying the first write data to the nBE_SAN (see [0035]: IOC of controller interfaces with the storage devices, this would be the nBE_SAN); writing, by the nBE_SAN, the first write data to the at least one storage device (see [0087]: data is persisted to the targeted volume); where the second write lock request is transmitted to the nBE_SAN after the first write lock request is transmitted to the nBE_SAN and before the first nFE_SAN provides the first write complete signal to the first host computer; and after the first write data is copied to the nBESAN, providing a second write lock grant to the second nFE_SAN (see RADOVANOVIC below).
RADOVANOVIC discloses the following limitations that are not disclosed by JIBBE: generating a first write lock request and transmitting the first write lock request from the first nFE_SAN to a back-end storage controller (nBESAN) (see [0035]: front end will examine the command, determine a write command is received, then send a lock request); transmitting a first write lock grant from the nBE_SAN to the first nFE_SAN (see [0035]: back end will respond acknowledging a successful lock); where the second write lock request is transmitted to the nBE_SAN after the first write lock request is transmitted to the nBE_SAN (see [0036]: a second request for a lock can be sent to the back end controller) and before the first nFE_SAN provides the first write complete signal to the first host computer (see [0035]: lock mechanisms are used to enforce atomic execution of commands, obtaining a lock before sending a write complete signal would be part of the atomic execution of the instruction); and after the first write data is copied to the nBESAN, providing a second write lock grant to the second nFE_SAN (see [0035]-[0036]: successful lock is acknowledged, this would be the second lock grant, the second lock will be granted after the first lock is released). JIBBE discloses sending a write complete signal after copying the data to the second or third nFE_SAN. JIBBE does not disclose also sending a write lock request before sending the write complete signal. RADOVANOVIC discloses using the lock mechanism to enforce an atomic execution of an operation. Obtaining a lock before sending the write request would be considered part of the atomic execution of an operation. Once the lock is obtained, the controller now has exclusive access to the address ranges for the write data, ensuring there is no intervening operations. Modifying JIBBE to include a lock mechanism would allow for execution of commands that require atomic execution (see [0035]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JIBBE to request a lock and receive a lock grant, as disclosed by RADOVANOVIC. One of ordinary skill in the art would have been motivated to make such a modification to allow for execution of commands that require atomic execution, as taught by RADOVANOVIC. JIBBE and RADOVANOVIC are analogous/in the same field of endeavor as both references are directed to hosts writes to a storage system.
2. The method of claim 1 where the first and second host computer are different (see JIBBE, figure 1, element 104: multiple independent host computers).
4. The method of claim 2 wherein the first write complete signal is provided to the first computer before the copying of the write data from the nFE_SAN to the nBE_SAN completes (see JIBBE [0087]: once the write is mirrored to the second storage controller, a status confirmation is sent back to the host, the status confirmation is sent prior to the data being written to the storage devices).
Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over JIBBE (U.S. Patent Application Publication #2017/0220249) and RADOVANOVIC (U.S. Patent Application Publication #2013/0145064) as applied to claims 1, 2 and 4 above, and further in view of BERT (U.S. Patent Application Publication #2016/0203080).
3. The method of claim 2 (see JIBBE above) where a memory in which the first write data is stored and selected from the memory of the first nFE_SAN and the memory of the nBE_SAN comprises a nonvolatile or flash memory (see BERT below).
BERT discloses the following limitations that are not disclosed by JIBBE: a memory in which the first write data is stored and selected from the memory of the first nFE_SAN and the memory of the nBE_SAN comprises a nonvolatile or flash memory (see [0021]: cache memory of controller can be a flash memory or NVDRAM). There are a limited number of options for cache memory used by a storage controller, as shown by BERT. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397. JIBBE also suggests the use of non-volatile memory for the cache (see [0003]: controllers commit the data to non-volatile memory prior to returning status).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JIBBE to use a nonvolatile or flash memory, as disclosed by BERT. One of ordinary skill in the art would have been motivated to make such a modification as the use of non-volatile memory for a cache would be obvious to try based on the limited number of available options, as taught by BERT. JIBBE and BERT are analogous/in the same field of endeavor as both references are directed to a storage system with multiple controllers.
5. The method of claim 4 (see JIBBE above) where a memory in which the first write data is stored and selected from the memory of the first nFE_SAN and the memory of the nBE_SAN comprises a nonvolatile or flash memory (see BERT below).
BERT discloses the following limitations that are not disclosed by JIBBE: a memory in which the first write data is stored and selected from the memory of the first nFE_SAN and the memory of the nBE_SAN comprises a nonvolatile or flash memory (see [0021]: cache memory of controller can be a flash memory or NVDRAM). There are a limited number of options for cache memory used by a storage controller, as shown by BERT. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397. JIBBE also suggests the use of non-volatile memory for the cache (see [0003]: controllers commit the data to non-volatile memory prior to returning status).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify JIBBE to use a nonvolatile or flash memory, as disclosed by BERT. One of ordinary skill in the art would have been motivated to make such a modification as the use of non-volatile memory for a cache would be obvious to try based on the limited number of available options, as taught by BERT. JIBBE and BERT are analogous/in the same field of endeavor as both references are directed to a storage system with multiple controllers.
Allowable Subject Matter
Claim 6 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The state of the art fails to anticipate, or render obvious, “… upon completing receiving the first write data into the memory of the first nFE_SAN, and passing the first write data to at least one of cache memory of the second nFE_SAN, third nFE_SAN, and nBE_SAN, and receiving a first write lock grant from the nBE_SAN, provide a write complete signal to the first host computer; and where the nBESAN is configured to write the first write data to the at least one storage device after sending the first write lock grant to the first nFE_SAN.”
The art of record discloses mirroring write requests between two or more controllers, but does not disclose also writing that data to a cache of the nBE_SAN before providing a write complete signal.
OLSON [7,127,633] discloses mirroring data between a front end controller and a back end controller to protect the data in the event a front end controller was to fail (see column 19). However, JIBBE already discloses mirroring data between front end controllers to prevent data loss if one of the controllers were to fail. There is no rationale for also mirroring the data to a back end controller, because the data has already been protected by mirroring between the front end controllers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CHANDRASHEKAR [2016/0085460]: discloses redundant front end controllers, mirroring data between the controllers and sending a write complete signal to the host. [0007]-[0009]
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132