DETAILED ACTION
1. This action is in response the election filed on 8/17/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
3. Applicant’s election without traverse of Species V, claims 1-10 and 13-15 (Fig. 11, 12A-C, 13 and 14) in the reply filed on 8/17/26 is acknowledged.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Stanesti et al. (US 20040113585) in view of Kayama (US 20130313904).
Regarding claim 1: Stanesti et al. disclsoes (i.e. figures 7-9) an integrated circuit (IC) for power management (i.e. 700), the IC comprising:
a power supply node (i.e. node for AC adapter);
a first port (i.e. port for BATT. B) for coupling to a primary power source (i.e. BATT. B);
a first switch (i.e. SW4) coupled (i.e. electrically coupled) between the power supply node (i.e. node for AC adapter) and the first port (i.e. port for BATT. B);
a second port (i.e. port for BATT. A) for coupling to a secondary power source (i.e. BATT. A);
a third port (i.e. port for 708 input terminal) for coupling (i.e. electrically coupled) to the secondary power source (i.e. BATT. A) through an inductive element (i.e. 708), a second switch (i.e. SW1) coupled to the power supply node (i.e. node for AC adapter),
a second voltage regulator (i.e. regulator of 700 includes SW5, SW6) comprising a first node (i.e. node between 708 and 707) coupled (i.e. electrically coupled) to the third port (i.e. port for 708 input terminal); and
a second switch (i.e. SW1) coupled between the power supply node (i.e. node for AC adapter) and a second node (i.e. node connecting SW5 to 731) of the second voltage regulator (i.e. regulator of 700 includes SW5, SW6).
but does not specifically disclose a first voltage regulator coupled between the power supply node and the second port.
Kayama discloses an integrated circuit (i.e. figures 2-4) comprising a first voltage regulator (i.e. 2122) coupled between the power supply node (i.e. T1) and the second port (i.e. T3);
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the integrated circuit as disclose by Kayama to have a second switch coupled between the power supply node and a second node of the second voltage regulator, because there a need to implement an electronic circuit that automatically selects a power supply to be used from a plurality of power supplies.
Regarding claim 8: Stanesti et al. disclose (i.e. figures 7-9) the primary power source (i.e. BATT. B) coupled (i.e. electrically coupled) to the first port (i.e. port for BATT. B) of the IC; the secondary power source (i.e. BATT. A) coupled (i.e. electrically coupled) to the second port (i.e. port for BATT. B) of the IC; an inductive element (i.e. inductor) coupled (i.e. electrically coupled) between the third port (i.e. port for 708 input terminal) of the IC and the secondary power source (i.e. BATT. B); and one or more circuits (i.e. circuit of 700) coupled (i.e. electrically coupled) to, and configured to receive power (i.e. from 732) via, the power supply node (i.e. node for AC adapter).
Regarding claim 10: Stanesti et al. disclose a power supply circuit for a portable device (i.e. figures 7-9), the power supply circuit comprising:
a first power supply node (i.e. node for AC adapter);
a second power supply node (i.e. node for BATT. B) for coupling to a primary power source (i.e. BATT. B);
a first switch (i.e. SW4) coupled between the first power supply node (i.e. node for AC adapter) and the second power supply node (i.e. node for BATT. B);
a third power supply node (i.e. node for BATT. A) for coupling to a secondary power source (i.e. BATT. B);
a second voltage regulator (i.e. regulator of 700 includes SW5, SW6) comprising an input (i.e. input of the regulator) coupled to the third power supply node (i.e. node for BATT. A) and an output coupled to the first power supply node (i.e. node for AC adapter); and
an integrated circuit (IC) (i.e. IC of figure 700) comprising a first port (i.e. 794) coupled (i.e. electrically coupled) to the first power supply node (i.e. node for AC adapter) and a second port (i.e. 798) coupled to the third power supply node (i.e. node for BATT. B) and configured to sense a parameter (i.e. parameter provide to the port) associated with the secondary power source (i.e. BATT. B), wherein the IC is configured to control charging of the secondary power source (i.e. BATT. B) based on the sensed parameter (i.e. parameter provide to the port).
but does not specifically disclose a first voltage regulator comprising an input coupled to the first power supply node and an output coupled to the third power supply node;
Kayama discloses an integrated circuit (i.e. figures 2-4) comprising a first voltage regulator (i.e. 2122) comprising an input coupled to the first power supply node (i.e. T1) and an output coupled (i.e. electrically coupled) to the third power supply node (i.e. T3);
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the integrated circuit as disclose by Kayama to have a second switch coupled between the power supply node and a second node of the second voltage regulator, because there a need to implement an electronic circuit that automatically selects a power supply to be used from a plurality of power supplies.
6. Claims 2-3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Stanesti et al. (US 20040113585) in view of Kayama (US 20130313904) and further in view of Lim et al. (US 20200067335).
Regarding claim 2: Stanesti et al. disclsoes (i.e. figures 7-9) the second voltage regulator (i.e. regulator of 700 includes SW5, SW6) comprises a buck converter in a forward direction from the second node (i.e. node connecting SW5 to 731) to the first node (i.e. node between 708 and 707),
but does not specifically disclose the first voltage regulator comprises a low-dropout (LDO) regulator and wherein and a boost converter in a reverse direction from the first node to the second node.
Kayama discloses an integrated circuit (i.e. figures 2-4) the first voltage regulator comprises a low-dropout (LDO) regulator (i.e. 2122).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the integrated circuit as disclose by Kayama to have a second switch coupled between the power supply node and a second node of the second voltage regulator, because there a need to implement an electronic circuit that automatically selects a power supply to be used from a plurality of power supplies.
Lim et al. disclose a power supply comprising a boost converter (i.e. SMPS of figure 4) in a reverse direction (i.e. reverse boost) from the first node (i.e. 412) to the second node (i.e. 404) (i.e. ¶ 29-37).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the power supply as disclose by Lim et al.’s to allow a load such as a CPU to operate at maximum performance.
Regarding claim 3: Stanesti et al. disclsoes (i.e. figures 7-9) wherein for a hot swap mode (i.e. swap between batteries): the second switch (i.e. SW1) is configured to be closed; and the first switch (i.e. SW4) is configured to be open after primary power source (i.e. BATT. B) is removed,
but does not specifically disclose the second voltage regulator is configured to be enabled in a reverse boost configuration, such that the secondary power source can provide power to the power supply node via the second voltage regulator and the second switch.
Lim et al. disclose a power supply comprising the second voltage regulator (i.e. SMPS of figure 4) is configured to be enabled in a reverse boost configuration (i.e. reverse boost), such that the secondary power source (i.e. 104) can provide power to the power supply node (i.e. 404) via the second voltage regulator (i.e. SMPS of figure 4) (i.e. ¶ 29-37).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the power supply as disclose by Lim et al.’s to have the secondary power source can provide power to the power supply node via the second voltage regulator and the second switch, because it allows a load such as a CPU to operate at maximum performance.
Regarding claim 13: Stanesti et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the first voltage regulator comprises a low-dropout (LDO) regulator and wherein the second voltage regulator comprises a boost converter.
Kayama discloses an integrated circuit (i.e. figures 2-4) the first voltage regulator comprises a low-dropout (LDO) regulator (i.e. 2122).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the integrated circuit as disclose by Kayama to have a second switch coupled between the power supply node and a second node of the second voltage regulator, because there a need to implement an electronic circuit that automatically selects a power supply to be used from a plurality of power supplies.
Lim et al. disclose a power supply comprising the second voltage regulator comprises a boost converter (i.e. SMPS of figure 4) (i.e. ¶ 29-37).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the power supply as disclose by Lim et al.’s to allow a load such as a CPU to operate at maximum performance.
7. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Stanesti et al. (US 20040113585) in view of Kayama (US 20130313904) and further in view of Kudo et al. (US 20160087462).
Regarding claim 6: Stanesti et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a fourth port for coupling to a charger; a fifth port for coupling to the power supply node; a third voltage regulator including a first node coupled to the fifth port; and a third switch coupled between the fourth port and a second node of the third voltage regulator.
Kudo et al. disclose a power supply (i.e. figures 13 and 14) comprising a fourth port (i.e. SYS) for coupling to a charger (i.e. circuitry of 200 or 300); a fifth port (i.e. input port of 330) for coupling to the power supply node (i.e. IN1); a third voltage regulator (i.e. 330) including a first node (i.e. node connecting S11, S12) coupled to the fifth port (i.e. input port of 330); and a third switch (i.e. SP) coupled (i.e. electrically coupled) between the fourth port (i.e. SYS) and a second node (i.e. node between T3, T4) of the third voltage regulator (i.e. 330).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.’s invention with the power supply as disclose by Kudo et al. to increase the efficiency and stability of the charger.
8. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Stanesti et al. (US 20040113585) in view of Kayama (US 20130313904) and further in view of Akiyama et al. (US 20180123385).
Regarding claim 9: Stanesti et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose an interface for a user of the portable device to selectively control the portable device to enter a hot swap mode; and an indicator configured to indicate to the user that the portable device is in the hot swap mode.
Akiyama et al. disclose a hardware switch (i.e. figure 6) comprising an interface for a user (i.e. user of mobile devices) of the portable device (i.e. device of figure 6) to selectively control the portable device to enter a hot swap mode (i.e. hot swap of the batteries); and an indicator configured to indicate to the user (i.e. indicator of the mobile devices) that the portable device is in the hot swap mode (i.e. 1 50-51).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Stanesti et al.'s invention with the hardware switch as disclose by Akiyama et al., because it is desirable to implement a dual battery system for a mobile device that allows for swapping of a primary battery without interrupting the functionality of the mobile device, which may include hot swapping of the primary battery.
Allowable Subject Matter
9. Claims 4-5, 7, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nguyen Tran/Primary Examiner, Art Unit 2838