Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 12/31/2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/22/2025 and 05/12/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claims 4, 5, 8, and 16 are objected to because of the following informalities: Regarding claim 4, in line 1-2, “further being coupled to” appears that it should read as “further coupled to”.
Regarding claim 5, in line 1-2, “further being coupled to” appears that it should read as “further coupled to”.
Regarding claim 8, in line 2-3, “substantially keeps unchanged” appears that it should read as “remains substantially unchanged”.
Regarding claim 16, in line 2-3, “substantially keeps unchanged” appears that it should read as “remains substantially unchanged”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-9, and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ju et al. (US Patent US 8,106,639 B1, hereinafter “Ju”) in view of Chen et al. (US Patent Application Publication US 2010/0231272 A1, hereinafter “Chen”).
Regarding claim 1, Ju discloses (see Figs. 2 - 7) a control circuit (comprising feed-forward circuit 210, control circuitry 220, and error amplifier EA1) for a power converter (regulator 200), the power converter having an input voltage (VDD) and an output voltage (VOUT), the control circuit comprising: an operation circuit (412 of Fig. 4), configured to generate a second error voltage (adjusted error signal VC′1 and VC’2) according to a computation result of a first error voltage (error signal VC) and the input voltage (VDD) (the feed-forward circuit provides adjusted error signal VC′1 and VC’2 from error signal VC and input voltage VDD; see col.5, lines 9-58), wherein the first error voltage is generated from the output voltage (error amplifier EA1 provides error signal VC from feedback signal VFB derived from VOUT; see col. 4, lines 59-64); and a comparator (see Fig. 5, PWM comparator COMP1 and COMP2), coupled to the operation circuit, configured to compare the second error voltage with a ramp voltage (ramp signal VRAMP) to generate a control signal (PWM signals SCTL_1 – SCTL_4; PWM comparator compares the adjusted error signal to a ramp signal; see col. 8, lines 4-17).
Ju does not disclose a ramp generator configured to receive the input voltage or the output voltage to generate the ramp voltage.
However, Chen teaches (see Fig. 7 and Fig. 8) a ramp generator (ramp generator 72) configured to receive the input voltage to generate a ramp voltage (ramp generator 72 to monitor the input voltage Vin to provide two ramp signals SAWbuck and SAWboost, see [0021]; a peak of the buck ramp signal SAWbuck, and a valley of the boost ramp signal SAWboost, varying with the input voltage, see [0019]-[0020]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control circuit of Ju wherein the ramp generator receives the input voltage to generate the ramp voltage, as taught by Chen, because it can help change the duty of the control signal in response to a variation of the input voltage so as to achieve fast line response and stabilize the output voltage (see [0006] of Chen).
Regarding claim 3, Ju discloses (see Fig. 7) wherein the control signal is used to control a duty cycle of the power converter (the duty cycles of buck mode and boost mode are determined by the comparisons of VC’1 and VC’2 with VRAMP, see col. 7, line 59 – col. 8, line 3).
Regarding claim 4, Ju discloses (see Fig. 5 and Fig. 6) a processing circuit (520 and drive circuit DRV1), which receives the control signal and generates a plurality of driving signals (switch control signals SCTL_1–SCTL_4) for controlling a plurality of switches (transistors M1–M4) in the power converter according to the control signal (drive circuit DRV1 drives switches M1, M2, M3, and M4 based on signals BOOST and BUCK, see col. 8, lines 10-17).
Regarding claim 5, Ju discloses (see Fig. 2) further being coupled to an error amplifier (EA1), to receive the first error voltage (error signal VC) from the error amplifier (feed-forward circuit 210 is arranged to receive error signal VC).
Regarding claim 6, Ju discloses (see Fig. 2) wherein the error amplifier (EA1) generates the first error voltage (error signal VC) according to the output voltage (EA1 receives feedback signal VFB provided by divider R1/R2 from VOUT and provides error signal VC).
Regarding claim 7, Ju does not disclose wherein the ramp generator changes a magnitude of the ramp voltage according to the input voltage or the output voltage.
However, Chen teaches (see Fig. 4 and Fig. 8) wherein the ramp generator (72) changes a magnitude of the ramp voltage (SAWbuck) according to the input voltage (Vin; the peak value of the buck ramp signal SAWbuck is adjusted according to the varying input voltage Vin, see [0019]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control circuit of Ju wherein the ramp generator changes a magnitude of the ramp voltage according to the input voltage or the output voltage, as taught by Chen, because it can help change the duty of the control signal in response to a variation of the input voltage so as to achieve fast line response and stabilize the output voltage (see [0006] of Chen).
Regarding claim 8, Ju discloses (see Fig. 7) wherein the first error voltage substantially keeps unchanged during a transition of the input voltage (the feed-forward scaling constants are calculated to reduce the variance on error signal VC for a step on VDD, col. 6, lines 54-62; col. 9, lines 11-62).
Regarding claim 9, Ju discloses (see Figs. 2 - 7) a power converter (regulator 200), the power converter having an input voltage (VDD) and an output voltage (VOUT), the control circuit comprising: an operation circuit (412 of Fig. 4), configured to generate a second error voltage (adjusted error signal VC′1 and VC’2) according to a computation result of a first error voltage (error signal VC) and the input voltage (VDD) (the feed-forward circuit provides adjusted error signal VC′1 and VC’2 from error signal VC and input voltage VDD; see col.5, lines 9-58), wherein the first error voltage is generated from the output voltage (error amplifier EA1 provides error signal VC from feedback signal VFB derived from VOUT; see col. 4, lines 59-64); and a comparator (see Fig. 5, PWM comparator COMP1 and COMP2), coupled to the operation circuit, configured to compare the second error voltage with a ramp voltage (ramp signal VRAMP) to generate a control signal (PWM signals SCTL_1 – SCTL_4; PWM comparator compares the adjusted error signal to a ramp signal; see col. 8, lines 4-17).
Ju does not disclose a ramp generator configured to receive the input voltage or the output voltage to generate the ramp voltage.
However, Chen teaches (see Fig. 7 and Fig. 8) a ramp generator (ramp generator 72) that monitors the input voltage to provide a ramp signal whose magnitude varies with the input voltage (see [0019]-[0021] of Chen).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power converter of Ju wherein the ramp generator receives the input voltage to generate the ramp voltage, as taught by Chen, because it can help change the duty of the control signal in response to a variation of the input voltage so as to achieve fast line response and stabilize the output voltage (see [0006] of Chen).
Regarding claim 11, Ju discloses (see Fig. 7) wherein the control signal is used to control a duty cycle of the power converter (the duty cycles of buck mode and boost mode are determined by the comparisons of VC’1 and VC’2 with VRAMP, see col. 7, line 59 – col. 8, line 3).
Regarding claim 12, Ju discloses (see Fig. 5 and Fig. 6) a processing circuit (520 and drive circuit DRV1), which receives the control signal and generates a plurality of driving signals (switch control signals SCTL_1–SCTL_4) for controlling a plurality of switches (transistors M1–M4) in the power converter according to the control signal (drive circuit DRV1 drives switches M1, M2, M3, and M4 based on signals BOOST and BUCK, see col. 8, lines 10-17).
Regarding claim 13, Ju discloses (see Fig. 2) further being coupled to an error amplifier (EA1), to receive the first error voltage (error signal VC) from the error amplifier (feed-forward circuit 210 is arranged to receive error signal VC).
Regarding claim 14, Ju discloses (see Fig. 2) wherein the error amplifier (EA1) generates the first error voltage (error signal VC) according to the output voltage (EA1 receives feedback signal VFB provided by divider R1/R2 from VOUT and provides error signal VC).
Regarding claim 15, Ju does not disclose wherein the ramp generator changes a magnitude of the ramp voltage according to the input voltage or the output voltage.
However, Chen teaches (see Fig. 4 and Fig. 8) wherein the ramp generator (72) changes a magnitude of the ramp voltage (SAWbuck) according to the input voltage (Vin; the peak value of the buck ramp signal SAWbuck is adjusted according to the varying input voltage Vin, see [0019]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control circuit of Ju wherein the ramp generator changes a magnitude of the ramp voltage according to the input voltage or the output voltage, as taught by Chen, because it can help change the duty of the control signal in response to a variation of the input voltage so as to achieve fast line response and stabilize the output voltage (see [0006] of Chen).
Regarding claim 16, Ju discloses (see Fig. 7) wherein the first error voltage substantially keeps unchanged during a transition of the input voltage (the feed-forward scaling constants are calculated to reduce the variance on error signal VC for a step on VDD, col. 6, lines 54-62; col. 9, lines 11-62).
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ju in view of Chen, and further in view of Bello et al. (US Patent US 4,536,700, hereinafter “Bello”).
Regarding claim 2, Ju does not disclose wherein the operation circuit comprises a subtractor, which is configured to subtract the input voltage from the first error voltage to generate the second error voltage.
However, Bello teaches (see Fig. 3) an operation circuit (a feed-forward resistor network connecting the input voltage and the error-amplifier output to a common comparator input) comprising a subtractor configured to subtract the input voltage from the first error voltage (the error-amplifier output) to generate the second error voltage (control voltage Vc; when the input voltage increases, the control voltage decreases in proportion to the input voltage for a constant error-amplifier output voltage, see col. 5, ll. 25-40).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control circuit of Ju wherein the operation circuit comprises a subtractor configured to subtract the input voltage from the first error voltage to generate the second error voltage, as taught by Bello, because subtracting a feed-forward portion of the input voltage from the error-amplifier output provides a swifter and more complete cancellation of input-voltage variations so as to keep the output voltage constant (see col. 2, lines 13-26 of Bello).
Regarding claim 10, Ju does not disclose wherein the operation circuit comprises a subtractor, which is configured to subtract the input voltage from the first error voltage to generate the second error voltage.
However, Bello teaches (see Fig. 3) an operation circuit (a feed-forward resistor network connecting the input voltage and the error-amplifier output to a common comparator input) comprising a subtractor configured to subtract the input voltage from the first error voltage (the error-amplifier output) to generate the second error voltage (control voltage Vc; when the input voltage increases, the control voltage decreases in proportion to the input voltage for a constant error-amplifier output voltage, see col. 5, ll. 25-40).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the control circuit of Ju wherein the operation circuit comprises a subtractor configured to subtract the input voltage from the first error voltage to generate the second error voltage, as taught by Bello, because subtracting a feed-forward portion of the input voltage from the error-amplifier output provides a swifter and more complete cancellation of input-voltage variations so as to keep the output voltage constant (see col. 2, lines 13-26 of Bello).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2010/0231183 A1 discloses a power converter with improved line transient. US 2010/0148740 A1 discloses an input feedforward buck-boost converter. US 2005/0046401 A1 discloses an input feedforward converter with constant bandwidth.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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