Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 19/006,300, the amendment filed on 5/7/2026 is herein acknowledged. Claims 1, 12 and 20 have been amended. Claims 1-20 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
CLAIM CONSTRUCTION
The present application contains contingent limitations. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04(II).
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding "The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim"); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
It is suggested that the conditional statements be removed. Alternatively, the conditions precedent may be claimed affirmatively in order to give the claims their proper weight.
The limitations “determining whether an input memory address… corresponds to one of predetermined designated memory addresses… in response to the determination that the input memory address corresponds to one of the designated memory address…” in method claim 12 are contingent limitations since it may be determined that “an input memory address…” does not “correspond” to one of the designated memory addresses under the “whether condition”. These limitations in method claim 12 should be amended to require the conditional statement to be met and then perform the claimed functionality.
For example, claim 12 should be amended to recite “determining an input memory address… corresponds to one of predetermined designated memory addresses… in response to the determination that the input memory address corresponds to one of the designated memory address…”.
Method claim 16 should be amended in a similar manner.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kotra et al. (US 2023/0205693) in view of C. H. Kim et al. (“Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests”, vol. 33, no. 2, pp. 251-262, 1 Feb. 2022, doi: 10.1109/TPDS.2021.3065365).
1. An electronic device comprising: a routing register configured to store mapping information that maps each of predetermined designated memory addresses representing a partial area of a memory to a redirected memory address representing another partial area of the memory; and [Kotra teaches “the memory controller 140 includes a PIM register mapping table 142 to facilitate the use of the PIM register file 118 for expediting non-PIM instructions. The PIM register mapping table 142 maps memory locations to PIM registers. For example, to utilize a PIM register as a write buffer for a non-PIM instruction, the memory controller logic 130 remaps (since the address is remapped, it corresponds to the claimed redirected memory address) the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register.” (par. 0040) (see fig. 1 and related text) where memory device 312 includes PIM registers in PIM unit 352 and physical memory location within a memory row 356 of memory array 350 (see fig. 4 and related text) thus, both the PIM registers and physical address locations in the memory device represent partial areas of the memory device 312 (see pars. 0041, 0051, 0059 and 0064)]
selection logic configured to, when an input memory address comprised in a memory command received from a host processor corresponds to one of the designated memory addresses, convert the input memory address into a redirected memory address that is mapped to the corresponding designated memory address based on the mapping information, [Kotra teaches “ FIG. 1 includes a host device 170 having a processor 132 that includes one or more processor cores 104. While four processor cores are depicted in FIG. 1, it should be understood that the host device 170 can include more or fewer processor cores than depicted. In various examples, the processor cores 104 are CPU cores, GPU cores, or other cores known to those of ordinary skill in the art. The processor cores 104 issue memory instructions or commands to transfer data between the processor 132 and a memory device 180 by, for example, reading data stored in the memory device into a processor cache or writing data in a processor cache to the memory device. “ (par. 0023) where “ the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location… Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040) thus addresses are remapped or redirected from target memory locations to PIM register locations within the memory device]
wherein, in response to the memory command being executed at the converted redirected memory address, [Kotra teaches “the memory controller logic 130 drains write instructions to the PIM register file 118 using PIM write commands.” (par. 0034) “the memory controller 310 migrates the first data 322 to the first memory location using a PIM store command. For example, the PIM store command specifies the register index of the PIM register 326 that holds the data 322 and the memory location 324 that is the destination for the write instruction 320.” (par. 0049) “the memory controller 610 reads the data 622 held in the PIM register 626 instead of dispatching the non-PIM read instruction to the memory device 612.” (par. 0059)].
the electronic device executes an instruction of a processing in memory (PIM) program, [Kotra teaches “[0032]… the memory controller 140 dispatches PIM commands that are not based on a PIM instruction received from the processor 132. That is, the memory controller 140 dispatches PIM commands to manage the PIM register file 118 for expediting non-PIM instructions. In some examples, PIM read commands and PIM write commands, along with PIM load commands and PIM store commands, are employed by the memory controller 140 to execute non-PIM read instructions and non-PIM write instructions using the PIM register file 118. Thus, teaching PIM operations for non-PIM memory commands].
Kotra does not expressly disclose the execution of the PIM program for the converted redirected memory address, using an operand stored at the converted redirected memory address to perform an arithmetic operation; however, regarding these limitations, C. H. Kim teaches [“The PIM device driver stores the PIM source and destination operand addresses and their read/write attributes in the PIM memory device’s configuration area before starting the PIM execution. The PIM device compares all incoming memory requests with the stored addresses and identifies the PIM requests. The operations for the PIM and non-PIM memory requests are the same except for handling the datapath. “ (Section 1) “ The PIM device compares the address of the incoming memory request with the stored operand information for identifying it as the PIM request. The PIM engine computes using the configuration information at every incoming PIM request.” (Section 3) “5) Arithmetic operation (MAC, ADD, SUB, MUL)… The PIM RD/WR command performs the standard memory request service also with the PIM execution. If the PIM RIU recognizes the PIM RD command, it turns on the bus switch connected to the PIM datapath. For example, the RD command matched to src0 operand (REG A) or src1 operand (REG B) stores the data read from the bank in vecA and vecB, respectively. Also, in PIM WR (matching the address of the destination operand in REG C), the PIM RIU turns on the bus switch and stores the accumulator registers to the bank instead of the data expressed in the write memory request. MOV ISA defines data movement from the general registers into vACC with mantissa expansion. CSTB ISA broadcasts one scalar from a vector register to the source of the entire MACs for vector-matrix multiplication.” (Section 4.1) “ the Silent-PIM architecture, performing inside DRAM with standard DRAM memory requests, and presented how the entire architecture layers, including applications, operating systems, and PIM devices to perform the computation. “ (Section 8)].
Kotra and C. H. Kim are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Kotra to include the execution of the PIM program for the converted redirected memory address, using an operand stored at the converted redirected memory address to perform an arithmetic operation as taught by C. H. Kim since doing so would provide the benefits of [“To the best of our knowledge, our study in this paper is first to propose a PIM architecture that does not require any modification of hardware components except for the PIM DRAM device itself. It implies that we can control the PIM device and perform the PIM computation only with standard memory requests by complying with the standard DRAM interface [17], i.e., preserving the DRAM standard operation semantics and their timing constraints.” (Section 1)].
Therefore, it would have been obvious to combine Kotra and C. H. Kim for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The electronic device of claim 1, wherein, when processing in memory (PIM) operations are performed on a target PIM tile of a PIM file corresponding to the converted redirected memory address, a plurality of redirected memory addresses stored in the routing register is updated to a plurality of redirected memory addresses corresponding to a next PIM tile of the PIM file [Kotra teaches “For example, when a PIM instruction reaches the execution unit 150, it can be serialized with other PIM instructions and memory accesses to DRAM targeting the same subset of the physical address space.” (par. 0026) “instructions issued by a processor core to read data from, or write data to, the memory array in the memory device 180 are referred to as ‘non-PIM instructions’… a memory controller that dispatches a PIM command the memory device 180 in response to receiving non-PIM instructions from a processor core 104” (par. 0031) “[0032]… In accordance with the present disclosure, the memory controller 140 utilizes the PIM register file 118 to expedite non-PIM memory instructions, such as read and write instructions, directed to the memory device 180. As described above, the memory controller 140 dispatches PIM commands in response to receiving a PIM instruction from the processor 132. In accordance with the present disclosures, the memory controller 140 dispatches PIM commands that are not based on a PIM instruction received from the processor 132. That is, the memory controller 140 dispatches PIM commands to manage the PIM register file 118 for expediting non-PIM instructions. In some examples, PIM read commands and PIM write commands, along with PIM load commands and PIM store commands, are employed by the memory controller 140 to execute non-PIM read instructions and non-PIM write instructions using the PIM register file 118.” Where “ the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location… Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040) where multiple PIM registers may be written or read (see figs. 5 and 8 and related text; pars. 0051, 0064)].
3. The electronic device of claim 1, wherein a PIM operation corresponding to the memory command is performed on data at the converted redirected memory address [Kotra teaches “[0032]… In accordance with the present disclosure, the memory controller 140 utilizes the PIM register file 118 to expedite non-PIM memory instructions, such as read and write instructions, directed to the memory device 180. As described above, the memory controller 140 dispatches PIM commands in response to receiving a PIM instruction from the processor 132. In accordance with the present disclosures, the memory controller 140 dispatches PIM commands that are not based on a PIM instruction received from the processor 132. That is, the memory controller 140 dispatches PIM commands to manage the PIM register file 118 for expediting non-PIM instructions. In some examples, PIM read commands and PIM write commands, along with PIM load commands and PIM store commands, are employed by the memory controller 140 to execute non-PIM read instructions and non-PIM write instructions using the PIM register file 118.” Where “ the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location… Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040)].
4. The electronic device of claim 1, further comprising: a control register configured to transmit, to the selection logic, an activation signal for the routing register, wherein the selection logic selects one of the input memory address and the mapped redirected memory address according to the activation signal [Kotra teaches “the PIM unit 150 includes control logic 114 for decoding instructions or commands issued from the processor cores 104 (e.g. command decoder), an arithmetic logic unit (ALU) 116 that performs an operation indicated in the PIM instruction, and a PIM register file 118 including a plurality of indexed registers for holding data for load/store operations to memory or intermediate values of ALU computations. In some examples, the ALU 116 is capable performing a limited set of operations relative to the ALUs of the processor cores 104, thus making the ALU 116 less complex to implement and, for example, more suited for an in-memory implementation. A PIM instruction can move data between the PIM registers and the memory array, and it can also trigger computation on this data in the ALU 116.” (par. 0025) where “ the memory controller 140 includes a PIM register mapping table 142 to facilitate the use of the PIM register file 118 for expediting non-PIM instructions. The PIM register mapping table 142 maps memory locations to PIM registers. For example, to utilize a PIM register as a write buffer for a non-PIM instruction, the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location... When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command. In some examples, the PIM register mapping table 142 includes multiple entries, where each entry maps a PIM register index to a memory location.” (par. 0040)].
5. The electronic device of claim 1, wherein the selection logic is configured to: determine whether the input memory address matches a given address among the designated memory addresses, when the input memory address matches the given address, convert the input memory address into a redirected memory address that is mapped to the given address and output the redirected memory address, and when the input memory address does not match the given address, output the input memory address [Kotra teaches “the memory controller logic 130 drains write instructions to the PIM register file 118 using PIM write commands.” (par. 0034) “the memory controller 310 migrates the first data 322 to the first memory location using a PIM store command. For example, the PIM store command specifies the register index of the PIM register 326 that holds the data 322 and the memory location 324 that is the destination for the write instruction 320.” (par. 0049) “the memory controller 610 reads the data 622 held in the PIM register 626 instead of dispatching the non-PIM read instruction to the memory device 612.” (par. 0059)].
6. The electronic device of claim 1, wherein the selection logic is configured to determine whether the input memory address corresponds to one of the designated memory addresses based on some bits of the input memory address [Kotra teaches “In some examples, the PIM register mapping table 142 includes multiple entries, where each entry maps a PIM register index to a memory location.” (par. 0040) “ In such an example, the PIM register mapping table 142 can be organized as a K-way set associative cache (K<N) with a number of sets equal to M. The index bits can be provided by the DRAM bank select bits (from the physical address of a memory instruction) (thus, corresponding to some bits of the input memory address). The remaining physical address bits can serve as a tag. The PIM register index can be stored in each PIM register mapping table entry. “ (par. 0041)].
7. The electronic device of claim 1, wherein the mapping information maps each of the predetermined designated memory addresses to the redirected memory address and a processing in memory (PIM) command to be executed at the redirected memory address, and the selection logic is configured to update the memory command to a PIM command that is mapped to the corresponding designated memory address, based on the mapping information [Kotra teaches “[0032]… In accordance with the present disclosure, the memory controller 140 utilizes the PIM register file 118 to expedite non-PIM memory instructions, such as read and write instructions, directed to the memory device 180. As described above, the memory controller 140 dispatches PIM commands in response to receiving a PIM instruction from the processor 132. In accordance with the present disclosures, the memory controller 140 dispatches PIM commands that are not based on a PIM instruction received from the processor 132. That is, the memory controller 140 dispatches PIM commands to manage the PIM register file 118 for expediting non-PIM instructions. In some examples, PIM read commands and PIM write commands, along with PIM load commands and PIM store commands, are employed by the memory controller 140 to execute non-PIM read instructions and non-PIM write instructions using the PIM register file 118.” Where “ the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location… Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040)].
8. The electronic device of claim 1, wherein non-cacheable access to an area corresponding to the designated memory addresses is allowed in the memory, and cacheable access to an area corresponding to the redirected memory address is allowed in the memory [Kotra teaches “the memory controller logic 130 uses the PIM register file 118 as a memory side cache or prefetch buffer. For example, the memory controller logic 130 can prepopulate, based on a speculative algorithm, the PIM register file 118 with data loaded using a PIM load command. If a non-PIM read instruction hits on the memory side cache, the memory controller logic can read the requested data from the PIM register file 118 using a PIM read command, which is faster than reading from the memory array because there is no need to open a memory row.” (par. 0039)].
9. The electronic device of claim 1, wherein the input memory address, designated memory addresses stored in the routing register, and the redirected memory addresses are expressed as row addresses [PIM registers are mapped to memory array rows (see figs. 3-8 and related text) “In some variations, there is a one-to-one mapping between all PIM registers within the memory channel and PIM register mapping table entries. In these implementations, the memory controller 310 updates an entry 406 corresponding to the PIM register 326, which holds the data 322 for the non-PIM write instruction 320, with the memory location 324 identified in the non-PIM write instruction 320… For example, in the example of FIG. 4, the memory controller 310 writes data 322 to PIM Register 1 and stores the PIM register index of PIM Register 1 and physical address 1 in an entry 406 of the PIM register mapping table 404…“ (par. 0050) where “the method of FIG. 5 also includes identifying 502, in the PIM register mapping table 404, a second entry 506 associating a second PIM register 526 with a second memory location 524, wherein the first memory location 324 and the second memory location 524 are included in one memory row. In some implementation, the memory controller 310 determines whether two or more valid entries in the PIM register mapping table 404 are associated with memory locations in the same bank row.” (par. 0051)].
10. The electronic device of claim 1, wherein, in the mapping information, each of the designated memory addresses is one-to-one mapped to a redirected memory address [Kotra teaches “the memory controller 140 includes a PIM register mapping table 142 to facilitate the use of the PIM register file 118 for expediting non-PIM instructions.” (par. 0040) “In some variations, there is a one-to-one mapping between all PIM registers within the memory channel and PIM register mapping table entries. In these implementations, the memory controller 310 updates an entry 406 corresponding to the PIM register 326, which holds the data 322 for the non-PIM write instruction 320, with the memory location 324 identified in the non-PIM write instruction 320… For example, in the example of FIG. 4, the memory controller 310 writes data 322 to PIM Register 1 and stores the PIM register index of PIM Register 1 and physical address 1 in an entry 406 of the PIM register mapping table 404…“ (par. 0050) “See PIM register mapping table (figs. 4-8)].
11. The electronic device of claim 1, further comprising: the host processor; and a memory controller configured to generate the memory command in response to a memory request received from the host processor, wherein the routing register and the selection logic are comprised in the memory controller, and the memory receives the converted redirected memory address from the memory controller [Kotra teaches “FIG. 1 includes a host device 170 having a processor 132 that includes one or more processor cores 104. While four processor cores are depicted in FIG. 1, it should be understood that the host device 170 can include more or fewer processor cores than depicted. In various examples, the processor cores 104 are CPU cores, GPU cores, or other cores known to those of ordinary skill in the art. The processor cores 104 issue memory instructions or commands to transfer data between the processor 132 and a memory device 180 by, for example, reading data stored in the memory device into a processor cache or writing data in a processor cache to the memory device. “ (par. 0023) ““ the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location… Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040) (see figs. 4-8 and related text)].
12. A method of operating an electronic device, the method comprising: determining whether an input memory address comprised in a memory command received from a host processor corresponds to one of predetermined designated memory addresses; [Kotra teaches “ FIG. 1 includes a host device 170 having a processor 132 that includes one or more processor cores 104. While four processor cores are depicted in FIG. 1, it should be understood that the host device 170 can include more or fewer processor cores than depicted. In various examples, the processor cores 104 are CPU cores, GPU cores, or other cores known to those of ordinary skill in the art. The processor cores 104 issue memory instructions or commands to transfer data between the processor 132 and a memory device 180 by, for example, reading data stored in the memory device into a processor cache or writing data in a processor cache to the memory device.” (par. 0023) “ the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location… Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040)]
in response to the determination that the input memory address corresponds to one of the designated memory addresses, converting the input memory address into a redirected memory address that is mapped to the corresponding designated memory address, based on mapping information stored in a routing register, [Note that the limitations “determining whether an input memory address… corresponds to one of predetermined designated memory addresses… in response to the determination that the input memory address corresponds to one of the designated memory address…” in method claim 12 are contingent limitations since it may be determined that “an input memory address…” does not “correspond” to one of the designated memory addresses under the “whether condition”. As such, the condition precedent may never be reached within the scope of the claim under the broadest reasonable interpretation. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II). (see Claim Construction section above). However; Kotra teaches “the memory controller 140 includes a PIM register mapping table 142 to facilitate the use of the PIM register file 118 for expediting non-PIM instructions. The PIM register mapping table 142 maps memory locations to PIM registers. For example, to utilize a PIM register as a write buffer for a non-PIM instruction, the memory controller logic 130 remaps (since the address is remapped, it corresponds to the claimed redirected memory address) the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register... Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040) thus addresses are remapped or redirected from target memory locations to PIM register locations within the memory device” (see fig. 1 and related text) where memory device 312 includes PIM registers in PIM unit 352 and physical memory location within a memory row 356 of memory array 350 (see fig. 4 and related text) (see pars. 0041, 0051, 0059 and 0064)]
wherein the mapping information maps each of the designated memory addresses representing a partial area of a memory to a redirected memory address representing another partial area of the memory; and [Kotra teaches “the memory controller 140 includes a PIM register mapping table 142 to facilitate the use of the PIM register file 118 for expediting non-PIM instructions. The PIM register mapping table 142 maps memory locations to PIM registers. For example, to utilize a PIM register as a write buffer for a non-PIM instruction, the memory controller logic 130 remaps (since the address is remapped, it corresponds to the claimed redirected memory address) the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register.” (par. 0040) (see fig. 1 and related text) where memory device 312 includes PIM registers in PIM unit 352 and physical memory location within a memory row 356 of memory array 350 (see fig. 4 and related text) thus, both the PIM registers and physical address locations in the memory device represent partial areas of the memory device 312 (see pars. 0041, 0051, 0059 and 0064)]
wherein, in response to the memory command being executed at the converted redirected memory address, [Kotra teaches “the memory controller logic 130 drains write instructions to the PIM register file 118 using PIM write commands.” (par. 0034) “the memory controller 310 migrates the first data 322 to the first memory location using a PIM store command. For example, the PIM store command specifies the register index of the PIM register 326 that holds the data 322 and the memory location 324 that is the destination for the write instruction 320.” (par. 0049) “the memory controller 610 reads the data 622 held in the PIM register 626 instead of dispatching the non-PIM read instruction to the memory device 612.” (par. 0059)]
executing an instruction of a processing in memory (PIM) program, [Kotra teaches “[0032]… the memory controller 140 dispatches PIM commands that are not based on a PIM instruction received from the processor 132. That is, the memory controller 140 dispatches PIM commands to manage the PIM register file 118 for expediting non-PIM instructions. In some examples, PIM read commands and PIM write commands, along with PIM load commands and PIM store commands, are employed by the memory controller 140 to execute non-PIM read instructions and non-PIM write instructions using the PIM register file 118. Thus, teaching PIM operations for non-PIM memory commands].
Kotra does not expressly disclose the executing using an operand stored at the converted redirected memory address to perform an arithmetic operation; however, regarding these limitations, C. H. Kim teaches [“The PIM device driver stores the PIM source and destination operand addresses and their read/write attributes in the PIM memory device’s configuration area before starting the PIM execution. The PIM device compares all incoming memory requests with the stored addresses and identifies the PIM requests. The operations for the PIM and non-PIM memory requests are the same except for handling the datapath. “ (Section 1) “ The PIM device compares the address of the incoming memory request with the stored operand information for identifying it as the PIM request. The PIM engine computes using the configuration information at every incoming PIM request.” (Section 3) “5) Arithmetic operation (MAC, ADD, SUB, MUL)… The PIM RD/WR command performs the standard memory request service also with the PIM execution. If the PIM RIU recognizes the PIM RD command, it turns on the bus switch connected to the PIM datapath. For example, the RD command matched to src0 operand (REG A) or src1 operand (REG B) stores the data read from the bank in vecA and vecB, respectively. Also, in PIM WR (matching the address of the destination operand in REG C), the PIM RIU turns on the bus switch and stores the accumulator registers to the bank instead of the data expressed in the write memory request. MOV ISA defines data movement from the general registers into vACC with mantissa expansion. CSTB ISA broadcasts one scalar from a vector register to the source of the entire MACs for vector-matrix multiplication.” (Section 4.1) “ the Silent-PIM architecture, performing inside DRAM with standard DRAM memory requests, and presented how the entire architecture layers, including applications, operating systems, and PIM devices to perform the computation. “ (Section 8)].
Kotra and C. H. Kim are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Kotra to include the executing of the PIM command using an operand stored at the converted redirected memory address to perform an arithmetic operation as taught by C. H. Kim since doing so would provide the benefits of [“To the best of our knowledge, our study in this paper is first to propose a PIM architecture that does not require any modification of hardware components except for the PIM DRAM device itself. It implies that we can control the PIM device and perform the PIM computation only with standard memory requests by complying with the standard DRAM interface [17], i.e., preserving the DRAM standard operation semantics and their timing constraints.” (Section 1)].
Therefore, it would have been obvious to combine Kotra and C. H. Kim for the benefit of creating a storage system/method to obtain the invention as specified in claim 12.
13. The method of claim 12, wherein, when processing in memory (PIM) operations are performed on a target PIM tile of a PIM file corresponding to the converted redirected memory address, a plurality of redirected memory addresses stored in the routing register is updated to a plurality of redirected memory addresses corresponding to a next PIM tile of the PIM file [The rationale in the rejection of claim 2 is herein incorporated].
14. The method of claim 12, wherein a processing in memory (PIM) operation corresponding to the memory command is performed on data of the converted redirected memory address [The rationale in the rejection of claim 3 is herein incorporated].
15. The method of claim 12, further comprising: selecting one of the input memory address and the mapped redirected memory address according to the activation signal for the routing register [The rationale in the rejection of claim 4 is herein incorporated].
16. The method of claim 12, wherein the converting into the redirected memory address comprises: determining whether the input memory address matches a given address among the designated memory addresses, when the input memory address matches the given address, converting the input memory address into a redirected memory address that is mapped to the given address, and when the input memory address does not match the given address, outputting the input memory address [The rationale in the rejection of claim 5 is herein incorporated. Note that in method claim 16, the limitations “when…” are contingent limitations and as such, the condition precedent “when…” may never be reached within the scope of the claim under the broadest reasonable interpretation. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II). (see Claim Construction section above)].
17. The method of claim 12, wherein the converting into the redirected memory address comprises: determining whether the input memory address corresponds to one of the designated memory addresses based on some bits of the input memory address [The rationale in the rejection of claim 6 is herein incorporated].
18. The method of claim 12, wherein the converting into the redirected memory address comprises: updating the memory command to a processing in memory (PIM) command that is mapped to the corresponding designated memory address, based on the mapping information that maps each of the predetermined designated memory addresses to the redirected memory address and a PIM command to be executed at the redirected memory address [The rationale in the rejection of claim 7 is herein incorporated].
19. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 12 [The rationale in the rejection of claim 12 is herein incorporated].
20. A memory device comprising: a routing register configured to store mapping information that maps each of predetermined designated memory addresses representing a first region of a memory to a redirected memory address representing a second other region of the memory; and [Kotra teaches “the memory controller 140 includes a PIM register mapping table 142 to facilitate the use of the PIM register file 118 for expediting non-PIM instructions. The PIM register mapping table 142 maps memory locations to PIM registers. For example, to utilize a PIM register as a write buffer for a non-PIM instruction, the memory controller logic 130 remaps (since the address is remapped, it corresponds to the claimed redirected memory address) the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register.” (par. 0040) (see fig. 1 and related text) where memory device 312 includes PIM registers in PIM unit 352 and physical memory location within a memory row 356 of memory array 350 (see fig. 4 and related text) thus, both the PIM registers and physical address locations in the memory device represent partial areas of the memory device 312 (see pars. 0041, 0051, 0059 and 0064)]
a selection logic configured to determine whether an input memory address received in a memory command corresponds to a given address among the designated memory addresses, [Kotra teaches “ the memory controller logic 130 remaps the write destination of the write data from the target memory location of the non-PIM write instruction to a PIM register. The memory controller logic 130 writes the write data to the PIM register using a PIM write command and updates the PIM register mapping table 142 to include an association between that PIM register and the target memory location… Similarly, for example, to utilize a PIM register as an early fetch or prefetch buffer, the memory controller logic 130 loads data from a memory location into a PIM register and updates the PIM register mapping table 142 to include an association between the PIM register and the memory location. When a non-PIM read instruction hits on the PIM register mapping table 142 (i.e., the target memory location of the non-PIM read instruction matches a memory location in the PIM register mapping table 142), the source of the non-PIM read instruction is remapped from the target memory location of the non-PIM read instruction to the PIM register associated with that memory location, and the data is read from the PIM register using a PIM read command.” (par. 0040) thus addresses are remapped or redirected from target memory locations to PIM register locations within the memory device]]
based on some bits of the input memory address, [Kotra teaches “In some examples, the PIM register mapping table 142 includes multiple entries, where each entry maps a PIM register index to a memory location.” (par. 0040) “ In such an example, the PIM register mapping table 142 can be organized as a K-way set associative cache (K<N) with a number of sets equal to M. The index bits can be provided by the DRAM bank select bits (from the physical address of a memory instruction) (thus, corresponding to some bits of the input memory address). The remaining physical address bits can serve as a tag. The PIM register index can be stored in each PIM register mapping table entry. “ (par. 0041)]
wherein the memory device executes the memory command at the input memory address in response to the determination that the input memory address does not correspond to the given address, and wherein, in response to the memory command being executed at the redirected memory address, [Kotra teaches “the memory controller logic 130 drains write instructions to the PIM register file 118 using PIM write commands.” (par. 0034) “the memory controller 310 migrates the first data 322 to the first memory location using a PIM store command. For example, the PIM store command specifies the register index of the PIM register 326 that holds the data 322 and the memory location 324 that is the destination for the write instruction 320.” (par. 0049) where “the memory controller logic 130 uses the PIM register file 118 as a memory side cache or prefetch buffer. For example, the memory controller logic 130 can prepopulate, based on a speculative algorithm, the PIM register file 118 with data loaded using a PIM load command. If a non-PIM read instruction hits on the memory side cache, the memory controller logic can read the requested data from the PIM register file 118 using a PIM read command, which is faster than reading from the memory array because there is no need to open a memory row.” (par. 0039; see par. 0040) “the memory controller 610 reads the data 622 held in the PIM register 626 instead of dispatching the non-PIM read instruction to the memory device 612. In some examples, the memory controller 610 reads the data 622 by dispatching a PIM read command.” (par. 0059) thus, for data not in the PIM register, the memory array is read].
the memory device executes an instruction of a processing in memory (PIM) program, [Kotra teaches “[0032]… the memory controller 140 dispatches PIM commands that are not based on a PIM instruction received from the processor 132. That is, the memory controller 140 dispatches PIM commands to manage the PIM register file 118 for expediting non-PIM instructions. In some examples, PIM read commands and PIM write commands, along with PIM load commands and PIM store commands, are employed by the memory controller 140 to execute non-PIM read instructions and non-PIM write instructions using the PIM register file 118. Thus, teaching PIM operations for non-PIM memory commands].
Kotra does not expressly disclose the execution of the PIM program for the converted redirected memory address, using an operand stored at the converted redirected memory address to perform an arithmetic operation; however, regarding these limitations, C. H. Kim teaches [“The PIM device driver stores the PIM source and destination operand addresses and their read/write attributes in the PIM memory device’s configuration area before starting the PIM execution. The PIM device compares all incoming memory requests with the stored addresses and identifies the PIM requests. The operations for the PIM and non-PIM memory requests are the same except for handling the datapath. “ (Section 1) “ The PIM device compares the address of the incoming memory request with the stored operand information for identifying it as the PIM request. The PIM engine computes using the configuration information at every incoming PIM request.” (Section 3) “5) Arithmetic operation (MAC, ADD, SUB, MUL)… The PIM RD/WR command performs the standard memory request service also with the PIM execution. If the PIM RIU recognizes the PIM RD command, it turns on the bus switch connected to the PIM datapath. For example, the RD command matched to src0 operand (REG A) or src1 operand (REG B) stores the data read from the bank in vecA and vecB, respectively. Also, in PIM WR (matching the address of the destination operand in REG C), the PIM RIU turns on the bus switch and stores the accumulator registers to the bank instead of the data expressed in the write memory request. MOV ISA defines data movement from the general registers into vACC with mantissa expansion. CSTB ISA broadcasts one scalar from a vector register to the source of the entire MACs for vector-matrix multiplication.” (Section 4.1) “ the Silent-PIM architecture, performing inside DRAM with standard DRAM memory requests, and presented how the entire architecture layers, including applications, operating systems, and PIM devices to perform the computation. “ (Section 8)].
Kotra and C. H. Kim are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Kotra to include the execution of the PIM program for the converted redirected memory address, using an operand stored at the converted redirected memory address to perform an arithmetic operation as taught by C. H. Kim since doing so would provide the benefits of [“To the best of our knowledge, our study in this paper is first to propose a PIM architecture that does not require any modification of hardware components except for the PIM DRAM device itself. It implies that we can control the PIM device and perform the PIM computation only with standard memory requests by complying with the standard DRAM interface [17], i.e., preserving the DRAM standard operation semantics and their timing constraints.” (Section 1)].
Therefore, it would have been obvious to combine Kotra and C. H. Kim for the benefit of creating a storage system/method to obtain the invention as specified in claim 20.
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant's arguments filed on 5/7/2026 have been fully considered but are moot in view of the new ground(s) of rejection.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received an action on the merits and are subject to a final rejection.
b. DIRECTION OF FUTURE CORRESPONDENCES
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June 1, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
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