DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 6-7, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okayama et al. (US 2019/0058468).
In regard to Claim 1:
Okayama discloses, in Figure 1, a semiconductor device, comprising:
a first gate electrode (2U gate electrode), a second gate electrode (2V gate electrode), and a third gate electrode (2W gate electrode),
the first gate electrode (2U gate electrode), the second gate electrode (2V gate electrode), and the third gate electrode (2W gate electrode) being configured to be controlled independently from each other (6U, 6V, 6W control 2U, 2V, 2W respectively),
an on-period of the second gate electrode (2V gate electrode) being shorter than an on-period of the first gate electrode (2U gate electrode) in a period from when the first gate electrode is turned on until the first gate electrode is turned off (Paragraph 0057),
an on-period of the third gate electrode (2W gate electrode) being shorter than the on-period of the second gate electrode (2V gate electrode) in the period from when the first gate electrode is turned on until the first gate electrode is turned off (Paragraph 0059),
a timing at which a third gate voltage of the third gate electrode (2W gate electrode) reaches a third threshold voltage and a start timing of a third Miller period of the third gate voltage being within a first Miller period of a first gate voltage of the first gate electrode (2U gate electrode) and within a second Miller period of a second gate voltage of the second gate electrode (2V electrode; Paragraph 0060).
In regard to Claim 3:
Okayama discloses, in Figure 1, the semiconductor device according to claim 1, wherein the semiconductor device includes an IGBT (Insulated Gate Bipolar Transistor) (Paragraph 0053).
In regard to Claim 4:
Okayama discloses, in Figure 1, a semiconductor device, comprising:
a first gate electrode (2U gate electrode) and a second gate electrode (2V gate electrode), the first gate electrode and the second gate electrode being configured to be controlled independently from each other (6U controls 2U and 6V controls 2V),
an on-period of the second gate electrode (2V gate electrode) being shorter than an on-period of the first gate electrode (2U gate electrode) in a period from when the first gate electrode is turned on until the first gate electrode is turned off (Paragraph 0057),
a timing at which a second gate voltage of the second gate electrode (2V gate electrode) reaches a second threshold voltage and a start timing of a second Miller period of the second gate voltage being within a first Miller period of a first gate voltage of the first gate electrode (2U gate electrode; Paragraph 0060).
In regard to Claim 6:
Okayama discloses, in Figure 1, the semiconductor device according to claim 4, wherein the semiconductor device includes an IGBT (Insulated Gate Bipolar Transistor) (Paragraph 0053).
In regard to Claim 7:
Okayama discloses, in Figure 1, a semiconductor module, comprising: the semiconductor device according to claim 1 (see the rejection of Claim 1 above); and a drive circuit (6U, 6V, 6W) electrically connected with the first, second, and third gate electrodes (2U, 2V, 2W respectively).
In regard to Claim 9:
Okayama discloses, in Figure 1, a semiconductor module, comprising: the semiconductor device according to claim 4 (see the rejection of Claim 4 above); and a drive circuit (6U, 6V) electrically connected with the first and second gate electrodes (2U, 2V respectively).
Allowable Subject Matter
Claims 2, 5, 8, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sato (US 2022/0014184) discloses an electronic circuit, including a first switching device that contains a first semiconductor material with a first band gap, and a second switching device that is coupled in parallel to the first switching device, and contains a second semiconductor material with a second band gap smaller than the first band gap. Each of the first and second switching devices has a control electrode, and the control electrode of the first switching device is coupled to the control electrode of the second switching device.
Shoda (US 2009/0059999) discloses A temperature detection circuit includes: a voltage generator that is connected to a first voltage line having first voltage and a second voltage line having second voltage and to output a third voltage to a third voltage line, the third voltage being obtained by transforming the first voltage to be stepped down as an ambient temperature becomes higher; and a detecting unit that includes: a delay section that is connected to the second voltage line and the third voltage line and to receive a pulse signal, the delay section being configured to output a delayed pulse signal that is obtained by delaying the pulse signal for a delay time set to be longer as the third voltage becomes lower; and a temperature detecting section that is configured to: receive the delayed pulse signal and the pulse signal; latch the delayed pulse signal based on the pulse signal; output the latched signal as a detection result.
Mamitsu (US 2008/0117557) discloses a power semiconductor device includes a power semiconductor element, a protection circuit, an inspection terminal, and an electrical conductor. The protection circuit includes multiple zener diodes connected in series between a gate and an emitter of the power semiconductor element. The protection circuit limits a voltage between the gate and emitter of the power semiconductor element, when an abnormal voltage is applied to the gate. The electrical conductor electrically connects the inspection terminal to a node between the zener diodes of the protection circuit. The zener diodes are separately inspected by using the inspection terminal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2896