DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/31/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-8, 10-11, 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Minato (US 2021/0294529) and further in view of Na (US 2022/0197561).
As per claims 1 and 15, Minato teaches a nonvolatile memory device (Minato: fig. 2, item 24)/a method of operating nonvolatile memory device (par. [0028]) comprising:
processing circuitry (Minato: fig. 2, item 52, logic control circuit) configured to receive a read command (Minato: par. [0094]: “the controller 22 transmits a read command sequence”), a start read address, and [[a data chunk indicator]], the read command including a page read command (according to current disclosure par. [0045] page read command may include “00h” and “30h”’ and data read command Minato fig. 7A shows the read sequence “00h” and “30h”) and a data read command (Minato: fig. 7B: data output command), and the start read address including a start row address and a start column address (Minato: fig. 7A; par. [0095]: “The row address RA indicates the address of the page from which data is to be read by the read command sequence. The column address CA indicates the address of the storage location at the beginning of the data to be read within the page”);
a memory cell array (Minato: fig. 2, item 78) configured to output first page data based on the start row address, the first page data (it is inherent that the page data read from the memory cell array is output based on the read command).
Minato fails to teach the data read command including a data chunk indicator and a memory cell array configured to output first page data based on the start row address, the first page data including a plurality of first data chunks; and the processing circuitry further configured to output one or more of the plurality of first data chunks based on the data chunk indicator.
Na teaches a read command including a data chunk indicator and a memory cell array configured to output first page data based on the start row address, the first page data including a plurality of first data chunks; and the processing circuitry further configured to output one or more of the plurality of first data chunks based on the data chunk indicator. (Na: fig. 2, pars. [0096] and [0097] teaches that the memory blocks MB1, MB2 are divided into pages PAGE1, PAGE2 and the pages further divided into sub-page or chunks SP0, SP1, SP2 and SP3. Na in par. [0073] teaches that memory controller may provide the memory device with the read command and physical addresses, par. [0058] teaches that the physical address may include plane number, a block number, page number and a sub-page number, means a read command with physical address includes a chunk indicator/a sub-page number; Na: fig. 11, shows the command SP read (index 0) which reads page 5 (PG5) from block 100 and reads two chunks S0 and S3 using the read command). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a chunk indicator with read command and output multiple chunks as taught by Na in the system Minato to improve read performance of the system (Na: par. [0006]).
As per claim 2, Minato and Na expressly fail to teach wherein the plurality of first data chunks correspond to a plurality of read address ranges, respectively; and the processing circuitry is further configured to continuously output two or more of the plurality of first data chunks. However, Na teaches (par. [0096]) that the sub-page (chunk) size can be determining based on the size of the page and therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention select the chunk size as the read address range required for the optimal system configurations.
As per claim 3, Minato and Na teach wherein the plurality of read address ranges include two or more discontinuous address ranges of the memory cell array. (Na: fig. 11, the sub-pages S0 and S3 are discontinuous address ranges).
As per claims 6 and 16, Minato and Na teach wherein the processing circuitry is further configured to: receive the page read command and the start read address; and receive the data read command and the data chunk indicator. Minato figs. 7 and 8 teach reading data of page n to page buffer and then the data read command to read page of data and Na teaches reading sub-pages of data from the page buffer based on sub-page or chunk indicator.
As per claims 7 and 17, Minato and Na teach wherein the page read command includes a first read command and a second read command; and the data read command includes a third read command and a fourth read command. Minato figs. 8A, 8B, 8C teaches reading pages n, n+1 sequentially and outputting read data (figs. 9A, 9B), which teaches providing multiple page read and data read commands to read sequential data from the memory array and output the read data from the page buffer to memory controller.
As per claim 8, Minato and Na teach wherein the processing circuitry is further configured to: sequentially receive the third read command, the data chunk indicator, and the fourth read command. It is inherent that the memory device can sequentially receive multiple read commands with chunk indicators (Na: figs. 8 and 10 shows command queue with multiple read commands and sub-page indicators).
As per claim 10, Minato and Na teach wherein, before the read command is received, the processing circuitry is further configured to: receive a chunk size indicator indicating a size of each of the plurality of first data chunks (Na: par. [0096]: taught as pages are divided into virtual sub-pages according to read unit and it may be determined based on size of page and number of sub-pages, which means the page is divided into chunk sizes based on requirement).
As per claim 11, Minato and Na expressly fail to teach wherein, in response to the nonvolatile memory device being initialized or powered on, the processing circuitry is further configured to: receive the chunk size indicator; and store the chunk size indicator. However, as explained above with respect to claim 10 above, the page is divided into sub-pages based on read unit size and page size, where it would be readily apparent to one having ordinary skill in the art to receive the sub-page (chunk) size indicator and store the chunk size indicator such that when the read requests are issued, the correct amount of data can be read from the memory.
As per claim 14, Minato and Na teach wherein the memory cell array is configured to output block data or plane data based on the start row address, the block data including a plurality of first block data chunks, and the plane data including a plurality of first plane data chunks; and the processing circuitry is further configured to sequentially output two or more of the plurality of first block data chunks or two or more of the plurality of first plane data chunks based on the data chunk indicator (Na: pars. [0168] – [0176] teach read commands with plane numbers, block numbers and sub-page numbers and sub-pages are output based on the address provided).
As per claim 18, Minato and Na teach wherein the receiving the page read command and the start read address includes sequentially receiving the first read command, the start read address, and the second read command; and the receiving the read command and the data chunk indicator includes sequentially receiving the third read command, the data chunk indicator, and the fourth read command. It is inherent that the memory device can sequentially receive multiple read commands with chunk indicators (Na: figs. 8 and 10 shows command queue with multiple read commands and sub-page indicators where sequential page read commands with start address is provided to read data from sequential pages to the page buffer and then subsequent data read commands are provided to output sub-pages of data from the page buffer to the controller).
As per claim 20, Minato and Na teach a memory system (Minato: fig. 1) comprising: a memory controller (Minato: fig. 1, item 22) configured to output a read command, a start read address, and a data chunk indicator, the read command including a page read command and a data read command, and the start read address including a start row address and a start column address; and a nonvolatile memory device configured to operate based on the read command, the start read address, and the data chunk indicator, the nonvolatile memory device including, a memory cell array configured to output first page data based on the start row address, the first page data including a plurality of first data chunks, and a page buffer circuit configured to continuously output two or more of the plurality of first data chunks based on the data chunk indicator. The limitations of the claim 20 are similar in scope with claim 1 above and thus rejected under same rationales as applied to claim 1 above.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Minato (US 2021/0294529) and Na (US 2022/0197561) as applied to claim 1 above, and further in view of Fu et al. (US 2024/0086317).
As per claim 4, Minato and Na fail to teach wherein the data chunk indicator includes binary data indicating one or more of the plurality of first data chunks.
Fu teaches sending command with bitmaps to selectively read valid data chunks from the page of the memory device (Fu: fig. 2, pars. [0006], [0019]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a read command with the chunk indicator using binary data to identify data to be read from the page buffer as taught by Fu to provide an efficient way of the reading selected sub-pages of the data from the memory (Fu: par. [0004]).
As per claim 5, Minato, Na and Fu teach wherein a number of the plurality of first data chunks is N, wherein N is an integer of 2 or more; and the data chunk indicator has a size of N-bits. (Fu: fig. 2 shows shaded sub-pages with valid data to be read by providing bitmap, for example page j has 2 sub-pages in plane 0).
Claims 9, 12-13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Minato (US 2021/0294529) and Na (US 2022/0197561) as applied to claims 7 and 15 above, and further in view of Endo (US 2022/0084568) and Jeong et al. (US 2022/0365842).
As per claims 9 and 19, Minato and Na teach wherein the processing circuitry is further configured to: sequentially receive the first read command, the start read address, the second read command, the third read command, the data chunk indicator, and the fourth read command (Na: figs. 8 and 10 shows command queue with multiple read commands and sub-page indicators where sequential page read commands with start address is provided to read data from sequential pages to the page buffer and then subsequent data read commands are provided to output sub-pages of data from the page buffer to the controller). Minato and Na expressly fail to teach and in response to a desired time period elapsing from a time the nonvolatile memory device received the fourth read command, sequentially output two or more of the plurality of first data chunks. Endo teaches sequentially output two or more of the plurality of first data chunks (Endo: par. [0084]: “In the page transfer mode, the NANDC 14 transfers data in units of pages by toggling the read enable signal pair RE/REn by the number of times corresponding to the size of the page”).
Jeong teaches in response to a desired time period elapsing from a time the nonvolatile memory device received the fourth read command (Jeong: par. [0154]). The process of providing read enable signal pair and toggling to read data as taught by Endo and generating data strobe signal DQS after predetermined delay based on read enable signal to read data as taught by Jeong is well-known in the art to provide data aligned with the toggle time point of data strobe to capture valid data during a read operation and ignoring noise. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide read enable signal to generate data strobe at predetermined time to capture valid data during data read operation from the memory.
As per claim 12, Minato, Na, Endo and Jiang teach wherein the processing circuitry is further configured to: receive a read enable signal which toggles based on a size of each of the plurality of first data chunks; and generate a data strobe signal which toggles based on the read enable signal. Endo teaches sequentially output two or more of the plurality of first data chunks (Endo: par. [0084]: “In the page transfer mode, the NANDC 14 transfers data in units of pages by toggling the read enable signal pair RE/REn by the number of times corresponding to the size of the page”).
Jeong teaches generating a data strobe signal which toggles based on the read enable signal (Jeong: par. [0154]). The process of providing read enable signal pair and toggling to read data as taught by Endo and generating data strobe signal DQS after predetermined delay based on read enable signal to read data as taught by Jeong is well-known in the art to provide data aligned with the toggle time point of data strobe to capture valid data during a read operation and ignoring noise. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide read enable signal to generate data strobe at predetermined time to capture valid data during data read operation from the memory.
As per claim 13, Minato, Na, Endo and Jiang teach wherein the processing circuitry is further configured to: output one or more of the plurality of first data chunks based on the data chunk indicator and the data strobe signal. Endo teaches sequentially output two or more of the plurality of first data chunks (Endo: par. [0084]: “In the page transfer mode, the NANDC 14 transfers data in units of pages by toggling the read enable signal pair RE/REn by the number of times corresponding to the size of the page”)
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Arya et al. (US 2010/0125444) teaches a memory device divided into a plurality of pages and each page is divided into plurality of sectors and reading data from the sectors.
Lee et al. (US 2009/0024791) teaches a solid state disk controller selectively reading sectors of the page using bit map values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138
Prosecution Insights