Detailed Action
summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on April 04, 2025.
2. Claims 1-21 previously cancelled and claims 22-40 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 06/03/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 22-30,34-37 and 39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-21 of U.S. Patent No. 12237774. Although the claims at issue are not identical, they are not patentably distinct from each other because patented claims anticipates examined claims
Conflicting claims US Patent 12237774
Conflicting claims Case No 19006534
Claim 1:
A system for detecting a power, the system comprising: a first signal converter configured to receive a first signal and generate a pulse-width-modulation signal based at least in part on the first signal; a second signal converter configured to receive a second signal and generate a voltage signal based at least in part on the second signal; and a low-pass filter configured to receive the pulse-width-modulation signal and the voltage signal and generate a power detection signal based at least in part on the pulse-width-modulation signal and the voltage signal; wherein: the first signal is either an input current or an input voltage; the second signal is either the input current or the input voltage; and the first signal and the second signal are different; Wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes linearly with the input power in magnitude.
Claim 22:
A system for detecting a power, the system comprising: a first signal converter configured to receive a first signal and generate a logic signal based at least in part on the first signal; a second signal converter configured to receive a second signal and generate a third signal based at least in part on the second signal; and a signal generator configured to receive the logic signal and the third signal and generate a power detection signal based at least in part on the logic signal and the third signal; wherein: the first signal is either an input current or an input voltage; the second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes with the input power in magnitude.
2. The system of claim 1 wherein: if the input power increases, the power detection signal increases linearly with the input power in magnitude; and if the input power decreases, the power detection signal decreases linearly with the input power in magnitude.
23. The system of claim 22 wherein: if the input power increases, the power detection signal increases linearly with the input power in magnitude; and if the input power decreases, the power detection signal decreases linearly with the input power in magnitude.
3. The system of claim 1 wherein: the first signal converter is further configured to change a duly cycle of the pulse-width-modulation signal linearly with the first signal in magnitude; wherein: if the first signal increases in magnitude, the duty cycle increases linearly with the first signal; and if the first signal decreases in magnitude, the duty cycle decreases linearly with the first signal.
24. The system of claim 22 wherein: the logic signal is a pulse-width-modulation signal; the first signal converter is further configured to change a duty cycle of the pulse- width-modulation signal linearly with the first signal in magnitude; wherein :if the first signal increases in magnitude, the duty cycle increases linearly with the first signal; and if the first signal decreases in magnitude, the duty cycle decreases linearly with the first signal.
4. The system of claim 3 wherein the first signal converter is further configured to, even if the cycle changes, keep a frequency of the pulse-width-modulation signal constant.
25. (New) The system of claim 24 wherein the first signal converter is further configured to, even if the duty cycle changes, keep a frequency of the pulse-width- modulation signal constant.
5. The system of claim 1 wherein: the second signal converter is further configured to change the voltage signal linearly with the second signal in magnitude; wherein: if the second signal increases in magnitude, the voltage signal increases with the second signal; and if the second signal decreases in magnitude, the voltage signal decreases with the second signal.
26. (New) The system of claim 22 wherein: the third signal is a voltage signal; the second signal converter is further configured to change the voltage signal linearly with the second signal in magnitude; wherein: if the second signal increases in magnitude, the voltage signal increases with the second signal; and if the second signal decreases in magnitude, the voltage signal decreases with the second signal.
6. The system of claim 1 wherein, if the first signal is the input voltage and the second signal is the input current, the first signal converter is a voltage-to-duty-cycle converter and the second signal converter is a current-to-voltage converter.
27. The system of claim 22 wherein, if the first signal is the input voltage and the second signal is the input current, the first signal converter is a voltage-to- duty-cycle converter and the second signal converter is a current-to-voltage converter.
7. The system of claim 1 wherein, if the first signal is the input current and the second signal is the input voltage, the first signal converter is a current-to-duty-cycle converter and the second signal converter is a voltage-to-voltage converter.
28. The system of claim 22 wherein, if the first signal is the input current and the second signal is the input voltage, the first signal converter is a current-to- duty-cycle converter and the second signal converter is a voltage-to-voltage converter.
8. The system of claim 1 wherein: the input current represents an output current of a power converter; and the input voltage represents an output voltage of the power converter; wherein: the input current changes linearly with the output current of the power converter; and the input voltage charges linearly with the output voltage of the power converter.
29The system of claim 22 wherein: the input current represents an output current of a power converter; and the input voltage represents an output voltage of the power converter; wherein: the input current changes linearly with the output current of the power converter; and the input voltage changes linearly with the output voltage of the power converter.
9. The system of claim 8 wherein: the power detection signal represents an output power of the power converter, the output power being equal to the output current multiplied by the output voltage; and the power detection signal changes linearly the output power of the power converter in magnitude.
30. The system of claim 29 wherein: the power detection signal represents an output power of the power converter, the output power being equal to the output current multiplied by the output voltage; and the power detection signal changes linearly with the output power of the power converter in magnitude.
10. A system for detecting a power, the system comprising: a first signal converter configured to receive a first signal and generate a logic signal based at least in part on the first signal; a second signal converter configured to receive a second signal and generate a current signal based at least in part on the second signal; and a signal generator configured to receive the logic signal and the current signal and generate a power detection signal based at least in part on the logic signal and the current signal; wherein: the first signal is either an input current or an input voltage; the second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes linearly with the input power in magnitude.
22. A system for detecting a power, the system comprising: a first signal converter configured to receive a first signal and generate a logic signal based at least in part on the first signal; a second signal converter configured to receive a second signal and generate a third signal based at least in part on the second signal; and a signal generator configured to receive the logic signal and the third signal and generate a power detection signal based at least in part on the logic signal and the third signal; wherein: the first signal is either an input current or an input voltage; the second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes with the input power in magnitude.
11. The system of claim 10 wherein: if the input power increases, the power detection signal increases linearly with the input power in magnitude; and if the input power decreases, the power detection signal decreases linearly with the input power in magnitude.
23. The system of claim 22 wherein: if the input power increases, the power detection signal increases linearly with the input power in magnitude; and if the input power decreases, the power detection signal decreases linearly with the input power in magnitude.
12. The system of claim 10 wherein: the first signal converter is further configured to change a pulse width of the logic signal linearly with the first signal in magnitude; wherein: if the first signal increases in magnitude, the pulse width increases linearly with the first signal; and if the first signal decreases in magnitude, the pulse width decreases linearly with the first signal.
33. The system of claim 31 wherein: the first signal converter is further configured to change a pulse width of the logic signal linearly with the first signal in magnitude; wherein: if the first signal increases in magnitude, the pulse width increases linearly with the first signal; and if the first signal decreases in magnitude, the pulse width decreases linearly with the first signal.
13. The system of claim 12 wherein: the logic signal changes between a logic high level and a logic low level; the pulse width represents a time duration when the logic signal is at the logic high level; and an off time represents a time duration when the logic signal is at the logic low level.
34. The system of claim 33 wherein: the logic signal changes between a logic high level and a logic low level; the pulse width represents a time duration when the logic signal is at the logic high level; and an off time represents a time duration when the logic signal is at the logic low level.
14. The system of claim 13 wherein: the first signal converter is further configured to, even if the pulse width changes, keep the off time of the logic signal constant.
35 .The system of claim 34 wherein: the first signal converter is further configured to, even if the pulse width changes, keep the off time of the logic signal constant.
15. The system of claim 10 wherein: the second signal converter is further configured to change the current signal linearly with the second signal in magnitude; wherein: if the second signal increases in magnitude, the current signal increases with the second signal; and if the second signal decreases in magnitude, the current signal decreases with the second signal.
36. (The system of claim 31 wherein: the third signal is a current signal; the second signal converter is further configured to change the current signal linearly with the second signal in magnitude; wherein: if the second signal increases in magnitude, the current signal increases with the second signal; and if the second signal decreases in magnitude, the current signal decreases with the second signal
16. The system of claim 10 wherein, if the first signal is the input voltage and the second signal is the input current, the first signal converter is a voltage-to-pulse-width converter and the second signal converter is a current-to-current converter.
37. (New) The system of claim 31 wherein, if the first signal is an input voltage and the second signal is an input current, the first signal converter is a voltage-to-pulse-width converter; the second signal converter is a current-to-current converter; and the input power is equal to the input current multiplied by the input voltage.
17. The system of claim 10 wherein, if the first signal is the input current and the second signal is the input voltage, the first signal converter is a current-to-pulse-width converter and the second signal converter is a voltage-to-current converter.
38. (New) The system of claim 31 wherein, if the first signal is an input current and the second signal is an input voltage, the first signal converter is a current-to- pulse-width converter and the second signal converter is a voltage-to-current converter, the input power is equal to the input current multiplied by the input voltage.
18. The system of claim 10 wherein: the input current represents an output current of a power converter; and the input voltage represents an output voltage of the power converter; wherein: the input current changes linearly with the output current of the converter; and the input voltage changes linearly with the output voltage of the power converter.
29. (New) The system of claim 22 wherein: the input current represents an output current of a power converter; and the input voltage represents an output voltage of the power converter; wherein: he input current changes linearly with the output current of the power converter; and the input voltage changes linearly with the output voltage of the power converter.
19. The system of claim 18 wherein: the power detection signal represents an output power of the power converter, the output power being equal to the output current multiplied by the output voltage; and the power detection signal changes linearly with the output power of the power converter in magnitude.
30. (New) The system of claim 29 wherein: the power detection signal represents an output power of the power converter, the output power being equal to the output current multiplied by the output voltage; and the power detection signal changes linearly with the output power of the power converter in magnitude.
20. A method for detective a power, the method comprising: receiving a first signal; generating a pulse-width-modulation signal based at least in part on the first signal; receiving a second signal; generating a voltage signal based at least in part on the second signal; receiving the pulse-width-modulation signal and the voltage signal; and generating a power detection signal based at least in part on the pulse-width-modulation signal and the voltage signal, the power detection signal being equal to the voltage signal multiplied by a duty cycle of the pulse-width-modulation signal; wherein: the first signal is either an input current or an input voltage; the second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes linearly with the input power in magnitude.
39. (New) A method for detecting a power, the method comprising: receiving a first signal; generating a logic signal based at least in part on the first signal; receiving a second signal; generating a third signal based at least in part on the second signal; receiving the logic signal and the third signal; and generating a power detection signal based at least in part on the logic signal and the third signal; wherein:the first signal is either an input current or an input voltage;the second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes with the input power in magnitude.
21. A method for detecting a power, the method comprising: receiving a first signal; generating a logic signal based at least in part on the first signal; receiving a second signal; generating a current signal based at least in part on the second signal; receiving the logic signal and the current signal; and generating a power detection signal based at least in part on the logic signal and the current signal, the power detection signal being equal to the current signal multiplied by a pulse width of the logic signal and also multiplied by a predetermined constant; wherein: the first signal is either an input current or an input voltage; the second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes linearly with the input power in magnitude. second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes linearly with the input power in magnitude.
Claim 22 + claim 23:
A system for detecting a power, the system comprising: a first signal converter configured to receive a first signal and generate a logic signal based at least in part on the first signal; a second signal converter configured to receive a second signal and generate a third signal based at least in part on the second signal; and a signal generator configured to receive the logic signal and the third signal and generate a power detection signal based at least in part on the logic signal and the third signal; wherein: the first signal is either an input current or an input voltage; the second signal is either the input current or the input voltage; and the first signal and the second signal are different; wherein: the power detection signal represents an input power that is equal to the input current multiplied by the input voltage; and the power detection signal changes with the input power in magnitude.
Claim 23. The system of claim 22 wherein: if the input power increases, the power detection signal increases linearly with the input power in magnitude; and if the input power decreases, the power detection signal decreases linearly with the input power in magnitude.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 22-23, 26,29-32, 36 and 39-40 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by unpatentable over MA “CN 2703260”.
In re to claim 22, MA discloses a system for detecting a power (Figs. 1-5 : is a system for reactive power measurement), the system comprising: a first signal converter (Figs. 2: analogue/digital (A/D) conversion circuit 1. , see page 5, lines 7-20 ) configured to receive a first signal ( receiving the current channel 1, see page 5, lines 7-20 ) and generate a logic signal based at least in part on the first signal (Fig.2: output from low-pass filter circuit 3 to multiplier 6 is a logic signal based on the output signal from A/D conversion circuit 1) ;
a second signal converter ( analog/digital (A/D) conversion circuit 4) configured to receive a second signal (receiving the voltage channel, see page 5, lines 7-20) and generate a third signal based at least in part on the second signal (output from phase compensation circuit 5 respectively receives the low-pass filter circuit to the multiplier 6 is a signal generated based on A/D conversion circuit 4, see page 5, lines 7-20); and
a signal generator (digital multiplier 6, see page 5, lines 7-20) configured to receive the logic signal (output signal from low-pass filter circuit 3) and the third signal (output from phase compensation circuit 5) and generate a power detection signal ( phase compensation circuit to current signal and voltage signal multiplied by the digital multiplier 6. with the multiplier 6 for filtering transient power in alternating current quantity of the low-pass filter circuit 7, 7 connected with the low-pass filter circuit is used for converting the average power output is the digital/frequency conversion circuit, see page 5, lines 18-24. Examiner noted that the average power output is equivalent to power detection signal) based at least in part on the logic signal (output from 3) and the third signal ( output from phase compensation 5) ; wherein: the first signal is either an input current or an input voltage (Fig.2 : A/D conversion circuit 1 is receiving current channel 1 ) ;
the second signal is either the input current or the input voltage (Fig.2 : A/D conversion circuit 4 is receiving voltage channel) ; and
the first signal and the second signal are different (current and voltage channel are different) ; wherein:
the power detection signal represents an input power that is equal to the input current (current channel to A/D 1) multiplied by the input voltage (voltage channel to A/D 4) ; and the power detection signal changes with the input power in magnitude (it is understood/implicit in the art that the basic formula for electrical power (P) in a circuit is Power equals Voltage times Current (P = V times I), thus when the value voltage or current increase, the power magnitude increase proportional or linearly and vise versal )
In re to claim 23, MA discloses (Figs. 1-5) if the input power increases, the power detection signal increases linearly with the input power in magnitude (P=V*I) ; and if the input power decreases, the power detection signal decreases linearly with the input power in magnitude (it is understood/implicit in the art that the basic formula for electrical power (P) in a circuit is Power equals Voltage times Current (P = V times I), thus when the average power output from the multiplier 6 increase based on the increase of voltage and current , thus the power magnitude increase proportional or linearly and vise versal )
.
In re to claim 26, MA discloses (Figs. 1-5) the third signal is a voltage signal (output from the low-pass filter circuit 3 to the multiplier 6 is a signal generated based on A/D conversion circuit 1) ; the second signal converter (A/D 4) is further configured to change the voltage signal linearly with the second signal in magnitude (increase or decrease of voltage channel at A/D 4 is linearly change output from compensation 5) ; wherein: if the second signal increases in magnitude, the voltage signal increases with the second signal; and if the second signal decreases in magnitude, the voltage signal decreases with the second signal (it is understood in the art that when the magnitude of the voltage channel increase the output from compensation channel increase and vise vera) .
In re to claim 29, MA discloses (Figs. 1-5) the input current (current channel 1) represents an output current of a power converter (it is understood that a reactive power measurement circuit is used in the power converter in technical field of power grid control ) ; and the input voltage (voltage channel input to A/D 4) represents an output voltage of the power converter; wherein: the input current changes linearly with the output current of the power converter (it is understood that input current channel to A/D 1 goes up or down, the output from LPF 3 changes by the exact same amount every single time) ; and the input voltage changes linearly with the output voltage of the power converter (it is understood that input voltage channel to A/D 4 goes up or down, the output from phase compensation circuit (5) changes by the exact same amount every single time because the input voltage channel determine the magnitude of average power at the multiplier).
In re to claim 29, MA discloses (Figs. 1-5): the power detection signal represents an output power (, see page 5, lines 18-24) of power converter (it is understood that a reactive power measurement circuit is used in the power converter in technical field of power grid control ), the output power being equal to the output current (current channel 1 to A/D 1 ) multiplied (6) by the output voltage (voltage channel to A/D 4) ; and the power detection signal changes linearly with the output power of the power converter in magnitude (it is understood that the magnitude of the input voltage and current channel to goes up or down, the output from multiplier 6 changes by the exact same amount every single time).
In re to claim 30, MA discloses (Figs. 1-5): the power detection signal (output from multiplier 6) represents an output power of the power converter (it is understood that a reactive power measurement circuit is used in the power converter in technical field of power grid control ) , the output power being equal to the output current multiplied by the output voltage ( phase compensation circuit to current signal and voltage signal multiplied by the digital multiplier 6. with the multiplier 6 for filtering transient power in alternating current quantity of the low-pass filter circuit 7, 7 connected with the low-pass filter circuit is used for converting the average power output is the digital/frequency conversion circuit, see page 5, lines 18-24); and the power detection signal changes linearly with the output power of the power converter in magnitude (it is understood the output from multiplier changes based on increase or decrease of voltage and current channel of A/D converter) .
In re to claim 31, MA discloses a system for detecting a power (Figs. 1-5 : is a system for reactive power measurement), the system comprising:
a first signal converter (Figs. 2: analogue/digital (A/D) conversion circuit 4) configured to receive a first signal ( A/D 4 is receiving the voltage channel 1 ) and generate a logic signal based at least in part on the first signal (Fig.2: output from phase compensation circuit 5 to the multiplier 6 is based on voltage channel of A/D 4 );
a second signal converter ( analog/digital (A/D) conversion circuit 1) configured to receive a second signal (receiving the current channel, see page 5, lines 7-20 ) and generate a third signal based at least in part on the second signal ( output from low-pass filter circuit 3 to multiplier 6 is a logic signal based on the output signal from A/D conversion circuit 1; see page 5, lines 7-20 ); and
a signal generator (digital multiplier 6, see page 5, lines 7-20 ) configured to receive the logic signal (output signal from phase compensation 5 ) and the third signal (output from pass filter circuit 3) and generate a power detection signal based at least in part on the logic signal and the third signal ( phase compensation circuit to current signal and voltage signal multiplied by the digital multiplier 6. with the multiplier 6 for filtering transient power in alternating current quantity of the low-pass filter circuit 7, 7 connected with the low-pass filter circuit is used for converting the average power output is the digital/frequency conversion circuit, see page 5, lines 18-24. Examiner noted that the average power output is equivalent to power detection signal );
wherein: the power detection signal represents an input power that is associated with the first signal (Fig.2 : A/D conversion circuit 4 is receiving voltage channel ) and second signal (Fig.2 : A/D conversion circuit 1 is receiving current channel 1); and the power detection signal changes with the input power in magnitude (it is understood/implicit in the art that the basic formula for electrical power (P) in a circuit is Power equals Voltage times Current (P = V times I), thus when the magnitude voltage or current increase, the power magnitude increase proportional or linearly and vise versal )
In re to claim 32, MA discloses (Figs. 1-5) if the input power increases, the power detection signal increases linearly with the input power in magnitude; and if the input power decreases, the power detection signal decreases linearly with the input power in magnitude (it is understood/implicit in the art that the basic formula for electrical power (P) in a circuit is Power equals Voltage times Current (P = V times I), thus when the average power output from the multiplier 6 increase is base on the increase of input channel of Voltage and current , thus the power magnitude increase proportional or linearly and vise versal )
In re to claim 36, MA discloses (Figs. 1-5) the third signal is a current signal (output from low-pass filter circuit 3 to multiplier 6 is a logic signal based on the output signal from A/D current conversion circuit 1) ; the second signal converter (A/D converter 1) is further configured to change the current signal linearly with the second signal in magnitude; wherein: if the second signal increases in magnitude, the current signal increases with the second signal; and if the second signal decreases in magnitude, the current signal decreases with the second signal (it is understood/implicit in the art when in input current channel increase , the output from at A/D 1 converter change linearly /proportionally at the output of LPF 3 and Vise versal ) .
In re to claim 39, MA discloses a method for detecting a power (Figs. 1-5 : is a method of calculating/detecting for reactive power measurement), the method comprising:
receiving a first signal ( A/D converter 1 is receiving the current channel 1 ); generating a logic signal based at least in part on the first signal (Fig.2: output from low-pass filter circuit 3 to multiplier 6 is a logic signal based on the output signal from A/D conversion circuit 1);
receiving a second signal (analog/digital (A/D) conversion circuit 4 is receiving voltage channel ); generating a third signal based at least in part on the second signal (output from phase compensation circuit 5 respectively receives the low-pass filter circuit to the multiplier 6 is a signal generated based on A/D conversion circuit 4, see page 5, lines 7-20);
receiving the logic signal and the third signal (digital multiplier 6 is receiving signals from the output of LPF 3 and phase compensation 5); and generating a power detection signal based at least in part on the logic signal and the third signal ( phase compensation circuit to current signal and voltage signal multiplied by the digital multiplier 6. with the multiplier 6 for filtering transient power in alternating current quantity of the low-pass filter circuit 7, 7 connected with the low-pass filter circuit is used for converting the average power output is the digital/frequency conversion circuit, see page 5, lines 18-24. Examiner noted that the average power output is equivalent to power detection signal);
wherein: the first signal is either an input current or an input voltage (Fig.2 : A/D conversion circuit 1 is receiving current channel 1 ) ;
the second signal is either the input current or the input voltage (Fig.2 : A/D conversion circuit 4 is receiving voltage channel) ; and
the first signal and the second signal are different (current and voltage channel are different);
wherein: the power detection signal represents an input power that is equal to the input current (current channel 1 to A/D1 ) multiplied by the input voltage (voltage channel to A/D 4) ; and the power detection signal changes with the input power in magnitude (it is understood/implicit in the art that the basic formula for electrical power (P) in a circuit is Power equals Voltage times Current (P = V times I), thus when the magnitude voltage or current increase, the power magnitude increase proportional or linearly and vise versal ).
In re to claim 40, MA discloses a method for detecting a power ((Figs. 1-5 : is a method of calculating/detecting for reactive power measurement),, the method comprising:
receiving a first signal ( A/D converter 1 is receiving the current channel 1 ); generating a logic signal based at least in part on the first signal (Fig.2: output from low-pass filter circuit 3 to multiplier 6 is a logic signal based on the output signal from A/D conversion circuit 1);
receiving a second signal (analog/digital (A/D) conversion circuit 4 is receiving voltage channel ); generating a third signal based at least in part on the second signal (output from phase compensation circuit 5 respectively receives the low-pass filter circuit to the multiplier 6 is a signal generated based on A/D conversion circuit 4, see page 5, lines 7-20);
receiving the logic signal and the third signal (digital multiplier 6 is receiving signals from the output of LPF 3 and phase compensation 5); and generating a power detection signal based at least in part on the logic signal and the third signal ( phase compensation circuit to current signal and voltage signal multiplied by the digital multiplier 6. with the multiplier 6 for filtering transient power in alternating current quantity of the low-pass filter circuit 7, 7 connected with the low-pass filter circuit is used for converting the average power output is the digital/frequency conversion circuit, see page 5, lines 18-24. Examiner noted that the average power output is equivalent to power detection signal);
the power detection signal (see page 5, lines 18-24) changes with the input power in magnitude (it is understood/implicit in the art that the basic formula for electrical power (P) in a circuit is Power equals Voltage times Current (P = V times I), thus when the of voltage or current increase, the power magnitude increase proportional or linearly and vise versal ).
Allowable Subject Matter
7. Claims 24-25 27-28 and 33-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 24 is objected because the prior art in the records fails to discloses or suggest the system including the limitation of “the logic signal is a pulse-width-modulation signal; the first signal converter is further configured to change a duty cycle of the pulse- width-modulation signal linearly with the first signal in magnitude; wherein: if the first signal increases in magnitude, the duty cycle increases linearly with the first signal; and if the first signal decreases in magnitude, the duty cycle decreases linearly with the first signal.”
Claim 27 is objected because the prior art in the records fails to discloses or suggest the system including the limitation of “if the first signal is the input voltage and the second signal is the input current, the first signal converter is a voltage-to- duty-cycle converter and the second signal converter is a current-to-voltage converter” .
Claim 28 is objected because the prior art in the records fails to discloses or suggest the system including the limitation of “if the first signal is the input current and the second signal is the input voltage, the first signal converter is a current-to- duty-cycle converter and the second signal converter is a voltage-to-voltage converter.”
Claim 33 is objected because the prior art in the records fails to discloses or suggest the system including the limitation of “the first signal converter is further configured to change a pulse width of the logic signal linearly with the first signal in magnitude; wherein: if the first signal increases in magnitude, the pulse width increases linearly with the first signal; and if the first signal decreases in magnitude, the pulse width decreases linearly with the first signal.”
Claim 37 is objected because the prior art in the records fails to discloses or suggest the system including the limitation of “if the first signal is an input voltage and the second signal is an input current, the first signal converter is a voltage-to-pulse-width converter; the second signal converter is a current-to-current converter; and the input power is equal to the input current multiplied by the input voltage.”
Claim 38 is objected because the prior art in the records fails to discloses or suggest the system including the limitation of “if the first signal is an input current and the second signal is an input voltage, the first signal converter is a current-to- pulse-width converter and the second signal converter is a voltage-to-current converter, the input power is equal to the input current multiplied by the input voltage.”
Claim 25 dependent on claim 24, thus is also objected because to its dependency.
Claims 34-35 are dependent on claim 33, thus are also objected because to their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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HE “CN 202522622” New intelligent electric meter of this utility model relates to a comprehensive electric energy quality evaluation and power meter.
Yang “CN 2036275” A fast measuring device for monitoring intermediate frequency power factor and active power.
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/SISAY G TIKU/
Primary Examiner, Art Unit 2838
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