DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-14, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cariello, Giuseppe (PG Pub. 2023/0,359,370 A1) [hereafter Cariello], and further in view of Mason et al. (PG Pub. 2023/0,393,955 A1) [hereafter Mason].
As per claim 1, Cariello teaches:
A memory device comprising: a memory cell array comprising a plurality of memory cells and storing reference setting data comprising information regarding setting operations of the memory device; (Cariello, ¶ [0018], memory arrays of any type of memory cells, ¶ [0011], loading trim set into one or more latches of the selected memory device, ¶ [0034], loading trim sets (e.g., voltage parameters) associated with respective memory devices into corresponding latches of the respective memory devices, ¶ [0045], operational parameters)
a control logic configured to control memory operations on the memory cell array; and (Cariello, ¶ [0008], an array controller)
a latch circuit comprising a plurality of latches, (Cariello, ¶ [0011], one or more latches)
wherein the reference setting data is loaded from the memory cell array and stored as load setting data in the latch circuit, (Cariello, ¶ [0011], read the trim settings from the memory device and load the trim settings into one or more latches)
storing trim setting in respective registers of the memory devices (Cariello, ¶ [0011], ¶ [0035], load the trim sets into corresponding registers of the remaining memory devices; latches form registers by grouping multiple latches in parallel to store muti-bit data)
detecting error in the stored trim setting of a memory device and rereading the trim set associated with the memory device to load the trim sets in to the respective latches of the memory device (Cariello, ¶ [0041-0043])
Cariello does not teach:
wherein the control logic is further configured to: compare the reference setting data stored in the memory cell array, with the load setting data stored in the latch circuit to determine whether the reference setting data and the load setting data match, and perform a recovery operation to load the reference setting data from the memory cell array back to the latch circuit when the control logic determines that the reference setting data and the load setting data do not match
However, Mason in an analogous art teaches:
comparing trim settings in the trim registers to the trim settings loaded during manufacturing to determine a trim error (Mason, ¶ [0041-0042]), and attempting self-recovery upon detecting mismatching bits (Mason, ¶ [0042])
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Mason into the method of Cariello to provide a method wherein the control logic is further configured to: compare the reference setting data stored in the memory cell array, with the load setting data stored in the latch circuit to determine whether the reference setting data and the load setting data match, and perform a recovery operation to load the reference setting data from the memory cell array back to the latch circuit when the control logic determines that the reference setting data and the load setting data do not match. The modification would be obvious because such method allows the memory device to determine whether the failure was due to a trim setting and allows the proper failure handling based on the determined nature of the failure (Mason, ¶ [0042]).
As per claim 2, the rejection of claim 1 is incorporated and Mason further teaches:
wherein the control logic is further configured to compare the reference setting data with the load setting data for each pair of bits, determine a bit of the load setting data, in which a bit value of the load setting data and a bit value of the reference setting data do not match, as an error bit, and perform the recovery operation when at least one of the bits of the load setting data is an error bit (Mason, ¶ [0041-0042], a bitwise comparison of the trim setting values and attempting self-recovery in response to determining error in trim setting)
As per claim 3, the rejection of claim 2 is incorporated and Mason further teaches:
wherein the control logic is further configured to compare the reference setting data with the load setting data for each bit until the error bit is determined from among the bits of the load setting data, and perform the recovery operation when the error bit of the load setting data is determined (Mason, ¶ [0043], a bitwise comparison and a threshold number of mismatching bits means the number of error bits can be set to 1 to initiate recovery upon the detection of error)
As per claim 4, the rejection of claim 2 is incorporated and Mason further teaches:
wherein the control logic is further configured to compare every bit value of the load setting data with every bit value of the reference setting data, perform the recovery operation when at least one of the bits of the load setting data is the error bit, and not perform the recovery operation when none of the bits of the load setting data is the error bit (Mason, ¶ [0041-0043], a bitwise comparison of the trim setting values and attempting self-recovery in response to determining error in trim setting, the self-recovery manager returns the memory device to the regular error handling flow if the threshold number of mismatching bits is not satisfied)
As per claim 5, the rejection of claim 1 is incorporated and Mason further teaches:
further comprising a page buffer connected to the memory cell array, wherein the reference setting data stored in the memory cell array is stored in the page buffer, (Mason, par [0038], storing snapshot of trim settings such as factory defined settings, manufacturer recommended settings, or a similar state prior to any runtime changes)
wherein the control logic is further configured to compare the reference setting data stored in the page buffer with the load setting data stored in the latch circuit to determine whether the reference setting data and the load setting data match (Mason, ¶ [0041], re-initialized trim settings with the trim settings that were stored and performing the comparison)
As per claim 6, the rejection of claim 5 is incorporated and Mason further teaches:
wherein the control logic is further configured to perform the recovery operation when determining that the reference setting data stored in the page buffer and the load setting data stored in the latch circuit do not match (Mason, ¶ [0041], performs self-recovery upon detecting mismatching bits)
As per claim 7, the rejection of claim 1 is incorporated and Mason further teaches:
wherein the control logic is further configured to, after a preset period of time after the performing of the recovery operation, compare the reference setting data stored in the memory cell array with the load setting data stored in the latch circuit to determine whether the reference setting data and the load setting data match, and (Mason, [0041], a bitwise comparison of re-initialized trim settings with the trim settings that were stored previously; a time taken for power-off and a power-on cycle is a preset period of time)
stop the recovery operation when determining that the reference setting data and the load setting data do not match (Mason, ¶ [0044], self-recovery manager retiring the locations if an additional failure is detected after re-initialization)
As per claim 9, Cariello teaches:
A memory device comprising: a memory cell array storing reference setting data comprising information regarding setting operations of the memory device; (Cariello, ¶ [0018], memory arrays of any type of memory cells, ¶ [0011], loading trim set into one or more latches of the selected memory device, ¶ [0034], loading trim sets (e.g., voltage parameters) associated with respective memory devices into corresponding latches of the respective memory devices, ¶ [0045], operational parameters)
a latch circuit in which the reference setting data is loaded from the memory cell array and stored as load setting data; (Cariello, ¶ [0011], one or more latches; read the trim settings from the memory device and load the trim settings into one or more latches)
storing trim setting in respective registers of the memory devices (Cariello, ¶ [0011], ¶ [0035], load the trim sets into corresponding registers of the remaining memory devices; latches form registers by grouping multiple latches in parallel to store muti-bit data)
detecting error in the stored trim setting of a memory device and rereading the trim set associated with the memory device to load the trim sets in to the respective latches of the memory device (Cariello, ¶ [0041-0043])
Cariello does not teach:
a comparison circuit configured to compare the reference setting data output from the memory cell array and the load setting data output from the latch circuit to output a comparison signal; and a determination circuit configured to generate a determination signal for controlling a recovery operation to load the reference setting data from the memory cell array back to the latch circuit, based on the comparison signal indicating that the reference setting data and the load setting data do not match
However, Mason in an analogous art teaches:
comparing trim settings in the trim registers to the trim settings loaded during manufacturing to determine a trim error (Mason, ¶ [0041-0042]), and attempting self-recovery upon detecting mismatching bits (Mason, ¶ [0042])
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Mason into the method of Cariello to provide a comparison circuit configured to compare the reference setting data output from the memory cell array and the load setting data output from the latch circuit to output a comparison signal; and a determination circuit configured to generate a determination signal for controlling a recovery operation to load the reference setting data from the memory cell array back to the latch circuit, based on the comparison signal indicating that the reference setting data and the load setting data do not match. The modification would be obvious because such method allows the memory device to determine whether the failure was due to a trim setting and allows the proper failure handling based on the determined nature of the failure (Mason, ¶ [0042]).
As per claim 10, the rejection of claim 9 is incorporated and Mason further teaches:
wherein the comparison circuit is further configured to compare the reference setting data with the load setting data for each bit to determine whether the reference setting data and the load setting data match, and output the comparison signal for each bit (Mason, ¶ [0041-0042], a bitwise comparison of the trim setting values determine the number of mismatching bits)
As per claim 11, the rejection of claim 10 is incorporated and Mason further teaches:
wherein the comparison circuit is further configured to: output the comparison signal having a first comparison value when the reference setting data and the load setting data match, and output the comparison signal having a second comparison value different from the first comparison value when the reference setting data and the load setting data do not match (Mason, ¶ [0041-0042], a bitwise comparison of the trim setting values determine the number of mismatching bits means matching and mismatching values will be different)
As per claim 12, the rejection of claim 11 is incorporated and Mason further teaches:
wherein the determination circuit is further configured to, upon receiving the comparison signal having the second comparison value, generate the determination signal including a first determination value for performing the recovery operation (Mason, ¶ [0041-0043], a bitwise comparison of the trim setting values and attempting self-recovery in response to determining error in trim setting, the self-recovery manager returns the memory device to the regular error handling flow if the threshold number of mismatching bits is not satisfied)
As per claim 13, the rejection of claim 11 is incorporated and Mason further teaches:
an accumulator configured to generate an accumulation value by accumulating comparison values of the comparison signal, and wherein the determination circuit is further configured to generate the determination signal based on the accumulation value (Mason, ¶ [0043], a bitwise comparison and a threshold number of mismatching bits)
As per claim 14, the rejection of claim 13 is incorporated and Mason further teaches:
wherein the determination circuit is further configured to generate the determination signal comprising a first determination value for performing the recovery operation when the accumulation value is greater than a reference accumulation value, and generate the determination signal comprising a second determination value for not performing the recovery operation when the accumulation value is less than or equal to the reference accumulation value (Mason, ¶ [0041-0043], a bitwise comparison of the trim setting values and attempting self-recovery in response to determining error in trim setting, the self-recovery manager returns the memory device to the regular error handling flow if the threshold number of mismatching bits is not satisfied)
Claim 17 is a method claim reciting similar limitations of the device claim 9 and is rejected for the same reasons set forth in connection of the rejection of claim 9 above. The only difference is that claim 17 recites the setting data is output to a page buffer. However, claim 5 recites a page buffer storing reference setting data and the same reasoning applied in claim 5 is incorporated in rejecting the page buffer limitation of claim 17.
As per claim 18, the rejection of claim 17 is incorporated and Mason further teaches:
wherein the outputting of the comparison signal comprises: outputting the comparison signal having a first value when the setting data stored in the page buffer and the setting data stored in the latch circuit match; and outputting the comparison signal having a second value when the setting data stored in the page buffer and the setting data stored in the latch circuit do not match, and wherein the first comparison value is different from the second comparison value (Mason, ¶ [0041-0042], a bitwise comparison of the trim setting values determine the number of mismatching bits means matching and mismatching values will be different)
As per claim 19, the rejection of claim 18 is incorporated and Mason further teaches:
wherein the generating of the determination signal comprises: generating the determination signal for not performing the recovery operation when the comparison signal having the first comparison value is output; and generating the determination signal for performing the recovery operation when the comparison signal having the second comparison value is output (Mason, ¶ [0041-0042], a bitwise comparison of the trim setting values determine the number of mismatching bits means matching and mismatching values will be different, ¶ [0041-0043], a bitwise comparison of the trim setting values and attempting self-recovery in response to determining error in trim setting, the self-recovery manager returns the memory device to the regular error handling flow if the threshold number of mismatching bits is not satisfied)
As per claim 20, the rejection of claim 18 is incorporated and Mason further teaches:
generating an accumulation value by accumulating a comparison value of the comparison signal, and the generating of the determination signal comprises: generating the determination signal comprising a first determination value for performing the recovery operation when the accumulation value is greater than a reference accumulation value; and generating the determination signal comprising a second determination value for not performing the recovery operation when the accumulation value is less than or equal to the reference accumulation value (Mason, ¶ [0041-0043], a bitwise comparison of the trim setting values and attempting self-recovery in response to determining error in trim setting, the self-recovery manager returns the memory device to the regular error handling flow if the threshold number of mismatching bits is not satisfied)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cariello, Mason, and further in view of Cadloni et al. (PG Pub. 2020/0,019,459 A1) [hereafter Cadloni].
As per claim 8, the rejection of claim 1 is incorporated:
Cariello and Mason do not teach:
wherein the control logic is further configured to perform the recovery operation when the memory device is in an idle state
However, Cadloni in an analogous art teaches:
memory management operation performed when the memory device is idle (Cadloni, ¶ [0059])
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Cadloni into the combined method of Cariello and Mason to provide a device wherein the control logic is further configured to perform the recovery operation when the memory device is in an idle state. The modification would be obvious because making such recovery procedure as idle operation makes such procedure a low-priority procedure and allows the memory device to handle when the memory device has no active task.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cariello, Mason, and further in view of Ellur, Harsharaj (PG Pub. 2019/0,227,867 A1) [hereafter Ellur].
As per claim 16, the rejection of claim 9 is incorporated:
Cariello and Mason do not teach:
wherein the comparison circuit comprises an XOR gate receiving the reference setting data as a first input and the load setting data as a second input and configured to compare the first input with the second input to output the comparison signal
However, Ellur in an analogous art teaches:
using XOR logic gate as a comparator (Ellur, ¶ [0037])
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Ellur into the combined method of Cariello and Mason to provide a device wherein the comparison circuit comprises an XOR gate receiving the reference setting data as a first input and the load setting data as a second input and configured to compare the first input with the second input to output the comparison signal. The modification would be obvious because XOR gate is a simple logic gate that further facilitates forming the fault detection circuit with a small footprint (Ellur, ¶ [0008]).
Allowable Subject Matter
Claim 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PG Pub. 2024/0,053,905 A1 discloses method for compression and decompression of trim data. A memory system may store one or more trim settings to a volatile memory in a compressed manner, and may expand (e.g., decompress) the data as part of a write operation to a non-volatile memory.
PG Pub. 2024/0,012,703 A1 discloses a memory device capable of determining whether reference setting data of a setting table matches the fetched setting data, the reference setting data indicating information about a designed operating environment of the non-volatile memory device, and providing a reset request to the latch unit, based on determining that the reference setting data does not match the fetched setting data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAE M KO whose telephone number is (571)270-3886. The examiner can normally be reached M-F 9 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHAE M KO/Primary Examiner, Art Unit 2114