DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21-40 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Copeland (pub #US 20110302390 A1) in view of Dobbie (pub # US 20130111073 A1).
Regarding claim 21, Copeland discloses a system (a system that uses a plurality of parallel processors, paragraph 41), comprising: a processor (general purpose processor for control, scheduling and synchronization of processing tasks, paragraph 41), a plurality of rank state machine engines (processing elements, paragraph 41) configured or programmable as a single logical group or multiple logical groups (processing steps are partitioned among a plurality of processing elements; allocation of computing resources can be dynamic using task queues and allocated to available processing elements according to a priority schedule, paragraph 41); a bus interface communicatively coupled between the processor and the plurality of rank state machine engines (a switch fabric to interconnect the processing elements, paragraph 26), wherein the bus interface comprises a plurality of data lines to transfer data streams to the plurality of rank state machine engines (multiple interconnection lines shown in figures 4 and 5).
Copeland does not teach explicitly inter-rank bus. However, Dobbie discloses and an inter-rank bus and process buffer interface (cross-bar control circuit 260, used by the 4 groups of 8 cores, paragraph 33, details shown in figure 2, paragraph 36) configured to receive a data stream of the data streams and send portions of the data stream to logical groups in the plurality of rank state machine engines to be analyzed or to be modified (the control circuit 260 receives signals at both the core-side and bank-side buses 250, 255, and routes those signals to the appropriate processor core group 210A-D or bank 230A-D). Furthermore, teachings of Copeland and Dobbie are from the same field of multi-core processor systems.
Therefore, it would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to combine teachings of Copeland with Dobbie by using a cross-bar control circuit to routing data between multiple core groups and multiple memory banks for the benefit of accommodating large multiple core systems (paragraph 33, Dobbie).
Regarding claim 22, the above reference(s) discloses the system of claim 21, wherein the bus interface comprises at least a memory interface (connection to memory banks 230A-D, paragraph 36, Dobbie.
Regarding claim 23, the above reference(s) discloses the system of claim 21, wherein the system comprises volatile memory coupled to the processor (DRAM, paragraph 36, Dobbie).
Regarding claim 24, the above reference(s) discloses the system of claim 21, wherein the plurality of rank state machine engines are configured to receive instructions from the processor to program the plurality of rank state machine engines, wherein the instructions comprise a same instruction set or multiple instruction sets (from control GPP, paragraph 41, Copeland).
Regarding claim 25, the above reference(s) discloses the system of claim 21, wherein the inter-rank bus and process buffer interface is configured to segment the data stream into the portions of the data stream and send it to the logical groups (routing data to corresponding core groups, paragraph 36, Dobbie).
Regarding claim 26, the above reference(s) discloses the system of claim 21, wherein the portions of the data stream comprise different data (this is implied as the system dynamically works on different instructions and data, paragraph 41; Copeland).
Regarding claim 27, the above reference(s) discloses the system of claim 21, wherein the logical groups receive different portions of the data stream (routing data to corresponding core groups, paragraph 36, Dobbie).
Regarding claim 28, the above reference(s) discloses the system of claim 21, wherein the inter-rank bus and process buffer interface is configured to send modified data between the logical groups (processing steps partitioned among a plurality of processing elements; switching fabric allows communication between any pair wise processing element either directly or indirectly, paragraph 41, Copeland).
Regarding claim 29, the above reference(s) discloses the system of claim 21, wherein the inter-rank bus and process buffer interface is configured to send data following a rank order of the plurality of rank state machine engines (ordering based on quality-of-service level, paragraph 44, Dobbie).
Regarding claim 30, the above reference(s) discloses the system of claim 21, wherein the inter-rank bus and process buffer interface and the plurality of rank of state machine engines are in a single device (device shown in figure 2, Dobbie).
Regarding claims 31-40, examiner notes that these claims are substantially similar to claims 21 and 24-30. The same grounds of rejection are applied.
Conclusion
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/SCOTT C SUN/Primary Examiner, Art Unit 2181