DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-8, 10, 14-16, 18-20 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Kimura (US 5057717).
Regarding claim 1, Kimura discloses a detector cell [B0, fig. 1] comprising: a first current source circuit [I1] having a terminal; a first transistor [M5] having a control terminal, a first terminal, and a second terminal [source] coupled to the terminal of the first current source circuit; a second current source circuit [I2] having a terminal coupled to the first terminal of the first transistor; a first current mirror [current mirror comprising Q8 and Q9] having a first terminal and a second terminal, the first terminal coupled to the terminal of the second current source circuit and the first terminal of the first transistor; a second transistor [Q3] having a control terminal, a first terminal [drain], and a second terminal [source] coupled to the terminal of the first current source circuit; a third current source circuit [I2] having a terminal [terminal connected to M3] coupled to the first terminal of the second transistor; and a second current mirror [current mirror comprising Q6 and Q7] having a first terminal [terminal drain Q6] coupled to the terminal of the third current source circuit and the first terminal of the second transistor and a second terminal [drain terminal Q7] coupled to the second terminal of the first current mirror.
Regarding claim 2, Kimura discloses [fig. 1] further including a resistor [R0] having a terminal [terminal coupled to B0 and B1] coupled to the second terminal of the first current mirror and the second terminal of the second current mirror.
Regarding claim 6, Kimura discloses [fig. 1] wherein at least one of the first transistor or the second transistor [BJT Q3] is implemented by a negative-positive-negative bipolar junction transistor.
Regarding claim 7, Kimura discloses [fig. 1] wherein at least one of the first transistor [MOS transistor M5] or the second transistor is implemented by a negative-channel metal-oxide-semiconductor field-effect transistor.
Regarding claim 8, Kimura discloses a logarithmic amplifier [fig. 1] comprising: a first detector cell [B0, fig. 1, cl. 1, ln 18-32] having a first terminal [output terminal connected to Q9], a second terminal [terminal connected to Vin and Q10], and a third terminal [terminal connected to Vin and Q11]; an amplifier [A1] having a first terminal [terminal connected between R10 and Q10], a second terminal [terminal connected between R11 and Q11], a third terminal [gate terminal connected to Q10] coupled to the second terminal of the first detector cell, and a fourth terminal [terminal connected to Q11] coupled to the third terminal of the first detector cell; a second detector cell [B1] having a first terminal [output terminal B1], a second terminal [terminal coupled to V1, terminal connected between R10 and Q10 ] coupled to the first terminal of the amplifier, and a third terminal [terminal coupled to V1, terminal connected between R11 and Q10] coupled to the second terminal of the amplifier; an adder [cl. 5, ln. 1-30] having a first terminal [terminal connected to V0], a second terminal [terminal connected to B0] coupled to the first terminal of the first detector cell, and a third terminal [terminal connected to B1] coupled to the first terminal of the second detector cell, respective ones of the first detector cell and the second detector cell including: a first current source circuit [I1] having a terminal [terminal connected to M5]; a first transistor [M5] having a control terminal [gate M5], a first terminal [source], and a second terminal [drain], the control terminal to operate as the second terminal of the respective ones of the first detector cell and the second detector cell, the second terminal coupled to the terminal of the first current source circuit; a second current source [I2] circuit having a terminal [terminal connected to source M5] coupled to the first terminal of the first transistor; a first current mirror [current mirror comprising Q8 and Q9] having a first terminal [terminal connected to drain Q8] coupled to the terminal of the second current source circuit [through M5] and the first terminal of the first transistor and a second terminal [terminal connected to collector Q9] to operate as the first terminal of the respective ones of the first detector cell and the second detector cell; a second transistor [Q2] having a control terminal [base terminal Q2], a first terminal [collector terminal Q2], and a second terminal [emitter terminal Q2], the control terminal to operate as the third terminal of the respective ones of the first detector cell and the second detector cell, the second terminal coupled to the terminal of the first current source circuit; a third current source [I2 connected to M2/M3] circuit having a terminal [terminal connected to M2/M3] coupled to the first terminal of the second transistor; and a second current mirror [current mirror comprising Q6 and Q7] having a first terminal [drain terminal Q6] coupled to the terminal of the third current source circuit and the first terminal of the second transistor and a second terminal [collector terminal Q7] coupled to the second terminal of the first current mirror [through Q8] and to operate as the first terminal of the respective ones of the first detector cell and the second detector cell.
Regarding claim 10, Kimura discloses [see fig. 1] wherein the respective ones of the first detector cell and the second detector cell further include a resistor [R0] having a first terminal coupled to the second terminal of the first current mirror and the second terminal of the second current mirror, the first terminal to operate as the first terminal of the respective ones of the first detector cell and the second detector cell.
Regarding claim 14, Kimura discloses [see fig. 1] wherein at least one of the first transistor or the second transistor [BJT Q3] is implemented by a negative-positive-negative bipolar junction transistor.
Regarding claim 15, Kimura discloses [see fig. 1] wherein at least one of the first transistor [MOS transistor M5] or the second transistor is implemented by a negative-channel metal-oxide-semiconductor field-effect transistor.
Regarding claim 16, Kimura discloses a logarithmic amplifier [fig. 1, ] having a non-linear transfer function [inherent], the logarithmic amplifier comprising: a first detector cell [B0, fig. 1, cl. 1, ln 18-32] having a first terminal [output terminal connected to Q9], a second terminal [terminal connected to Vin and Q10], and a third terminal [terminal connected to Vin and Q11], the first detector cell having a first linear transfer function [inherent]; an amplifier [A1] having a first terminal [terminal connected between R10 and Q10], a second terminal [terminal connected between R11 and Q11], a third terminal [terminal connected to base Q10] coupled to the second terminal of the first detector cell, and a fourth terminal [terminal connected to Q11] coupled to the third terminal of the first detector cell; a second detector cell [B1] having a first terminal [output terminal B1], a second terminal [terminal coupled to V1, terminal connected between R10 and Q10 ] coupled to the first terminal of the amplifier, and a third terminal [terminal coupled to V1, terminal connected between R11 and Q10] coupled to the second terminal of the amplifier, the second detector cell having a second linear transfer function [inherent]; and an adder [cl. 5, ln. 1-30] having a first terminal [terminal connected to V0], a second terminal [terminal connected to B0] coupled to the first terminal of the first detector cell, and a third terminal [terminal connected to B1]coupled to the first terminal of the second detector cell.
Regarding claim 18, Kimura discloses wherein respective ones of the first detector cell and the second detector cell are to rectify respective input voltage signals [cl. 3, ln. 26-46].
Regarding claim 19, Kimura discloses wherein respective output voltage signals from respective ones of the first detector cell and the second detector cell are to saturate after respective input voltage signals to the respective ones of the first detector cell and the second detector cell reach a saturation voltage [cl. 5, ln. 10-25 and ln. 45-50].
Regarding claim 20, Kimura discloses [fig. 1] wherein respective ones of the first detector cell and the second detector cell are to improve a logarithmic conformance error [inherent] and a dynamic range of the logarithmic amplifier [cl. 5, ln. 45-67].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Smith (US 7411455).
Regarding claims 3 and 11, Kimura discloses all the features with respect to claims 1 and 8 as outlined above. Kimura further discloses [see fig. 1] wherein respective ones of the first current mirror and the second current mirror include: a third transistor [Q8] having a control terminal [Base Q8], a first terminal [collector Q8], and a second terminal [Emitter Q8], the control terminal coupled to the first terminal, the first terminal to operate as the first terminal of the respective ones of the first current mirror and the second current mirror; a fourth transistor [Q9] having a control terminal [base Q9], a first terminal [collector Q9], and a second terminal [emitter Q9], the control terminal coupled to the control terminal of the third transistor, the first terminal to operate as the second terminal of the respective ones of the first current mirror and the second current mirror. Kimura does not explicitly disclose a first resistor having a first terminal and a second terminal, the second terminal of the third transistor coupled to the second terminal of the first resistor and a second resistor having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the second terminal of the fourth transistor.
However, Smith discloses a current mirror [see fig. 3] include a first resistor [R2] having a first terminal and a second terminal, the second terminal of a transistor [Q17] coupled to the second terminal of the first resistor and a second resistor [R1] having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the second terminal of a fourth transistor [Q15]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kimura by incorporating resistors in the current mirror as taught in smith in order to provide a relatively high incremental output impedance [cl. 1, ln. 50-62].
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Kimura (US 5319264 and Kimura264 hereinafter) further in view of Gilbert (US 5298811).
Regarding claim 9, Kimura discloses all the features with respect to claim 8 as outlined
above. Kimura further discloses [see fig. 1] wherein the amplifier is a first amplifier [A1], the adder is a first adder [adder (cl. 5, ln. 20-25)], and the logarithmic amplifier includes: a second amplifier [A2] having a first terminal [first terminal connected to A3], a second terminal [second terminal connected to A3], a third terminal [terminal connected to V1 between R10 and Q10] coupled to the first terminal of the first amplifier, and a fourth terminal [terminal connected to V1 between R11 and Q11] coupled to the second terminal of the first amplifier; a third detector cell [B2] having a first terminal [output terminal B2], a second terminal [first terminal connected to A3] coupled to the first terminal of the second amplifier, and a third terminal coupled to the second terminal of the second amplifier; a third amplifier [A3] having a first terminal, a second terminal, a third terminal coupled to the first terminal of the second amplifier, and a fourth terminal coupled to the second terminal of the second amplifier; a fourth detector cell [B3] having a first terminal, a second terminal coupled to the first terminal of the third amplifier, and a third terminal coupled to the second terminal of the third amplifier, respective ones of the third detector cell [e.g., B3] and the fourth detector cell [e.g., Bn, similar structure as explained above in claim 8] including: a fourth current source circuit [I1 in Bn] having a terminal; a third transistor [Mn5] having a control terminal, a first terminal, and a second terminal, the control terminal to operate as the second terminal of the respective ones of the third detector cell and the fourth detector cell, the second terminal coupled to the terminal of the fourth current source circuit; a fifth current source circuit [I2, in Bn] having a terminal coupled to the first terminal of the third transistor; a third current mirror [current mirror comprising Qn8 and Qn9] having a first terminal coupled to the terminal of the fifth current source circuit and the first terminal of the third transistor, and a second terminal to operate as the first terminal of the respective ones of the third detector cell and the fourth detector cell; a fourth transistor [Qn3] having a control terminal, a first terminal, and a second terminal, the control terminal to operate as the third terminal of the respective ones of the third detector cell and the fourth detector cell, the second terminal coupled to the terminal of the fourth current source circuit; a sixth current source circuit [I2 connected to Mn2/Mn3] having a terminal coupled to the first terminal of the fourth transistor; and a fourth current mirror [current mirror comprising Qn6 and Qn7] having a first terminal coupled to the terminal of the sixth current source circuit and the first terminal of the fourth transistor and a second terminal coupled to the second terminal of the third current mirror and to operate as the first terminal of the respective ones of the third detector cell and the fourth detector cell. Kimura does not explicitly disclose a second adder having a first terminal, a second terminal coupled to the first terminal of the third detector cell, and a third terminal coupled to the first terminal of the fourth detector cell; a third adder having a first terminal, a second terminal coupled to the first terminal of the first adder, and a third terminal coupled to the first terminal of the second adder; and a filter having a first terminal and a second terminal coupled to the first terminal of the third adder.
However, Kimura264 discloses [see fig. 1 and abstract] a second adder [first adder 3, fig.1; A current adder is provided for each or a group of the squaring full-wave rectifiers to add up the intermediate currents thereof and produce an output current, abstract] having a first terminal [terminal connected to V0], a second terminal coupled to the first terminal of a third detector cell [22], and a third terminal coupled to the first terminal of a fourth detector cell [23]; a third adder [second adder 3, fig.1] having a first terminal, a second terminal coupled to the first terminal of the first adder, and a third terminal coupled to the first terminal of the second adder. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kimura by incorporating a second and a third adder as taught in Kimura264 in order to provide high performance a logarithmic amplifying circuit which has a wide dynamic range and can obtain excellent logarithmic characteristics [cl. 1, ln 34-37]. Kimura in view of Kimura264 does not explicitly a filter having a first terminal and a second terminal coupled to the first terminal of the third adder.
However, Gilbert discloses [see fig. 1] a filter [18] having a first terminal and a second terminal coupled to the first terminal of adder [sum bus 24]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kimura/ Kimura264 by incorporating filter circuit as taught in Gilbert in order to provide a stable, filtered output.
Regarding claim 17, Kimura discloses all the features with respect to claim 16 as outlined
above. Kimura further discloses [see fig. 1] wherein the amplifier is a first amplifier [A1], the adder is a first adder [cl. 5, ln. 1-30], and the logarithmic amplifier includes: a second amplifier [A2] having a first terminal, a second terminal, a third terminal coupled to the first terminal of the first amplifier, and a fourth terminal coupled to the second terminal of the first amplifier; a third detector cell [B2] having a first terminal, a second terminal coupled to the first terminal of the second amplifier, and a third terminal coupled to the second terminal of the second amplifier, the third detector cell having a third linear transfer function [inherent]; a third amplifier [A3] having a first terminal, a second terminal, a third terminal coupled to the first terminal of the second amplifier, and a fourth terminal coupled to the second terminal of the second amplifier; a fourth detector cell [B3] having a first terminal, a second terminal coupled to the first terminal of the third amplifier, and a third terminal coupled to the second terminal of the third amplifier, the fourth detector cell having a fourth linear transfer function [inherent]. Kimura does not explicitly disclose a second adder having a first terminal, a second terminal coupled to the first terminal of the third detector cell, and a third terminal coupled to the first terminal of the fourth detector cell; a third adder having a first terminal, a second terminal coupled to the first terminal of the first adder, and a third terminal coupled to the first terminal of the second adder; and a filter having a first terminal and a second terminal coupled to the first terminal of the third adder.
However, Kimura264 discloses [see fig. 1 and abstract] a second adder [first adder 3, fig.1; A current adder is provided for each or a group of the squaring full-wave rectifiers to add up the intermediate currents thereof and produce an output current, abstract] having a first terminal [terminal connected to V0], a second terminal coupled to the first terminal of a third detector cell [22], and a third terminal coupled to the first terminal of a fourth detector cell [23]; a third adder [second adder 3, fig.1] having a first terminal, a second terminal coupled to the first terminal of the first adder, and a third terminal coupled to the first terminal of the second adder. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kimura by incorporating a second and a third adder as taught in Kimura264 in order to provide high performance a logarithmic amplifying circuit which has a wide dynamic range and can obtain excellent logarithmic characteristics [cl. 1, ln 34-37]. Kimura in view of Kimura264 does not explicitly a filter having a first terminal and a second terminal coupled to the first terminal of the third adder.
However, Gilbert discloses [see fig. 1] a filter [18] having a first terminal and a second terminal coupled to the first terminal of adder [sum bus 24]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kimura/ Kimura264 by incorporating filter circuit as taught in Gilbert in order to provide a stable, filtered output.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Smith (US 7411455).
Regarding claims 4 and 12, Kimura discloses all the features with respect to claims 1 and 8 as outlined above. Kimura does not explicitly disclose wherein: at least one of the second current source circuit or the third current source circuit is implemented by a positive-negative-positive bipolar junction transistor (BJT); and the first current source circuit is implemented by a negative-positive-negative BJT.
However, Smith discloses [fig. 1] a current source circuit is implemented by a positive-negative-positive bipolar junction transistor (BJT) and by a negative-positive-negative BJT. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kimura as taught in Smith in order to utilize a well-known current source.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Kaur et al. (US 2020/0019202 and Kaur hereinafter).
Regarding claims 5 and 13, Kimura discloses all the features with respect to claims 1 and 8 as outlined above. Kimura does not explicitly disclose wherein: at least one of the second current source circuit or the third current source circuit is implemented by a positive-channel metal-oxide-semiconductor field-effect transistor (MOSFET); and the first current source circuit is implemented by a negative-channel MOSFET.
However, Kaur discloses [see fig. 1C] a current source implemented by a positive-channel metal-oxide-semiconductor field-effect transistor (MOSFET); and the first current source circuit is implemented by a negative-channel MOSFET. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kimura as taught in Kaur in order to utilize a well-known current source.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842