DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Species I and Species C directed to claims 1-2 and 5-15 in the reply filed on 08 December 2025 is acknowledged.
Claims 3-4 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 and 5-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region” and further recites “perform wet chemical processing on the first region and the second region to form a first surface structure in the first region and a second surface structure in the second region, wherein an etching rate of etching the first region that is covered by the tunneling passivation layer is different from an etching rate of etching the second region” where it’s unclear by this language if the first surface structure in the first region and the second surface structure in the second region are referring to surface regions of the semiconductor substrate surface(s) or can refer to surfaces of layers on the semiconductor substrate in the first or second regions. As such, the scope of claim 1 cannot be reasonably determined and is rendered indefinite.
Claims 2 and 5-14 are also rendered indefinite by depending from indefinite claim 1.
For the purposes of examination, the first surface structure in the first region and the second surface structure in the second region are interpreted as being open to being surface structures of layers on the semiconductor substrate in the first or second regions as Figs. 10-11 of applicant’s drawings show first surface region 2 having a different surface structure from second surface region 3 which includes additional layers 4, 7 after wet chemical processing.
Claim 15 recites “a first surface structure in the first region and a second surface structure in the second region, wherein the first surface structure and the second surface structure are formed by performing a wet chemical processing, wherein an etching rate of etching the first region that is covered by the tunnel passivation layer is different from an etching rate of etching the second region” and is rejected as indefinite for the same reasons as claim 1 set forth above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-6, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mack et al (Progress in p-type Tunnel Oxide-Passivated Contact Solar Cells with Screen-Printed Contacts, Sol. RRL 2021, 5, 2100152).
Regarding claim 1 Mack discloses a method for manufacturing a solar cell, comprising:
providing a semiconductor substrate (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: providing boron-doped Cz Si wafer), wherein the semiconductor substrate has a first region (back surface) and a second region (front surface);
forming a tunneling passivation layer on at least the first region (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: interface oxide formation on back surface); and
perform wet chemical processing on the first region and the second region to form a first surface structure in the first region and a second surface structure in the second region (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: random pyramids are formed on the nonprotected front side by etching in alkaline solution, where rear-side SiNx:H layer acts as an etch mask and diffusion barrier during these processes, which causes its thickness to decrease slightly), wherein an etching rate of etching the first region that is covered by the tunneling passivation layer is different from an etching rate of etching the second region (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: etching rate of rear-side SiNx:H layer much slower (acting as a mask) than etching or front surface texturization),
wherein the first surface structure is different from the second surface structure (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: front surface random pyramids different from planar rear side structure).
Regarding claim 2 Mack discloses the method of claim 1, wherein the first surface structure and the second surface structure each comprise at least one of a polished structure, a planar structure, a pyramid structure, or an inverted pyramid structure (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: front surface random pyramids different from planar rear side structure).
Regarding claim 5 Mack discloses the method of claim 1, where the first region is on a back surface of the semiconductor substrate (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: first region is the back surface), and the second region is on a front surface of the semiconductor substrate (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: front surface random pyramids), and wherein the second region is etched by the wet chemical processing, or both the first region and the second region are etched by the wet chemical processing (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: front surface etched to form random pyramids and back surface of rear-side SiNx:H layer slightly etched).
Regarding claim 6 Mack discloses the method of claim 5, wherein the first surface structure comprises at least one of a polished structure or a pyramid structure (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: rear surface of boron-doped Cz Si wafer has saw damage removed and wet chemical cleaning considered to form a polished structure), and the second surface structure comprises a pyramid structure (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: front surface etched to form random pyramids).
Regarding claim 15 Mack discloses solar cell, comprising:
a semiconductor substrate (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: providing boron-doped Cz Si wafer) having a first region (back surface) and a second region (front surface);
a tunneling passivation layer on at least the first region (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: interface oxide formation on back surface); and
a first surface structure in the first region and a second surface structure in the second region, wherein the first surface structure and the second surface structure are formed by performing a wet chemical processing (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: random pyramids are formed on the nonprotected front side by etching in alkaline solution, where rear-side SiNx:H layer acts as an etch mask and diffusion barrier during these processes, which causes its thickness to decrease slightly), wherein an etching rate of etching the first region that is covered by the tunnel passivation layer is different from an etching rate of etching the second region (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: etching rate of rear-side SiNx:H layer much slower (acting as a mask) than etching or front surface texturization), and wherein the second surface structure is different from the first surface structure (Fig. 2 and right hand column of page 2 “2. Sample Preparation” see: front surface random pyramids different from planar rear side structure).
Claims 1-2, 5-8, and 10-15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Weidman et al (US 2015/0162483).
Regarding claim 1 Weidman discloses a method for manufacturing a solar cell, comprising:
providing a semiconductor substrate ([0050], Figs. 3A-3E see: substrate 302), wherein the semiconductor substrate has a first region (rear surface) and a second region (light receiving surface 301);
forming a tunneling passivation layer on at least the first region ([0050], Figs. 3A-3F see: forming thin oxide layer 304 as a tunnel dielectric silicon oxide layer); and
perform wet chemical processing on the first region and the second region to form a first surface structure in the first region and a second surface structure in the second region ([0056]-[0058] Figs. 3B-3C see: hydroxide-based wet etching is performed that simultaneously etches and forms texturization of light receiving surface 301 and formation/texturizing of trenches 322 through removal of non-implanted regions 312 of the silicon layer 306), wherein an etching rate of etching the first region that is covered by the tunneling passivation layer is different from an etching rate of etching the second region ([0030],[0056]-[0058], [0097], Figs. 3B-3C see: implanted regions 314/320 of the carbosilane layer protect or inhibit the etching (e.g., slow the etch rate of) the underlying regions 310/318 and thus have a different etch rate than formation/texturizing of trenches 322 and texturizing of light receiving surface 301),
wherein the first surface structure is different from the second surface structure ([0056]-[0058] Figs. 3B-3C see: light receiving surface has a regular shaped texture pattern, while trenches 322 show an irregular texture pattern and regions 310/318 are planar). It is also noted that alternatively, the regions 310/318 alone meet the limitations to the first region and first surface structure and texturized trenches 322 alternatively meet the limitations to the second region and second surface structure.
Regarding claim 2 Weidman discloses the method of claim 1, wherein the first surface structure and the second surface structure each comprise at least one of a polished structure, a planar structure, a pyramid structure, or an inverted pyramid structure ([0056]-[0058] Figs. 3B-3C see: light receiving surface has a regular shaped texture pattern, while trenches 322 show an irregular texture pattern and regions 310/318 are planar).
Regarding claim 5 Weidman discloses the method of claim 1, where the first region is on a back surface of the semiconductor substrate (back surface of substrate 302), and the second region is on a front surface of the semiconductor substrate (light receiving surface 301), and wherein the second region is etched by the wet chemical processing, or both the first region and the second region are etched by the wet chemical processing ([0030],[0056]-[0058], [0097], Figs. 3B-3C see: : implanted regions 314/320 of the carbosilane layer protect or inhibit the etching (e.g., slow the etch rate of) the underlying regions 310/318 and trenches 322 and light receiving surface 301 are both etched in the wet etching process).
Regarding claim 6 Weidman discloses the method of claim 5, wherein the first surface structure comprises at least one of a polished structure or a pyramid structure ([0056]-[0058] Figs. 3B-3C see: back surface includes texturized trenches 322 with pyramidal texturing), and the second surface structure comprises a pyramid structure ([0056]-[0058] Figs. 3B-3C see: light receiving surface 301 comprises a pyramid structure).
Regarding claim 7 Weidman discloses the method of claim 5, wherein the back surface comprises one or more first sub-regions (Fig. 3B see: regions corresponding to non-implanted regions 312) and one or more second sub-regions (Fig. 3B see: regions corresponding to first and second implanted regions 310/318) alternatively arranged with each other (regions 312 alternative arranged with regions 310/318), wherein the first region comprises the one or more first sub-regions (first region corresponds to the back surface and thus the first sub-regions),
wherein the method further comprises:
forming a first doped semiconductor layer on the tunnel passivation layer on the one or more first sub-regions ([0050], [0052]-[0054], Figs. 3A-3B see: forming on thin oxide layer 304 a silicon layer 306 which is doped in regions 310 and 318 and include non-implanted regions 312 which are not significantly implanted (para [0093]) thus silicon layer 306 is a doped silicon layer);
forming a mask on the one or more second sub-regions ([0051]-[0052] Figs. 3A-3B see: forming first self-aligned implanted regions 314 and second self-aligned implanted regions 320 of carbosilane layer 308 over regions 310/318 of silicon layer 306); and
etching, by the wet chemical processing, a portion of the first doped semiconductor layer that is not covered by the mask ([0056]-[0058] Figs. 3B-3C see: non-implanted regions 312 of doped silicon layer 306 that are not protected by implanted regions 314/320 of carbosilane layer 308 are etched by the hydroxide-based wet etchant).
Regarding claim 8 Westerberg discloses the method of claim 7, wherein, after the wet chemical processing, a surface of the one or more first sub-regions are recessed into the semiconductor substrate relative to a surface of the one or more second sub-regions ([0056]-[0058] Figs. 3B-3C see: trenches 322 are formed in area regions corresponding to removed non-implanted regions 312 and thus recessed compared to regions 310/318).
Regarding claim 10 Weidman discloses the method of claim 5, wherein the back surface comprises one or more first sub-regions (Figs. 3B-3C see: first implanted regions 310) and one or more second sub-regions (Figs. 3B-3C see: second implanted regions 318) alternatively arranged with each other and isolated from each other by one or more third sub-regions, wherein the first region comprises the one or more third sub-regions (Figs. 3B-3C see: trenches 322 or area regions corresponding to removed non-implanted regions 312 as third sub-regions).
Regarding claim 11 Weidman discloses the method of claim 10, wherein the one or more third sub-regions are selectively etched during the wet chemical processing ([0056]-[0058] Figs. 3B-3C see: trenches 322 are formed during the hydroxide-based wet etching).
Regarding claim 12 Weidman discloses the method of claim 11, wherein, after the wet chemical processing, a surface of the one or more third sub-regions is recessed into the semiconductor substrate relative to a surface of the one or more first sub-regions or the one or more second sub-regions ([0056]-[0058] Figs. 3B-3C see: trenches 322 are formed in area regions corresponding to removed non-implanted regions 312 and thus recessed compared to regions 310/318).
Regarding claim 13 Weidman discloses the method of claim 11, wherein a surface of the one or more third sub-regions comprises a pyramid structure (Fig. 3C see: trenches 322 have a pyramidal structure), and the second surface structure comprises a pyramid structure (Fig. 3C see: light receiving surface 301 has a pyramidal texture).
Regarding claim 14 Weidman discloses the method of claim 7, wherein the back surface has a middle region and edge isolation regions extending outward from the middle region (Fig. 3C see: edges of substrate 301 are illustrated as recessed and etched), wherein the one or more first sub-regions and the one or more second sub-regions are in the middle region (Fig. 3C see: regions 310/318 and trenches 322 are between the edges of substrate 301), and wherein, after the wet chemical processing, a surface of the edge isolation regions is recessed into the semiconductor substrate relative to surfaces of the one or more first sub-regions or the one or more second sub-regions (Fig. 3C see: edges of substrate 301 are illustrated as recessed and etched relative to regions 310/318).
Regarding claim 15 Weidman discloses a solar cell, comprising:
a semiconductor substrate ([0050], Figs. 3A-3F see: substrate 302) having a first region (back surface) and a second region (front surface);
a tunneling passivation layer on at least the first region ([0050], Figs. 3A-3F see: thin oxide layer 304 as a tunnel dielectric silicon oxide layer on back surface); and
a first surface structure in the first region and a second surface structure in the second region, wherein the first surface structure and the second surface structure are formed by performing a wet chemical processing ([0056]-[0058] Figs. 3B-3C see: hydroxide-based wet etching is performed that simultaneously etches and forms texturization of light receiving surface 301 and formation/texturizing of trenches 322 through removal of non-implanted regions 312 of the silicon layer 306), wherein an etching rate of etching the first region that is covered by the tunnel passivation layer is different from an etching rate of etching the second region ([0030],[0056]-[0058], [0097], Figs. 3B-3C see: implanted regions 314/320 of the carbosilane layer protect or inhibit the etching (e.g., slow the etch rate of) the underlying regions 310/318 and thus have a different etch rate than formation/texturizing of trenches 322 and texturizing of light receiving surface 301), and wherein the second surface structure is different from the first surface structure ([0056]-[0058] Figs. 3B-3C see: light receiving surface has a regular shaped texture pattern, while trenches 322 show an irregular texture pattern and regions 310/318 are planar). It is also noted that alternatively, the regions 310/318 alone meet the limitations to the first region and first surface structure and texturized trenches 322 alternatively meet the limitations to the second region and second surface structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Weidman et al (US 2015/0162483) as applied to claims 1-2, 5-8, and 10-15 above, and further in view of Moslehi et al (US 2014/0017846).
Regarding claim 9 Weidman discloses the method of claim 7, wherein a surface of the one or more first sub-regions comprises at least one of a polished structure or a pyramid structure ([0056]-[0058] Figs. 3B-3C see: trenches 322 include pyramidal structure), but Weidman does not explicitly disclose a surface of the one or more second sub-regions comprises a pyramid structure.
Moslehi teaches a further back surface doped region of a solar cell can further include a passivation layer with a pyramid structure texture to provide back side IR photon scattering (Moslehi, [0076] Fig. 13 see: back surface 50 of passivation layer 34 is textured between back surface field 32 and metallization layer 36).
Moslehi and Weidman are combinable as they are both concerned with the field of solar cell manufacture.
It would have been obvious to one having ordinary skill in art at the time of the invention to modify the method of Weidman in view of Moslehi such that the method further comprises a surface of the one or more second sub-regions (insulation and back surface field region) comprises a pyramid structure as in Moslehi (Moslehi, [0076] Fig. 13 see: back surface 50 of passivation layer 34 is textured between back surface field 32 and metallization layer 36) to further provide back side IR photon scattering as in Moslehi (para [0076]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Weidman et al (US 2015/0162483) as applied to claims 1-2, 5-8,10-13, and 15 above, and further in view of Cousins (US 2009/0205712).
Regarding claim 14 Weidman discloses the method of claim 7, and in the alternative where it’s not clear Weidman further discloses wherein the back surface has a middle region and edge isolation regions extending outward from the middle region, wherein the one or more first sub-regions and the one or more second sub-regions are in the middle region, and wherein, after the wet chemical processing, a surface of the edge isolation regions is recessed into the semiconductor substrate relative to surfaces of the one or more first sub-regions or the one or more second sub-regions, Cousins further teaches forming edge isolation regions extending outward from a middle region (Cousins [0019], [0027] Fig. 4D see: edge isolation trench 111 formed into substrate 101) wherein, after the wet chemical processing, a surface of the edge isolation regions is recessed into the semiconductor substrate relative to surfaces of one or more first sub-regions or one or more second sub-regions (Cousins, [0036]-[0038] Figs. 4J-4L see: edge isolation trench 111 recessed into substrate 101 deeper relative to contact holes 123 formed by selective etching process on unmasked portions of layer 109). Cousins teaches this edge isolation trench provides edge electrical isolation (para [0019]).
Cousins and Weidman are combinable as they are both concerned with the field of solar cell manufacture.
It would have been obvious to one having ordinary skill in art at the time of the invention to modify the method of Weidman in view of Cousins such that the method further comprises the back surface having a middle region and edge isolation regions extending outward from the middle region as in Cousins (Cousins [0019], [0027] Fig. 4D see: edge isolation trench 111 formed into substrate 101 around middle region), wherein the one or more first sub-regions and the one or more second sub-regions of Weidman are in the middle region, and wherein, after the wet chemical processing of Weidman, a surface of the edge isolation regions is recessed into the semiconductor substrate relative to surfaces of the one or more first sub-regions or the one or more second sub-regions as in Cousins ([0036]-[0038] Figs. 4J-4L see: edge isolation trench 111 recessed into substrate 101 deeper relative to contact holes 123 formed by selective etching process on unmasked portions of layer 109) as Cousins teaches this edge isolation trench provides edge electrical isolation (para [0019]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Weidman (US 2015/0162484 A1) at Figs. 1A-1F and at paras [0045]-[0049] discloses manufacturing a back contact solar cell including etching front and back surfaces of substrate 102 can be performed simultaneously in the same hydroxide-based etch process as part of the process used to remove non-implanted regions of the silicon layer 106.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW J GOLDEN whose telephone number is (571)270-7935. The examiner can normally be reached 11am-8pm.
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ANDREW J. GOLDEN
Primary Examiner
Art Unit 1726
/ANDREW J GOLDEN/Primary Examiner, Art Unit 1726
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