DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 20, 2026 has been entered.
Response to Amendment
Receipt is acknowledged of applicant’s amendment filed January 20, 2026. Claim 8 has been cancelled without prejudice. Claims 1-7 and 9-20 are pending and an action on the merits is as follows. Claims 6 and 16 were previously withdrawn.
Response to Arguments
Applicant's arguments filed January 20, 2026 have been fully considered but they are not persuasive.
In regard to independent claim 1, applicant’s arguments, on pages 7-8 of the Remarks, that the previously applied prior art fails to disclose all of the limitations of claim 1, have been fully considered and are appreciated. However, the newly cited reference, necessitated by amendment, discloses all of the limitations of claim 1, as newly amended. Namely, Huh et al. fails to disclose “where the second transparent conductive layer is not overlapped with the scan line.” However, Ahn discloses (see e.g. Figure 5a): where the second transparent conductive layer 122 (denoted “common electrode”, see e.g. paragraph [0049]) is not overlapped with the scan line 102 (denoted “gate line”, see e.g. paragraph [0049]). Providing the second transparent conductive layer and the gate/scan layer in a same layer rather than overlapping would allow for two components to be manufactured simultaneously thus reducing cost as well as mitigating potential parasitic capacitances.
Similar arguments apply to the double patenting rejections.
Therefore, claims 1-5 and 7-12 are rejected as set forth below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 4, and 5 of U.S. Patent No. 10,197,869 in view of Huh et al. (US 2014/0152934 A1) and further in view of Ahn (US 2006/0121634 A1).
In regard to independent claim 1, US 10,197,869 claims a display device (see e.g. claim 1, Column 9, line 61), comprising:
a substrate (see e.g. claim 1, Column 9, line 62);
a scan line disposed on the substrate wherein the scan line comprises a gate electrode (see e.g. claim 1, Column 9, lines 63-65);
a semiconductor layer disposed on the substrate, wherein a part of the semiconductor layer overlaps the gate electrode, and another part of the semiconductor layer extends outside the gate electrode (see e.g. claim 1, Column 9, line 66-Column 10, line 4);
a source electrode and a drain electrode disposed on the substrate, wherein the gate electrode, the semiconductor layer, the source electrode and the drain electrode form a thin film transistor (see e.g. Claim 1, Column 10, lines 3-9);
an insulating layer disposed on the drain electrode, wherein the insulating layer comprises a via hole (see e.g. Claim 1, Column 10, lines 10-11);
a first transparent conductive layer disposed on the substrate, wherein the first transparent conductive layer electrically connects to the drain electrode through the via hole (see e.g. Claim 1, Column 10, lines 12-15); and
a second transparent conductive layer disposed between the substrate and the first transparent conductive layer, wherein the second transparent conductive layer and the via hole are not overlapped (see e.g. Claim 1, Column 10, lines 16-19).
US 10,197,869 fails to claim
wherein the second transparent conductive layer and an uppermost potion of the via hold are not overlapped;
wherein the second transparent conductive layer is at least partially overlapped with the semiconductor layer and is not overlapped with the scan line.
However, Huh et al. discloses (see e.g. Figures 1-2):
wherein the second transparent conductive layer 131 and an uppermost portion of the via hole 185 are not overlapped (see e.g. Figures 1-2);
wherein the second transparent conductive layer 131 is at least partially overlapped with the semiconductor layer 154 (see e.g. Figure 2).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,197,869 with wherein the second transparent conductive layer and an uppermost potion of the via hold are not overlapped; wherein the second transparent conductive layer is at least partially overlapped with the semiconductor layer.
Doing so would provide an improved aperture ratio by extension of the second transparent electrode through the pixel.
US 10,197,869, in view of Huh et al., fails to disclose
where the second transparent conductive layer is not overlapped with the scan line.
However, Ahn discloses (see e.g. Figure 5a):
where the second transparent conductive layer 122 (denoted “common electrode”, see e.g. paragraph [0049]) is not overlapped with the scan line 102 (denoted “gate line”, see e.g. paragraph [0049]).
Given the teachings of Ahn, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of US 10,197,869, in view of Huh et al., with where the second transparent conductive layer is not overlapped with the scan line.
Providing the second transparent conductive layer and the gate/scan layer in a same layer rather than overlapping would allow for two components to be manufactured simultaneously thus reducing cost as well as mitigating potential parasitic capacitances.
In regard to claim 2, US 10,197,869 claims
wherein the scan line extends along an extension direction, a projection of the second transparent conductive layer on the substrate has a first edge, the projection of the drain electrode on the substrate has a second edge adjacent to the first edge, and a minimum distance between the first edge and the second edge along a direction perpendicular to the extension direction ranges from 0 µm to 4 µm (see e.g. claim 1, Column 10, lines 20-26).
In regard to claim 3, US 10,197,869 fails to claim
wherein the first transparent conductive layer comprises plural slits.
However, Huh et al. discloses
wherein the first transparent conductive layer 191 comprises plural slits 92 (see e.g. paragraph [0069] and Figures 1-2).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,197,869 with wherein the first transparent conductive layer comprises plural slits.
Doing so would provide a lateral electrode field type device which has the advantage of faster driving speeds.
In regard to claim 4, US 10,197,869 fails to claim
wherein the second edge and the second transparent conductive layer are not overlapped.
However, Huh et al. discloses
wherein the second edge (i.e. of drain electrode 175) and the second transparent conductive layer 131 are not overlapped (see e.g. annotated Figure 1 below and Figure 2).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,197,869 with wherein the second edge and the second transparent conductive layer are not overlapped.
Doing so would prevent unwanted parasitic capacitances between electrode layers.
In regard to claim 5, US 10,197,869 fails to claim
wherein the second transparent conductive layer comprises a third edge, and the third edge and the drain electrode are not overlapped.
However, Huh et al. discloses
wherein the second transparent conductive layer 131 comprises a third edge, and the third edge and the drain electrode 175 are not overlapped (see e.g. annotated Figure 1, attached below).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,197,869 with wherein the second transparent conductive layer comprises a third edge, and the third edge and the drain electrode are not overlapped.
Doing so would prevent unwanted parasitic capacitances between electrode layers.
In regard to claim 7, US 10,197,869 claims
wherein the first transparent conductive layer is at least partially overlapped with the drain electrode (see e.g. claim 1, Column 10, lines 29-30).
In regard to claim 8, US 10,197,869 claims
wherein the second transparent conductive layer does not overlap the via hole (see e.g. claim 1, Column 10, lines 18-19).
In regard to claim 9, US 10,197,869 claims
wherein the second transparent conductive layer does not overlap the drain electrode (see e.g. claim 4, Column 10, lines 42-43).
In regard to claim 12, US 10,197,869 claims
a counter substrate opposite to the substrate, and a display medium layer disposed between the first transparent conductive layer and the counter substrate (see e.g. claim 5, Column 10, lines 44-47).
Claims 10 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,197,869 in view of Huh et al. (US 2014/0152934 A1) in view of Ahn (US 2006/0121634 A1) and further in view of Ono (US 2015/0070619 A1).
In regard to claim 10, US 10,197,869, in view of Huh et al. and Ahn, fails to claim
wherein a projection of the source electrode on the substrate is completely located in a projection of the semiconductor layer on the substrate.
However, Ono discloses (see e.g. Figures 2-3):
wherein a projection of the source electrode 52 on the substrate 16 is completely located in a projection of the semiconductor layer 60 on the substrate 16.
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,197,869, in view of Huh et al. and Ahn, with wherein a projection of the source electrode on the substrate is completely located in a projection of the semiconductor layer on the substrate.
Doing so would provide a larger contact between the source electrode and the semiconductor layer.
In regard to claim 11, US 10,197,869, in view of Huh et al. and Ahn, fails to claim
wherein a projection of the drain electrode on the substrate is located in the projection of the semiconductor layer on the substrate.
However, Ono discloses (see e.g. Figures 2-3):
wherein a projection of the drain electrode 54 on the substrate 16 is located in the projection of the semiconductor layer 60 on the substrate 16.
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,197,869, in view of Huh et al. and Ahn, with wherein a projection of the drain electrode on the substrate is located in the projection of the semiconductor layer on the substrate.
Doing so would provide a larger contact between the source electrode and the semiconductor layer.
Claims 1-5, 7, 8, and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 5 of U.S. Patent No. US 10,802,352 in view of Huh et al. (US 2014/0152934 A1) and further in view of Ahn (US 2006/0121634 A1).
In regard to claim 1, US 10,802,352 claims a display device, comprising:
a substrate (see e.g. claim 1, Column 10, line 10);
a scan line disposed on the substrate wherein the scan line comprises a gate electrode (see e.g. claim 1, Column 10, lines 11-13);
a semiconductor layer disposed on the substrate, wherein a part of the semiconductor layer overlaps the gate electrode, and another part of the semiconductor layer extends outside the gate electrode (see e.g. claim 1, Column 10, lines 14-17);
a source electrode and a drain electrode disposed on the substrate, wherein the gate electrode, the semiconductor layer, the source electrode and the drain electrode form a thin film transistor (see e.g. claim 1, Column 10, lines 18-24);
an insulating layer disposed on the drain electrode, wherein the insulating layer comprises a via hole (see e.g. claim 1, Column 10, lines 25-26);
a first transparent conductive layer disposed on the substrate, wherein the first transparent conductive layer electrically connects to the drain electrode through the via hole (see e.g. claim 1, Column 10, lines 27-31); and
a second transparent conductive layer disposed between the substrate and the first transparent conductive layer, wherein the second transparent conductive layer and the via hole are not overlapped (see e.g. claim 1, Column 10, lines 32-34);
wherein the second transparent conductive layer is at least partially overlapped with the semiconductor layer (see e.g. claim 5, Column 10, lines 60-64).
US 10,802,352 fails to claim
wherein the second transparent conductive layer and an uppermost potion of the via hold are not overlapped,
where the second transparent conductive layer is not overlapped with the scan line.
However, Huh et al. discloses (see e.g. Figures 1-2):
wherein the second transparent conductive layer 131 is at least partially overlapped with the semiconductor layer 154 (see e.g. Figure 2).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,802,232, with wherein the second transparent conductive layer is at least partially overlapped with the semiconductor layer.
Doing so would provide an improved aperture ratio by extension of the second transparent electrode through the pixel.
US 10,802,232, in view of Huh et al., fails to disclose
where the second transparent conductive layer is not overlapped with the scan line.
However, Ahn discloses (see e.g. Figure 5a):
where the second transparent conductive layer 122 (denoted “common electrode”, see e.g. paragraph [0049]) is not overlapped with the scan line 102 (denoted “gate line”, see e.g. paragraph [0049]).
Given the teachings of Ahn, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of US 10,802,232, in view of Huh et al., with where the second transparent conductive layer is not overlapped with the scan line.
Providing the second transparent conductive layer and the gate/scan layer in a same layer rather than overlapping would allow for two components to be manufactured simultaneously thus reducing cost as well as mitigating potential parasitic capacitances.
In regard to claim 2, US 10,802,352 claims
wherein the scan line extends along an extension direction, a projection of the second transparent conductive layer on the substrate has a first edge, the projection of the drain electrode on the substrate has a second edge adjacent to the first edge, and a minimum distance between the first edge and the second edge along a direction perpendicular to the extension direction ranges from 0 µm to 4 µm (see e.g. claim 1, Column 10, lines 10-11, 35-41).
In regard to claim 3, US 10,802,352 claims
wherein the first transparent conductive layer comprises plural slits (see e.g. claim 1, Column 10, lines 42-43).
In regard to claim 4, US 10,802,352 fails to claim
wherein the second edge and the second transparent conductive layer are not overlapped.
However, Huh et al. discloses
wherein the second edge (i.e. of drain electrode 175) and the second transparent conductive layer 131 are not overlapped (see e.g. annotated Figure 1 below and Figure 2).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,802,352 with wherein the second edge and the second transparent conductive layer are not overlapped.
Doing so would prevent unwanted parasitic capacitances between electrode layers.
In regard to claim 5, US 10,802,352 fails to claim
wherein the second transparent conductive layer comprises a third edge, and the third edge and the drain electrode are not overlapped.
However, Huh et al. discloses
wherein the second transparent conductive layer 131 comprises a third edge, and the third edge and the drain electrode 175 are not overlapped (see e.g. annotated Figure 1, attached below).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,802,352 with wherein the second transparent conductive layer comprises a third edge, and the third edge and the drain electrode are not overlapped.
Doing so would prevent unwanted parasitic capacitances between electrode layers.
In regard to claim 7, US 10,802,352 claims
wherein the first transparent conductive layer is at least partially overlapped with the drain electrode (see e.g. claim 1, Column 10, lines 45-46).
In regard to claim 8, US 10,802,352 claims
wherein the second transparent conductive layer does not overlap the via hole (see e.g. claim 1, Column 10, lines 32-34).
In regard to claim 12, US 10,802,352 fails to claim
a counter substrate opposite to the substrate, and a display medium layer disposed between the first transparent conductive layer and the counter substrate.
However, Huh et al. discloses
a counter substrate opposite to the substrate, and a display medium layer disposed between the first transparent conductive layer and the counter substrate (see e.g. claim 5, Column 10, lines 44-47).
Given the teachings of Huh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,802,352 with a counter substrate opposite to the substrate, and a display medium layer disposed between the first transparent conductive layer and the counter substrate.
Doing so would provide components that allow the device to be operated as an image display device.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 5 of U.S. Patent No. 10,802,352 in view of Huh et al. (US 2014/0152934 A1) in view of Ahn (US 2006/0121634 A1) and further in view of Kimura et al. (US 2007/0146591 A1).
In regard to claim 9, US 10,802,352, in view of Huh et al. and Ahn, fails to claim
wherein the second transparent conductive layer does not overlap the drain electrode.
However, Kimura et al. discloses (see e.g. Figures 1-2):
wherein the second transparent conductive layer 103 does not overlap the drain electrode 109.
Given the teachings of Kimura et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of US 10,802,352, in view of Huh et al. and Ahn, with wherein the second transparent conductive layer does not overlap the drain electrode.
Doing so would prevent unwanted parasitic capacitances between electrode layers.
Claims 10 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,802,352 in view of Huh et al. (US 2014/0152934 A1) in view of Ahn (US 2006/0121634 A1) and further in view of Ono (US 2015/0070619 A1).
In regard to claim 10, 10,802,352, in view of Huh et al. and Ahn, fails to claim
wherein a projection of the source electrode on the substrate is completely located in a projection of the semiconductor layer on the substrate.
However, Ono discloses (see e.g. Figures 2-3):
wherein a projection of the source electrode 52 on the substrate 16 is completely located in a projection of the semiconductor layer 60 on the substrate 16.
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of 10,802,352, in view of Huh et al. and Ahn, with wherein a projection of the source electrode on the substrate is completely located in a projection of the semiconductor layer on the substrate.
Doing so would provide a larger contact between the source electrode and the semiconductor layer.
In regard to claim 11, 10,802,352, in view of Huh et al. and Ahn, fails to claim
wherein a projection of the drain electrode on the substrate is located in the projection of the semiconductor layer on the substrate.
However, Ono discloses (see e.g. Figures 2-3):
wherein a projection of the drain electrode 54 on the substrate 16 is located in the projection of the semiconductor layer 60 on the substrate 16.
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of 10,802,352, in view of Huh et al. and Ahn, with wherein a projection of the drain electrode on the substrate is located in the projection of the semiconductor layer on the substrate.
Doing so would provide a larger contact between the source electrode and the semiconductor layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Huh et al. (US 2014/0152934 A1) in view of Ahn (US 2006/0121634 A1).
In regard to claim 1, Huh et al. discloses a display device, comprising (see e.g. Figures 1-2):
a substrate 110 (see e.g. paragraph [0054]);
a scan line 121 (denoted “gate line”) disposed on the substrate 110 wherein the scan line 121 comprises a gate electrode 124 (see e.g. paragraph [0054]);
a semiconductor layer 154 disposed on the substrate 110 (see e.g. paragraph [0056]), wherein a part of the semiconductor layer 154 overlaps the gate electrode 124, and another part of the semiconductor layer 154 extends outside the gate electrode 124 (see e.g. Figures 1-2);
a source electrode 173 and a drain electrode 175 disposed on the substrate 110 (see e.g. paragraph [0058]), wherein the gate electrode 124, the semiconductor layer 154, the source electrode 173 and the drain electrode 175 form a thin film transistor Q (see e.g. paragraph [0076], Figures 1-2);
an insulating layer 180a/b disposed on the drain electrode 175 (see e.g. paragraph s[0063]-[0064]), wherein the insulating layer 180a/b comprises a via hole 185 (see e.g. paragraph [0068]);
a first transparent conductive layer 191 disposed on the substrate 110 (see e.g. paragraphs [0069] and [0078]), wherein the first transparent conductive layer 191 electrically connects to the drain electrode 175 through the via hole 185 (see e.g. paragraph [0077]); and
a second transparent conductive layer 131 disposed between the substrate 110 and the first transparent conductive layer 191 (see e.g. paragraphs [0066]-[0067] and Figure 2), wherein the second transparent conductive layer 131 and an uppermost portion of the via hole 185 are not overlapped (see e.g. Figures 1-2);
wherein the second transparent conductive layer 131 is at least partially overlapped with the semiconductor layer 154 (see e.g. Figure 2).
Huh et al. fails to disclose
where the second transparent conductive layer is not overlapped with the scan line.
However, Ahn discloses (see e.g. Figure 5a):
where the second transparent conductive layer 122 (denoted “common electrode”, see e.g. paragraph [0049]) is not overlapped with the scan line 102 (denoted “gate line”, see e.g. paragraph [0049]).
Given the teachings of Ahn, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huh et al. with where the second transparent conductive layer is not overlapped with the scan line.
Providing the second transparent conductive layer and the gate/scan layer in a same layer rather than overlapping would allow for two components to be manufactured simultaneously thus reducing cost as well as mitigating potential parasitic capacitances.
In regard to claim 2, Huh et al. discloses the limitations as applied to claim 1 above, and
wherein the scan line 121 extends along an extension direction, a projection of the second transparent conductive layer 131 on the substrate 110 has a first edge, the projection of the drain electrode 175 on the substrate has a second edge adjacent to the first edge (see e.g. annotated Figure 1 below).
Huh et al. fails to disclose
a minimum distance between the first edge and the second edge along a direction perpendicular to the extension direction ranges from 0µm to 4µm.
However, one of ordinary skill in the art before the effective filing date of the claimed invention would recognize using a minimum distance between the first edge and the second edge along a direction perpendicular to the extension direction ranges from 0 µm to 4 µm, since it has been held that where the general condition of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huh et al. with a minimum distance between the first edge and the second edge along a direction perpendicular to the extension direction ranges from 0 µm to 4 µm.
Doing so would provide a means to prevent or suppress a reduction of an aperture ratio.In regard to claim 3, Huh et al. discloses the limitations as applied to claim 1 above, and
wherein the first transparent conductive layer 191 comprises plural slits 92 (see e.g. paragraph [0069] and Figures 1-2).
In regard to claim 4, Huh et al. discloses the limitations as applied to claim 1 above, and
wherein the second edge (i.e. of drain electrode 175) and the second transparent conductive layer 131 are not overlapped (see e.g. annotated Figure 1 below and Figure 2).
In regard to claim 5, Huh et al. discloses the limitations as applied to claim 1 above, and
wherein the second transparent conductive layer 131 comprises a third edge, and the third edge and the drain electrode 175 are not overlapped (see e.g. annotated Figure 1, attached below).
In regard to claim 7, Huh et al. discloses the limitations as applied to claim 5 above, and
wherein the first transparent conductive layer 191 is at least partially overlapped with the drain electrode 175 (see e.g. Figures 1-2).
In regard to claim 12, Huh et al. discloses the limitations as applied to claim 1 above, but fails to disclose
a counter substrate 210 opposite to the substrate 110 (see e.g. paragraph [0050]), and
a display medium layer 3 (denoted “liquid crystal layer”, see e.g. paragraph [0052]) disposed between the first transparent conductive layer 191 and the counter substrate 210 (see e.g. Figure 2).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Huh et al. (US 2014/0152934 A1) in view of Ahn (US 2006/0121634 A1) and further in view of Kimura et al. (US 2007/0146591 A1).
In regard to claim 9, Huh et al., in view of Ahn, discloses the limitations as applied to claim 1 above, but fails to disclose
wherein the second transparent conductive layer does not overlap the drain electrode.
However, Kimura et al. discloses (see e.g. Figures 1-2):
wherein the second transparent conductive layer 103 does not overlap the drain electrode 109.
Given the teachings of Kimura et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huh et al., in view of Ahn, with wherein the second transparent conductive layer does not overlap the drain electrode.
Doing so would prevent unwanted parasitic capacitances between electrode layers.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Huh et al. (US 2014/0152934 A1) in view of Ahn (US 2006/0121634 A1) and further in view of Ono (US 2015/0070619 A1).
In regard to claim 10, Huh et al., in view of Ahn, discloses the limitations as applied to claim 1 above, but fails to disclose
wherein a projection of the source electrode on the substrate is completely located in a projection of the semiconductor layer on the substrate.
However, Ono discloses (see e.g. Figures 2-3):
wherein a projection of the source electrode 52 on the substrate 16 is completely located in a projection of the semiconductor layer 60 on the substrate 16.
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huh et al., in view of Ahn, with wherein a projection of the source electrode on the substrate is completely located in a projection of the semiconductor layer on the substrate.
Doing so would provide a larger contact between the source electrode and the semiconductor layer.
In regard to claim 11, Huh et al. discloses the limitations as applied to claim 10 above, and
wherein a projection of the drain electrode 175 on the substrate 110 is located in the projection of the semiconductor layer 154 on the substrate 110.
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Allowable Subject Matter
Claims 13-15 and 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter.
In regard to independent claim 13 and dependent claims 14-15 and 17-20, the closest prior art references fail to disclose all of the limitations of claim 13, as cited above, including the combination of limitations, “a first transparent conductive layer disposed on the substrate, wherein the first transparent conductive layer electrically connects to the drain electrode through the via hole; and a second transparent conductive layer disposed between the substrate and the first transparent conductive layer, wherein the second transparent conductive layer and the via hole are not overlapped, wherein a projection of the second transparent conductive layer on the substrate has a first edge, and a projection of the drain electrode on the substrate has a second edge adjacent to the first edge; wherein the drain electrode comprises a transition edge, the transition edge being located outside the scan line and not overlapped with the second transparent conductive layer; wherein the drain electrode further comprises a fourth edge, the transition edge is connected between the second edge and the fourth edge, and the second edge and the fourth edge are not overlapped with the second transparent conductive layer; wherein the scan line extends along an extension direction, and the fourth edge is substantially perpendicular to the extension direction; and wherein the transition edge is one of an arc edge or an inclined edge.”
Conclusion
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/JESSICA M MERLIN/Primary Examiner, Art Unit 2871