Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the arguments filed on 04/20/2026. Claims 1-4, 7-14 and 17-21 are pending. Foreign priority condition is met and reflected in Bib data sheet.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 12 and 20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The added limitation in the amended claims 1, 12 and 20 “wherein an energy loss by a leakage current increases from a first initial value over time and an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value” does not have sufficient support in the specification. The specification discloses the "time t1 and time t2 " are in paragraph [0051] for Fig 4 but not specifically teach first initial value over time and second initial value over time. Claim 1, 12 and 20 are therefore rejected under 35 U.S.C. 112 (pre-AIA ), first
paragraph as failing to comply with the written description requirement. Dependent
claims 2-4, 7-11, 13-14, 17-19 and 21 are rejected based on their dependency on rejected claims 1, 12 and 20.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 12 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-
AIA ), second paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which the inventor or a joint inventor, or
for pre-AIA the applicant regards as the invention. Claim 1, 12 and 20 amendment states “a first initial value over time” and “a second initial value over time” which are unknown and not defined anywhere where the time starts and how are they related to each other. The specification discloses the "time t1 and time t2 " are in paragraph [0051] for Fig 4 but not specifically teach first initial value over time and second initial value over time.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 7-14 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US 20230064572 A1) in view of Fang et al. (US 10714205 B1) hereinafter PARK and Fang.
Regarding claim 1, PARK teaches A memory device comprising: a command
decoder configured to obtain a command; (See Fig 3, paragraph [0058], illustrates memory device 200 may include a command decoder that decodes a command CMD received from the memory controller)
a timer configured to measure an operation time of an idle mode based on the idle mode being entered according to the command; and (See Fig 1, 2 and 3, paragraph [0060], illustrates timer 310 may perform operation of measuring first interval time of idle mode when receiving first command (Fig1 step S100 and S300))
a control circuit configured to: compare the operation time and a reference time; and control a state of a power control operation for at least one semiconductor device in the idle mode based on a result of the comparing. (See Fig 3, 4 and 9, paragraph [0096], illustrates power gating control circuit 332 may compare the first time interval or in other words operation time based on the measured time signal TMS and the reference time interval signal TREFS and may generate power gating control based on the result of comparing)
PARK teaches memory system with power control operation above. However, PARK does not explicitly teach wherein an energy loss by a leakage current increases from a first initial value over time and
an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value, and
wherein during the reference time, a difference between the energy loss by the leakage current and the energy loss by the operation current is within a predetermined range
On the other hand, Fang which also relates to memory system with power control operation teaches wherein an energy loss by a leakage current increases from a first initial value over time and (See Fig 23 and 26, col 27 line 57-67, illustrates comparator 1201 compares currents where leakage current maybe higher than stepping current or in other words operation current between two timing points)
an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value, and (See Fig 23 and 26, col 27 line 57-67, illustrates comparator 1201 compares currents where leakage current maybe lower than stepping current or in other words operation current between two timing points)
wherein during the reference time, a difference between the energy loss by the leakage current and the energy loss by the operation current is within a predetermined range (See Fig 23 and 26, col 28 line 1-5, illustrates if the result of comparison between leakage current and stepping or operation current is within range during a settling time, then data value is latched otherwise block is marked as bad)
Both PARK and Fang relate to memory system with power control operation
(see PARK, abstract, and see Fang, abstract, regarding power control operation in
memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine PARK with Fang by incorporating memory
system with power control operation by power gating and back bias devices, as taught
by Fang, to enable comparator 1201 to compare currents where leakage current maybe higher or lower than stepping current or in other words operation current between two timing points and if the result of comparison between leakage current and stepping or operation current is within range during a settling time, then data value is latched otherwise block is marked as bad. The combined system of PARK – Fang
allows precise and efficient leakage detection mechanisms that can operate according to current and voltage levels normally used in the memory operations of the device as mentioned in col 2 line 55-59. Therefore, the combination of PARK – Fang improves the accuracy and speed of leakage detection. See Fang, col 28 line 67.
Regarding claim 2, PARK in view of Fang teaches memory system with power control operation in claim 1. However, PARK - Fang combination does not explicitly teach The memory device of claim 1, wherein the control circuit is further configured to control the power control operation for the at least one semiconductor device in an enabled state based on the operation time being greater than or equal to the reference time
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 1, wherein the control circuit is further configured to control the power control operation for the at least one semiconductor device in an enabled state based on the operation time being greater than or equal to the reference time. (See Fig 2 and 22, paragraph [0132], illustrates at step S500 when first interval time is less than reference time or in other words operation time is greater than reference time, unperform power control operation or put memory device in enable state)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 2.
Regarding claim 3, PARK in view of Fang teaches memory system with power control operation in claim 2. However, PARK - Fang combination does not explicitly teach The memory device of claim 2, wherein the control circuit is further configured to control the power control operation for the at least one semiconductor device in a disabled state based on the operation time being less than the reference time
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 2, wherein the control circuit is further configured to control the power control operation for the at least one semiconductor device in a disabled state based on the operation time being less than the reference time. (See Fig 2 and 22, paragraph [0131], illustrates at step S500 when first interval time is greater than reference time or in other words operation time is less than reference time, perform power control operation or put memory device in disable state)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 3.
Regarding claim 4, PARK in view of Fang teaches memory system with power control operation in claim 1. However, PARK - Fang combination does not explicitly teach The memory device of claim 1, wherein the power control operation comprises a dynamic body-bias (DBB) operation and a power gating (PG) operation for the at least one semiconductor device
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 1, wherein the power control operation comprises a dynamic body-bias (DBB) operation and a power gating (PG) operation for the at least one semiconductor device. (See Fig 10, paragraph [0097] and [0101], illustrates power gating control circuit 332 controlling power control operation and adaptive body bias control circuit 336 controlling body bias operation on memory device)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 4.
Regarding claim 7, PARK in view of Fang teaches memory system with power control operation in claim 1. However, PARK - Fang combination does not explicitly teach The memory device of claim 1, wherein, based on a different command from the command being obtained from a memory controller,
the reference time is determined based on temperature information identified based on a cycle in which the different command is inputted
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 5, wherein, based on a different command from the command being obtained from a memory controller, (See Fig 1 and 2 paragraph [0037] and [0039], illustrates different commands are received from controller outside of memory device)
the reference time is determined based on temperature information identified based on a cycle in which the different command is inputted. (See Fig 1 paragraph [0038], illustrates at step S200 reference time maybe adjusted or controlled based on process, voltage and temperature (PVT) variation associated with or related to the memory device)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 7.
Regarding claim 8, PARK in view of Fang teaches memory system with power control operation in claim 1. However, PARK - Fang combination does not explicitly teach The memory device of claim 1, wherein the reference time is determined based on temperature information measured within the memory device regardless of a memory controller
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 5, wherein the reference time is determined based on temperature information measured within the memory device regardless of a memory controller. (See Fig 1 paragraph [0060], illustrates at step S300 and operation of internally measuring first time interval based on process, voltage and temperature variation associated with the memory device)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, PARK in view of Fang teaches memory system with power control operation in claim 1. However, PARK - Fang combination does not explicitly teach The memory device of claim 1, wherein the reference time is determined to decrease as a temperature increases and determined to increase as the temperature decreases
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 5, wherein the reference time is determined to decrease as a temperature increases and determined to increase as the temperature decreases. (See Fig 8 paragraph [0090], illustrates in table 322c reference time is inversely proportional to temperature. In other words, reference time decreases when temperature increases and vice versa)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 9.
Regarding claim 10, PARK in view of Fang teaches memory system with power control operation in claim 2. However, PARK - Fang combination does not explicitly teach The memory device of claim 2, wherein in the enabled state, a reverse body bias is applied to a first semiconductor device to which a dynamic body-bias (DBB) operation is applied among the at least one semiconductor device,
and a second semiconductor device to which a PG operation is applied among the at least one semiconductor device is controlled in a turned-off state
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 2, wherein in the enabled state, a reverse body bias is applied to a first semiconductor device to which a dynamic body-bias (DBB) operation is applied among the at least one semiconductor device, (See Fig 10 paragraph [0104], illustrates a body bias operation is implemented with body bias voltage VBBN and VBBP being applied to the semiconductor device 400)
and a second semiconductor device to which a PG operation is applied among the at least one semiconductor device is controlled in a turned-off state. (See Fig 10 paragraph [0102], illustrates a power gating operation is implemented with PGC control signal being applied for enabling or disabling the semiconductor device 334)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 10.
Regarding claim 11, PARK in view of Fang teaches memory system with power control operation in claim 3. However, PARK - Fang combination does not explicitly teach The memory device of claim 3, wherein in the disabled state, a forward body bias is applied or a source voltage is applied to a first semiconductor device to which a dynamic body-bias (DBB) operation is applied among the at least one semiconductor device, and
a second semiconductor device to which a PG operation is applied among the at least one semiconductor device is controlled in a turned-on state
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 3, wherein in the disabled state, a forward body bias is applied or a source voltage is applied to a first semiconductor device to which a dynamic body-bias (DBB) operation is applied among the at least one semiconductor device, and (See Fig 10 paragraph [0104], illustrates a body bias operation is implemented with body bias voltage VBBN and VBBP being applied to the semiconductor device 400)
a second semiconductor device to which a PG operation is applied among the at least one semiconductor device is controlled in a turned-on state. (See Fig 10 paragraph [0102], illustrates a power gating operation is implemented with PGC control signal being applied for enabling or disabling the semiconductor device 334)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 1 is equally applicable to claim 11.
Regarding claim 12, PARK teaches A method of operating a memory device, the method comprising: obtaining a command for entering an idle mode; (See Fig 2 paragraph [0037], illustrates the memory device may receive the first command CMDE (step S100). The first command CMDE may be a command for entering the idle mode 120)
measuring an operation time of the idle mode based on the idle mode being entered; and (See Fig 1, 2 and 3, paragraph [0060], illustrates timer 310 may perform operation of measuring first interval time of idle mode when receiving first command (Fig1 step S100 and S300))
comparing the operation time and a reference time and controlling a state of a power control operation for at least one semiconductor device in the idle mode based on a result of comparison. (See Fig 3, 4 and 9, paragraph [0096], illustrates power gating control circuit 332 may compare the first time interval or in other words operation time based on the measured time signal TMS and the reference time interval signal TREFS and may generate power gating control based on the result of comparing)
PARK teaches memory system with power control operation above. However, PARK does not explicitly teach wherein an energy loss by a leakage current increases from a first initial value over time and
an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value, and
wherein the reference time is determined as a time in which a difference between the energy loss by the leakage current and the energy loss by the operation current corresponds to within a predetermined range
On the other hand, Fang which also relates to memory system with power control operation teaches wherein an energy loss by a leakage current increases from a first initial value over time and (See Fig 23 and 26, col 27 line 57-67, illustrates comparator 1201 compares currents where leakage current maybe higher than stepping current or in other words operation current between two timing points)
an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value, and (See Fig 23 and 26, col 27 line 57-67, illustrates comparator 1201 compares currents where leakage current maybe lower than stepping current or in other words operation current between two timing points)
wherein the reference time is determined as a time in which a difference between the energy loss by the leakage current and the energy loss by the operation current corresponds to within a predetermined range (See Fig 23 and 26, col 28 line 1-5, illustrates if the result of comparison between leakage current and stepping or operation current is within range during a settling time, then data value is latched otherwise block is marked as bad)
Both PARK and Fang relate to memory system with power control operation
(see PARK, abstract, and see Fang, abstract, regarding power control operation in
memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine PARK with Fang by incorporating memory
system with power control operation by power gating and back bias devices, as taught
by Fang, to enable comparator 1201 to compare currents where leakage current maybe higher or lower than stepping current or in other words operation current between two timing points and if the result of comparison between leakage current and stepping or operation current is within range during a settling time, then data value is latched otherwise block is marked as bad. The combined system of PARK – Fang
allows precise and efficient leakage detection mechanisms that can operate according to current and voltage levels normally used in the memory operations of the device as mentioned in col 2 line 55-59. Therefore, the combination of PARK – Fang improves the accuracy and speed of leakage detection. See Fang, col 28 line 67.
Regarding claim 13, PARK in view of Fang teaches memory system with power control operation in claim 12. However, PARK - Fang combination does not explicitly teach The method of claim 12, wherein the controlling the state of the power control operation includes controlling the power control operation for the at least one semiconductor device in an enabled state based on the operation time being greater than or equal to the reference time
On the other hand, PARK which also relates to memory system with power control operation teaches The method of claim 12, wherein the controlling the state of the power control operation includes controlling the power control operation for the at least one semiconductor device in an enabled state based on the operation time being greater than or equal to the reference time. (See Fig 2 and 22, paragraph [0132], illustrates at step S500 when first interval time is less than reference time or in other words operation time is greater than reference time, unperform power control operation or put memory device in enable state)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 12 is equally applicable to claim 13.
Regarding claim 14, PARK in view of Fang teaches memory system with power control operation in claim 13. However, PARK - Fang combination does not explicitly teach The method of claim 13, wherein the controlling the state of the power control operation includes controlling the power control operation for the at least one semiconductor device in a disabled state based on the operation time being less than the reference time
On the other hand, PARK which also relates to memory system with power control operation teaches The method of claim 13, wherein the controlling the state of the power control operation includes controlling the power control operation for the at least one semiconductor device in a disabled state based on the operation time being less than the reference time. (See Fig 2 and 22, paragraph [0131], illustrates at step S500 when first interval time is greater than reference time or in other words operation time is less than reference time, perform power control operation or put memory device in disable state)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 12 is equally applicable to claim 14.
Regarding claim 17, PARK in view of Fang teaches memory system with power control operation in claim 12. However, PARK - Fang combination does not explicitly teach The method of claim 15, wherein, based on a different command from the command being obtained from a memory controller,
the reference time is determined based on temperature information identified based on a cycle in which the different command is inputted
On the other hand, PARK which also relates to memory system with power control operation teaches The method of claim 12, wherein, based on a different command from the command being obtained from a memory controller, (See Fig 1 and 2 paragraph [0037] and [0039], illustrates different commands are received from controller outside of memory device)
the reference time is determined based on temperature information identified based on a cycle in which the different command is inputted. (See Fig 1 paragraph [0038], illustrates at step S200 reference time maybe adjusted or controlled based on process, voltage and temperature (PVT) variation associated with or related to the memory device)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 12 is equally applicable to claim 17.
Regarding claim 18, PARK in view of Fang teaches memory system with power control operation in claim 12. However, PARK - Fang combination does not explicitly teach The method of claim 15, wherein the reference time is determined based on temperature information measured within the memory device regardless of a memory controller
On the other hand, PARK which also relates to memory system with power control operation teaches The method of claim 15, wherein the reference time is determined based on temperature information measured within the memory device regardless of a memory controller. (See Fig 1 paragraph [0060], illustrates at step S300 and operation of internally measuring first time interval based on process, voltage and temperature variation associated with the memory device)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 12 is equally applicable to claim 18.
Regarding claim 19, PARK in view of Fang teaches memory system with power control operation in claim 12. However, PARK - Fang combination does not explicitly teach The method of claim 12, wherein the reference time is determined to decrease as a temperature increases and determined to increase as the temperature decreases
On the other hand, PARK which also relates to memory system with power control operation teaches The method of claim 12, wherein the reference time is determined to decrease as a temperature increases and determined to increase as the temperature decreases. (See Fig 8 paragraph [0090], illustrates in table 322c reference time is inversely proportional to temperature. In other words, reference time decreases when temperature increases and vice versa)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 12 is equally applicable to claim 19.
Regarding claim 20, PARK teaches A memory system comprising: a memory device; and a memory controller configured to control the memory device, wherein the memory device comprises:
a command decoder configured to obtain a command; based on an idle mode being entered according to the command, (See Fig 3, paragraph [0058], illustrates memory device 200 may include a command decoder that decodes a command CMD received from the memory controller)
a timer configured to measure an operation time of the idle mode; and (See Fig 1, 2 and 3, paragraph [0060], illustrates timer 310 may perform operation of measuring first interval time of idle mode when receiving first command (Fig1 step S100 and S300))
a control circuit configured to compare the operation time and a reference time and control a state of a power control operation for at least one semiconductor device in the idle mode based on a result of comparison. (See Fig 3, 4 and 9, paragraph [0096], illustrates power gating control circuit 332 may compare the first time interval or in other words operation time based on the measured time signal TMS and the reference time interval signal TREFS and may generate power gating control based on the result of comparing)
PARK teaches memory system with power control operation above. However, PARK does not explicitly teach wherein an energy loss by a leakage current increases from a first initial value over time and
an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value, and
wherein during the reference time, a difference between the energy loss by the leakage current and the energy loss by the operation current is within a predetermined range
On the other hand, Fang which also relates to memory system with power control operation teaches wherein an energy loss by a leakage current increases from a first initial value over time and (See Fig 23 and 26, col 27 line 57-67, illustrates comparator 1201 compares currents where leakage current maybe higher than stepping current or in other words operation current between two timing points)
an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value, and (See Fig 23 and 26, col 27 line 57-67, illustrates comparator 1201 compares currents where leakage current maybe lower than stepping current or in other words operation current between two timing points)
wherein during the reference time, a difference between the energy loss by the leakage current and the energy loss by the operation current is within a predetermined range (See Fig 23 and 26, col 28 line 1-5, illustrates if the result of comparison between leakage current and stepping or operation current is with in range during a settling time, then data value is latched otherwise block is marked as bad)
Both PARK and Fang relate to memory system with power control operation
(see PARK, abstract, and see Fang, abstract, regarding power control operation in
memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine PARK with Fang by incorporating memory
system with power control operation by power gating and back bias devices, as taught
by Fang, to enable comparator 1201 to compare currents where leakage current maybe higher or lower than stepping current or in other words operation current between two timing points and if the result of comparison between leakage current and stepping or operation current is within range during a settling time, then data value is latched otherwise block is marked as bad. The combined system of PARK – Fang
allows precise and efficient leakage detection mechanisms that can operate according to current and voltage levels normally used in the memory operations of the device as mentioned in col 2 line 55-59. Therefore, the combination of PARK – Fang improves the accuracy and speed of leakage detection. See Fang, col 28 line 67.
Regarding claim 21, PARK in view of Fang teaches memory system with power control operation in claim 1. However, PARK - Fang combination does not explicitly teach The memory device of claim 1, wherein the reference time comprises a time at which the energy loss by the leakage current is equal to the energy loss by the operation current
On the other hand, PARK which also relates to memory system with power control operation teaches The memory device of claim 1, wherein the reference time comprises a time at which the energy loss by the leakage current is equal to the energy loss by the operation current. (See Fig 1 paragraph [0060], illustrates in step S200 adjusting the reference time interval used to determine the start time point of the power control operation 130 based on the process, voltage and temperature variation associated with the memory device 200. In other words, reference time may be determined by memory device characteristics which may include leakage current and operation current which are based on process, voltage and temperature variation)
The same motivation that was utilized for combining PARK and Fang as set
forth in claim 12 is equally applicable to claim 19.
Response to Arguments
Applicant’s arguments filed on 04/20/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1,12 and 20 amendment mapping by primary
and secondary references in page 9-10 of the response: " Pages 10-12 of the Office Action acknowledges that Park fails to disclose or suggest the subject matter of claims 6 and 16. However, the Office Action contends that Pedersen remedies the deficiencies of Park, relying on FIGS. 11 and 12, and paragraphs [0063] and [0069] of Pedersen. Applicant respectfully disagrees.
Pedersen appears to disclose adjusting operational modes or timing parameters in
response to general power conditions or system states. However, Pedersen does not disclose balancing two energy losses that evolve differently over time, nor of identifying a transitional region in which the difference between those energy losses falls within a predetermined range. Thus, Pedersen fails to disclose or suggest "an energy loss by a leakage current increases from a first initial value over time and an energy loss by an operation current decreases from a second initial value over time, the second initial value being greater than the first initial value, and wherein during the reference time, a difference between the energy loss by the leakage current and the energy loss by the operation current is within a predetermined range, as recited in claim
In summary, applicant argued that primary reference PARK or secondary
reference Pedersen do not teach amended limitation energy loss with respect to operation energy loss may be different over time and the difference to be within reference range. The amendment necessitates adding secondary reference Fang in this regard. For further clarification examiner cites portion from Fang. Also, for applicant’s
understanding examiner would like to explain the teachings of Fang and examiner’s interpretation in more detail here. See Fig 23 and 26, col 27 line 57-67, Fang teaches comparator 1201 compares currents where leakage current maybe higher than stepping current or in other words operation current between two timing points. Also See Fig 23 and 26, col 27 line 57-67, Fang teaches comparator 1201 compares currents where leakage current maybe lower than stepping current or in other words operation current between two timing points. Also See Fig 23 and 26, col 28 line 1-5, Fang teaches if the result of comparison between leakage current and stepping or operation current is within range during a settling time, then data value is latched otherwise block is marked as bad. The cited portions clearly teach leakage current with respect to stepping current or operation current may vary over time and if the comparison between them is within range. Thus, the rejection of amended claims 1,12 and 20 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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