Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/31/2024 is being
considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being
anticipated by PARK et al. (US 20230064572 A1) hereinafter PARK.
Regarding claim 1, PARK teaches A memory device comprising: a command
decoder configured to obtain a command; (See Fig 3, paragraph [0058], illustrates memory device 200 may include a command decoder that decodes a command CMD received from the memory controller)
a timer configured to measure an operation time of an idle mode based on the idle mode being entered according to the command; and (See Fig 1, 2 and 3, paragraph [0060], illustrates timer 310 may perform operation of measuring first interval time of idle mode when receiving first command (Fig1 step S100 and S300))
a control circuit configured to: compare the operation time and a reference time; and control a state of a power control operation for at least one semiconductor device in the idle mode based on a result of the comparing. (See Fig 3, 4 and 9, paragraph [0096], illustrates power gating control circuit 332 may compare the first time interval or in other words operation time based on the measured time signal TMS and the reference time interval signal TREFS and may generate power gating control based on the result of comparing)
Regarding claim 2, PARK teaches The memory device of claim 1, wherein the control circuit is further configured to control the power control operation for the at least one semiconductor device in an enabled state based on the operation time being greater than or equal to the reference time. (See Fig 2 and 22, paragraph [0132], illustrates at step S500 when first interval time is less than reference time or in other words operation time is greater than reference time, unperform power control operation or put memory device in enable state)
Regarding claim 3, PARK teaches The memory device of claim 2, wherein the control circuit is further configured to control the power control operation for the at least one semiconductor device in a disabled state based on the operation time being less than the reference time. (See Fig 2 and 22, paragraph [0131], illustrates at step S500 when first interval time is greater than reference time or in other words operation time is less than reference time, perform power control operation or put memory device in disable state)
Regarding claim 4, PARK teaches The memory device of claim 1, wherein the power control operation comprises a dynamic body-bias (DBB) operation and a power gating (PG) operation for the at least one semiconductor device. (See Fig 10, paragraph [0097] and [0101], illustrates power gating control circuit 332 controlling power control operation and adaptive body bias control circuit 336 controlling body bias operation on memory device)
Regarding claim 5, PARK teaches The memory device of claim 1, wherein the reference time is determined based on a result of comparing a leakage current flowing in the idle mode and an operation current flowing during performance of the power control operation. (See Fig 7,8,11 and 12 paragraph [0091] and [0092], illustrates reference time TREF is based on process, voltage, temperature and characteristics of transistors which determines leakage and operation current)
Regarding claim 7, PARK teaches The memory device of claim 5, wherein, based on a different command from the command being obtained from a memory controller, (See Fig 1 and 2 paragraph [0037] and [0039], illustrates different commands are received from controller outside of memory device)
the reference time is determined based on temperature information identified based on a cycle in which the different command is inputted. (See Fig 1 paragraph [0038], illustrates at step S200 reference time maybe adjusted or controlled based on process, voltage and temperature (PVT) variation associated with or related to the memory device)
Regarding claim 8, PARK teaches The memory device of claim 5, wherein the reference time is determined based on temperature information measured within the memory device regardless of a memory controller. (See Fig 1 paragraph [0060], illustrates at step S300 and operation of internally measuring first time interval based on process, voltage and temperature variation associated with the memory device)
Regarding claim 9, PARK teaches The memory device of claim 5, wherein the reference time is determined to decrease as a temperature increases and determined to increase as the temperature decreases. (See Fig 8 paragraph [0090], illustrates in table 322c reference time is inversely proportional to temperature. In other words, reference time decreases when temperature increases and vice versa)
Regarding claim 10, PARK teaches The memory device of claim 2, wherein in the enabled state, a reverse body bias is applied to a first semiconductor device to which a dynamic body-bias (DBB) operation is applied among the at least one semiconductor device, (See Fig 10 paragraph [0104], illustrates a body bias operation is implemented with body bias voltage VBBN and VBBP being applied to the semiconductor device 400)
and a second semiconductor device to which a PG operation is applied among the at least one semiconductor device is controlled in a turned-off state. (See Fig 10 paragraph [0102], illustrates a power gating operation is implemented with PGC control signal being applied for enabling or disabling the semiconductor device 334)
Regarding claim 11, PARK teaches The memory device of claim 3, wherein in the disabled state, a forward body bias is applied or a source voltage is applied to a first semiconductor device to which a dynamic body-bias (DBB) operation is applied among the at least one semiconductor device, and (See Fig 10 paragraph [0104], illustrates a body bias operation is implemented with body bias voltage VBBN and VBBP being applied to the semiconductor device 400)
a second semiconductor device to which a PG operation is applied among the at least one semiconductor device is controlled in a turned-on state. (See Fig 10 paragraph [0102], illustrates a power gating operation is implemented with PGC control signal being applied for enabling or disabling the semiconductor device 334)
Regarding claim 12, PARK teaches A method of operating a memory device, the method comprising: obtaining a command for entering an idle mode; (See Fig 2 paragraph [0037], illustrates the memory device may receive the first command CMDE (step S100). The first command CMDE may be a command for entering the idle mode 120)
measuring an operation time of the idle mode based on the idle mode being entered; and (See Fig 1, 2 and 3, paragraph [0060], illustrates timer 310 may perform operation of measuring first interval time of idle mode when receiving first command (Fig1 step S100 and S300))
comparing the operation time and a reference time and controlling a state of a power control operation for at least one semiconductor device in the idle mode based on a result of comparison. (See Fig 3, 4 and 9, paragraph [0096], illustrates power gating control circuit 332 may compare the first time interval or in other words operation time based on the measured time signal TMS and the reference time interval signal TREFS and may generate power gating control based on the result of comparing)
Regarding claim 13, PARK teaches The method of claim 12, wherein the controlling the state of the power control operation includes controlling the power control operation for the at least one semiconductor device in an enabled state based on the operation time being greater than or equal to the reference time. (See Fig 2 and 22, paragraph [0132], illustrates at step S500 when first interval time is less than reference time or in other words operation time is greater than reference time, unperform power control operation or put memory device in enable state)
Regarding claim 14, PARK teaches The method of claim 13, wherein the controlling the state of the power control operation includes controlling the power control operation for the at least one semiconductor device in a disabled state based on the operation time being less than the reference time. (See Fig 2 and 22, paragraph [0131], illustrates at step S500 when first interval time is greater than reference time or in other words operation time is less than reference time, perform power control operation or put memory device in disable state)
Regarding claim 15, PARK teaches The method of claim 12, wherein the reference time is determined based on a result of comparing a leakage current flowing in the idle mode and an operation current flowing during performance of the power control operation. (See Fig 7,8,11 and 12 paragraph [0091] and [0092], illustrates reference time TREF is based on process, voltage, temperature and characteristics of transistors which determines leakage and operation current)
Regarding claim 17, PARK (US 20230064572 A1) teaches The method of claim 15, wherein, based on a different command from the command being obtained from a memory controller, (See Fig 1 and 2 paragraph [0037] and [0039], illustrates different commands are received from controller outside of memory device)
the reference time is determined based on temperature information identified based on a cycle in which the different command is inputted. (See Fig 1 paragraph [0038], illustrates at step S200 reference time maybe adjusted or controlled based on process, voltage and temperature (PVT) variation associated with or related to the memory device)
Regarding claim 18, PARK teaches The method of claim 15, wherein the reference time is determined based on temperature information measured within the memory device regardless of a memory controller. (See Fig 1 paragraph [0060], illustrates at step S300 and operation of internally measuring first time interval based on process, voltage and temperature variation associated with the memory device)
Regarding claim 19, PARK teaches The method of claim 15, wherein the reference time is determined to decrease as a temperature increases and determined to increase as the temperature decreases. (See Fig 8 paragraph [0090], illustrates in table 322c reference time is inversely proportional to temperature. In other words, reference time decreases when temperature increases and vice versa)
Regarding claim 20, PARK teaches A memory system comprising: a memory device; and a memory controller configured to control the memory device, wherein the memory device comprises:
a command decoder configured to obtain a command; based on an idle mode being entered according to the command, (See Fig 3, paragraph [0058], illustrates memory device 200 may include a command decoder that decodes a command CMD received from the memory controller)
a timer configured to measure an operation time of the idle mode; and (See Fig 1, 2 and 3, paragraph [0060], illustrates timer 310 may perform operation of measuring first interval time of idle mode when receiving first command (Fig1 step S100 and S300))
a control circuit configured to compare the operation time and a reference time and control a state of a power control operation for at least one semiconductor device in the idle mode based on a result of comparison. (See Fig 3, 4 and 9, paragraph [0096], illustrates power gating control circuit 332 may compare the first time interval or in other words operation time based on the measured time signal TMS and the reference time interval signal TREFS and may generate power gating control based on the result of comparing)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over PARK in view of Pedersen et al. (US 20230131586 A1) hereinafter Pedersen.
Regarding claim 6, PARK teaches memory system with power control operation in claim 5. However, PARK does not explicitly teach The memory device of The memory device of wherein an energy loss by the leakage current increases over time and the energy loss by the operation current decreases over time, and wherein during the reference time, a difference between the energy loss by the leakage current and the energy loss by the operation current is within a predetermined range
On the other hand, Pedersen which also relates to memory system with power
control operation teaches The memory device of The memory device of wherein an energy loss by the leakage current increases over time and the energy loss by the operation current decreases over time, and wherein during the reference time, a difference between the energy loss by the leakage current and the energy loss by the operation current is within a predetermined range. (See Fig 11 and 12 paragraph [0063] and [0069], illustrates leakage current and operating current over time being function of voltage and also current being dependent on capacitor or transistor material where material property can be within range)
Both PARK and Pedersen relate to memory system with power control operation
(see PARK, abstract, and see Pedersen, abstract, regarding power control operation in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine PARK with Pedersen by incorporating memory system with power control operation by power gating and back bias devices, as taught by Pedersen, to enable leakage current and operating current over time being function of voltage and also current being dependent on capacitor or transistor material where material property can be within range. The combined system of PARK – Pedersen allows to receive a command from a host device when in the standby mode; a voltage regulator having an output that provides a supply voltage for accessing contents of memory cells in the memory device in abstract. Therefore, the combination of PARK – Pedersen improves current consumption. See Pedersen, paragraph [0055].
Regarding claim 16, PARK teaches memory system with power control operation in claim 15. However, PARK does not explicitly teach The method of The method of wherein an energy loss by the leakage current increases over time and the energy loss by the operation current decreases over time, and wherein the reference time is determined as a time in which a difference between the energy loss by the leakage current and the energy loss by the operation current corresponds to within a predetermined range
On the other hand, Pedersen which also relates to memory system with power
control operation teaches The method of The method of wherein an energy loss by the leakage current increases over time and the energy loss by the operation current decreases over time, and wherein the reference time is determined as a time in which a difference between the energy loss by the leakage current and the energy loss by the operation current corresponds to within a predetermined range. (See Fig 11 and 12 paragraph [0063] and [0069], illustrates leakage current and operating current over time being function of voltage and also current being dependent on capacitor or transistor material where material property can be within range)
Both PARK and Pedersen relate to memory system with power control operation
(see PARK, abstract, and see Pedersen, abstract, regarding power control operation in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine PARK with Pedersen by incorporating memory system with power control operation by power gating and back bias devices, as taught by Pedersen, to enable leakage current and operating current over time being function of voltage and also current being dependent on capacitor or transistor material where material property can be within range. The combined system of PARK – Pedersen allows to receive a command from a host device when in the standby mode; a voltage regulator having an output that provides a supply voltage for accessing contents of memory cells in the memory device in abstract. Therefore, the combination of PARK – Pedersen improves current consumption. See Pedersen, paragraph [0055].
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure.
a. Kim et al. (US 11054888 B2) teaches A power gating circuit is provided. The power gating circuit includes a logic gate group. The power gating circuit also includes a first switching circuit coupled to first and second supply voltages and the logic gate group. The power gating circuit further includes a second switching circuit coupled to the first and second supply voltages and the logic gate group. The first and second supply voltages are supplied to the logic gate group through the first switching circuit based on a voltage select signal. The first and second supply voltages are supplied to the logic gate group through the second switching circuit based on the voltage select signal and a power down signal.
b. Kim al. (US 10389349 B2) teaches A semiconductor apparatus may include a logic circuit and a power gating circuit including a gating transistor configured to apply a first supply voltage to the logic circuit based on an operation mode of the semiconductor apparatus. The semiconductor apparatus may be configured to monitor a characteristic of the logic circuit and adjust aback bias voltage to the gating transistor based on the characteristic of the logic circuit.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132