DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 5 is objected to because of the following informalities: Line 3 recites “a first portion of the cache” which should be --the first portion of the cache--. Appropriate correction is required.
Claims 12 and 19 are objected to for the same reasons as claim 5, as outlined above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8-9, 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Frey et al. (US 2010/0268886 A1) hereinafter Frey et al. in view of Okada et al. (US 2013/0311706 A1) hereinafter Okada et al.
Regarding claim 1, Frey et al. teaches a storage device, comprising:
a control circuit; a memory (effective address associated with memory storage Paragraphs [0033], see claim 1); and a cache, wherein the control circuit is configured:
to receive, from a host (processor core 202 generates load/store requests Paragraph [0022]), a caching hint identifying a first address (a DCBT instruction includes a TH field and RA/RB field, where a value of 11000 in the TH field provides an access hint that a program may soon access a portion of a cache block addressed by the DCBT instruction and the RA/RB field is used to provide the effective address Paragraphs [0033]-[0034]);
read a first quantity of data from the memory (the prefetch machine determines the cache block and the subsection thereof addressed by the DCBT instruction Paragraph [0038]); and
to store a portion of the first quantity of data in the cache, the first quantity being larger than the portion, the portion including a first data unit, having an address equal to the first address (prefetch machine prefetches only the indicated subsection of the addressed data into the cache Paragraph [0038]. Note that the data can be held concurrently and fully stored in the L2 cache and partially stored in the L3 cache Paragraphs [0023], [0035], [0038]).
Frey et al. teaches to read a first quantity of data from a memory and to store a portion of the data in a different cache memory. Frey et al. does not appear to explicitly teach, however, Okada et al. teaches a non-volatile memory (storage drive 303 is a non-volatile storage device for storing user data Paragraph [0033]), and to read a first quantity of data from the non-volatile memory (a read command is received from the host computer and the cluster retrieves the designated user data from a non-volatile semiconductor storage device (SSD) Paragraph [0084]).
The disclosures of Frey et al. and Okada et al., hereinafter FO, are analogous art to the claimed invention because they are in the same field of caching or prefetching data in a memory system. Because both Frey et al. and Okada et al. teach the use of associating hints with data for caching, it would have been obvious to one skilled in the art to substitute one type of memory for another to achieve the predictable result of retrieving data stored from a particular type of memory as disclosed by Okada, in this case, non-volatile SSD (KSR, MPEP 2143).
Regarding claim 2, FO teaches all of the features with respect to claim 1 as outlined above.
Frey et al. further teaches wherein: the portion of the first quantity of data includes a second data unit having a second address (a DCBT instruction includes a TH field and RA/RB field, where a value of 11000 in the TH field provides an access hint that a program may soon access a portion of a cache block addressed by the DCBT instruction and the RA/RB field is used to provide the effective address Paragraphs [0033]-[0034]), and Okada et al. further teaches the control circuit is further configured: to receive a host read command from the host, the host read command including the second address; and to store the second data unit in the cache based on the host read command (a read command is received from the host computer and the cluster retrieves the designated user data from a non-volatile semiconductor storage device (SSD) Paragraph [0084]).
Claims 8 and 15 are rejected under 35 USC 103 for the same reasons as claim 1, as outlined above.
Claims 9 and 16 are rejected under 35 USC 103 for the same reasons as claim 2, as outlined above.
Claim(s) 3, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over FO in further view of Durham et al. (US 2019/0108130 A1) hereinafter Durham et al.
Regarding claim 3, FO teaches all of the features with respect to claim 2 as outlined above.
FO does not appear to explicitly teach, however, Durham et al. teaches wherein the storing of the portion of the first quantity of data in the cache comprises: storing the portion of the first quantity of data in a first portion of the cache (cache 110 is comprised of multiple cachelines 115, where cachelines 115.sub.1 and 115.sub.2 combine into memory-line 115.sub.1 Paragraph [0024]); and storing the first data unit and the second data unit together in a bin of the first portion of the cache (memory requests can be issued on a sub-cacheline basis, where each sub-cacheline (i.e., slot) is analogous to a data unit Paragraphs [0038], [0041]).
The disclosures of FO and Durham et al., hereinafter FOD, are analogous art to the claimed invention because they are in the same field of endeavor of cache management and organization.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FOD before them, to modify the teachings of FO to include the teachings of Durham et al. since both FO teach storing data in a cache for future accesses. Therefore it is applying a known technique (storing data based on a sub-cacheline granularity [0038], [0041] of Durham et al.) to a known device (memory system performing prefetching data to a cache of Frey et al.) ready for improvement to yield predictable results (data is stored in a cacheline of Durham et al.), KSR, MPEP 2143.
Claims 10 and 17 are rejected under 35 USC 103 for the same reasons as claim 3, as outlined above.
Allowable Subject Matter
Claims 4-7, 11-14, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, “wherein: the portion of the first quantity of data includes a third data unit having a third address; the third address is stored in a history table; and the control circuit is configured to store the third data unit in the cache based on the third address being stored in the history table,” is not taught by the prior art. The closest prior art is FO in further view of Lafford et al. (US 2025/0272241 A1). Lafford et al. teaches prefetch tables to assist with various prefetch related operations by storing address regions of varying granularities with access count. Thus, Lafford et al. generally teaches a history table which lists addresses, however, is silent with regards to storing a third data unit within a portion of the first quantity of data based on the third address of the third data unit previously being stored in a history table. Claims 5-7 depend upon claim 4, thus, would be allowable for at least the same reasons as claim 4, as outlined above.
While one or more reasons are offered above citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of FO and Lafford et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Claims 11 and 18 recite subject matter substantially similar to that of claim 4 and would be allowable for the same reasons indicated above. Claims 12-14 and 19-20 depend upon claims 11 and 18, respectively, thus, would be allowable for at least the same reasons as claims 11 or 18, as outlined above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bert (US 2025/0013570 A1) teaches the prefetching of pages based on an access hint.
Hoffman et al. (US 2006/0047914 A1) teaches reading a portion of data from a page including the data at the predicted address into a pre-fetch buffer.
Punyamurtula et al. (US 2012/0131305 A1) teaches prefetching based on a cacheline granularity, where addresses are said to match if the bits which are significant to the granularity in use are equal.
Venugopal (US 2023/0315335 A1) teaches partially executing a speculative read command from a host identifying logical block addresses.
Arimilli et al. (US 2009/0198903 1) teaches using a hint to request either full cache lines or partial cache lines.
Kwon et al. (US 2025/0378031 A1) teaches a prefetch support circuit of the host device transmitting prefetch information used by a decision circuit of the memory device to determine prefetch addresses.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANE W BENNER whose telephone number is (571)270-0067. The examiner can normally be reached Mon - Thurs (8 AM - 5 PM).
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/ Primary Examiner, Art Unit 2139
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