DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 12/31/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 12/31/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Mikasa et al (US20140048860).
Regarding claim 1, Mikasa discloses an apparatus, comprising: a plurality of pillars extending in a first direction(FIG 2; [0110] discloses pillars P1-P3 in first direction); a plurality of word lines extending in a second direction(WL1-WL3 in second directions); a plurality of memory cells stacked in the first direction(FIG 2 & 4; [0100] discloses cell transistors in active region 7), wherein at least a memory cell of the plurality of memory cells is positioned between a word line of the plurality of word lines and a pillar of the plurality of pillars(FIG 2; region 7 comprising cell between WL1 and P1); and a plurality of voids separating the plurality of word lines from one another in the first direction(FIG 2; P1-P2 comprising voids e.g., P1-P3 boxes between WL1-WL3 e.g., P1 between WL1 and WL2, P2 between WL2 and WL3 and so on in the first direction).
Regarding claim 2, Mikasa discloses wherein an insulating material is disposed on sidewalls at least partially surrounding the plurality of voids (FIG 2; [0111] discloses S1 S2 S3 S4 insulating materials on side of P1-P2).
Regarding claim 3, Mikasa discloses wherein a dielectric material is disposed on sidewalls of the plurality of memory cells (16a comprising conductive materials on both sides of 7 regions).
Regarding claim 4, Mikasa discloses wherein an interior of the plurality of voids is separated from sidewalls of the plurality of pillars by an insulating material (P1-P2 voids separated by 15).
Regarding claim 5, Mikasa discloses wherein a conductive path extends from the word line to the pillar in a third direction, and wherein the first direction, the second direction, and the third direction are orthogonal to one another (FIG 2-3; 16s first direction X, second direction Y and third direction into the page e.g., Z (orthogonal to one another)).
Regarding claim 6, Mikasa discloses further comprising: a plurality of piers extending in the first direction (FIG 2; dummy pillars e.g., DP1-DP2 extended in first direction X), wherein the plurality of voids are enclosed at least in part by the plurality of word lines, the plurality of pillars, and the plurality of piers (P1-P2 voids are enclosed in part by WL1-WL3, P1-P2s, and DP1-P2).
Regarding claim 7, Mikasa discloses wherein a capacitance between adjacent word lines of the plurality of word lines is less than a threshold based at least in part on the plurality of voids separating the plurality of word lines from one another (FIG 2 & 4; [0018] discloses Pillar P through a capacitance contract A5 passes through A4 and 25, separates WL1-WL3 having Vt less than in part of P1-P2 voids separating WL1-WL3).
Regarding claim 8, Mikasa discloses wherein the plurality of voids each enclose a gaseous material (FIG 2; [0155] discloses pillars having impurity injection layer, n-type impurity having selective epitaxial growth to be carried out e.g., gaseous material).
Regarding claim 9, Mikasa discloses wherein the gaseous material comprises atmospheric air, a single gas, or another combination of gases ((FIG 2; [0155] discloses pillars having impurity injection layer, n-type impurity having selective epitaxial growth to be carried out e.g., atmospheres as gases).
Regarding claim 10, Mikasa discloses wherein the plurality of memory cells are separated from one another by the plurality of voids (FIG 2; P1-P2 voids (holes) separate plurality of memory cells in region 7).
Regarding claim 11, Mikasa discloses an apparatus, comprising: a plurality of memory cells stacked in a first direction(FIG 2 & 4; [0100] discloses cell transistors in active region 7) , wherein at least a memory cell of the plurality of memory cells is positioned between a word line of a plurality of word lines extending in a second direction and a pillar of a plurality of pillars extending in the first direction (FIG 2; region 7 comprising cell between WL1 and P1 in second and first direction); and a plurality of voids separating the plurality of word lines from one another in the first direction(FIG 2; P1-P2 comprising voids e.g., P1-P3 boxes between WL1-WL3 e.g., P1 between WL1 and WL2, P2 between WL2 and WL3 and so on in the first direction).
Regarding claim 12, Mikasa discloses wherein an insulating material is disposed on sidewalls at least partially surrounding the plurality of voids (FIG 2; [0111] discloses S1 S2 S3 S4 insulating materials on side of P1-P2).
Regarding claim 13, Mikasa discloses wherein a dielectric material is disposed on sidewalls of the plurality of memory cells (16a comprising conductive materials on both sides of 7 regions).
Regarding claim 14, Mikasa discloses wherein an interior of the plurality of voids is separated from sidewalls of the plurality of pillars by an insulating material (P1-P2 voids separated by 15).
Regarding claim 15, Mikasa discloses wherein a conductive path extends from the word line to the pillar in a third direction, and wherein the first direction, the second direction, and the third direction are orthogonal to one another (FIG 2-3; 16s first direction X, second direction Y and third direction into the page e.g., Z (orthogonal to one another)).
Regarding claim 16, Mikasa discloses further comprising: a plurality of piers extending in the first direction (FIG 2; dummy pillars e.g., DP1-DP2 extended in first direction X), wherein the plurality of voids are enclosed at least in part by the plurality of word lines, the plurality of pillars, and the plurality of piers (P1-P2 voids are enclosed in part by WL1-WL3, P1-P2s, and DP1-P2).
Regarding claim 17, Mikasa discloses wherein a capacitance between adjacent word lines of the plurality of word lines is less than a threshold based at least in part on the plurality of voids separating the plurality of word lines from one another (FIG 2 & 4; [0018] discloses Pillar P through a capacitance contract A5 passes through A4 and 25, separates WL1-WL3 having Vt less than in part of P1-P2 voids separating WL1-WL3).
Regarding claim 18, Mikasa discloses wherein the plurality of voids each enclose a gaseous material (FIG 2; [0155] discloses pillars having impurity injection layer, n-type impurity having selective epitaxial growth to be carried out e.g., gaseous material).
Regarding claim 19, Mikasa discloses wherein the plurality of memory cells are separated from one another by the plurality of voids (FIG 2; P1-P2 voids (holes) separate plurality of memory cells in region 7).
Regarding claim 20, Mikasa discloses an apparatus, comprising: a pillar extending in a first direction(FIG 2; P1-P2 in direction); a first word line extending in a second direction(FIG 2; WL1-WL3 in second direction); a plurality of memory cells stacked in the first direction(FIG 2 & 4; [0100] discloses cell transistors in active region 7 in the first direction), wherein at least a memory cell of the plurality of memory cells is positioned between the first word line and the pillar(FIG 2; region 7 comprising cell between WL1 and P1); and a void separating the first word line from a second word line in the first direction(FIG 2; P1-P2 comprising voids e.g., P1-P3 boxes between WL1-WL3 e.g., P1 between WL1 and WL2, P2 between WL2 and WL3 and so on in the first direction).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Sharma et al (US20200411078 FIG 3A; [0045] discloses 100 and having discloses 302 having a metal chalcogenides & 140s separated by 302).
Hasnat et al (US20190043882 FIG 1 &14; discloses plurality of word lines are separated by dielectric layers, and having airgap).
Thimmegoda et al (US20190043874 FIG 3; [0019 & 0035] discloses chalcogenide material, and dielectric 310 used to separate the word lines 308).
Lai et al (US10141221 FIG 8A, discloses first layer 18, separating the second layer 18 by dielectric layer 19 and having cavity e.g., 191 and 192).
Pellizer et al (USFIG 3b; 5; [0031 & 0050] discloses 202 being separated from word line driver by deep trench isolation having dielectric material; furthermore, 116 comprising chalcogenide material).
Baek et al (US20130148398 FIG 13 discloses air gap), Pekny et al (US20090230454 FIG 2B), Burns, Jr. et al (US6077745 FIG 15), & Kim et al (US20170062330 FIG 4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUNA A TECHANE/ Primary Examiner, Art Unit 2827
Prosecution Insights