DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species III in the reply filed on 9/2/26 is acknowledged. The traversal is on the ground(s) that the Requirement does not identify how the species differ and there is no serious search or examination burden. This is not found persuasive because for example, fig. 6a differs from fig. 5a and 5c via elements 72, 74, and bulk control of 70, while fig. 6a differs from fig. 6b via the Vdd connection to 72 and 74, and the gate connection 76. Therefore, there is a serious search burden because different strategies would be employed to search.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vulih (US 6,002,277).
Regarding claim 1, fig. 3 of Vulih discloses a solid state switch, comprising: a first field-effect transistor, FET [T12], comprising: a first terminal, a second terminal, a bulk terminal and a gate terminal, and configured to be switched between an on-state and an off-state; a second FET [T5] in series with the first FET, wherein the second FET comprises a first terminal, a second terminal, a bulk terminal, and a gate terminal, and wherein the second terminal of the first FET is connected to the second terminal of the second FET; and, a first buffer [BA2] comprising an output terminal coupled to the bulk terminal of the first FET, and an input terminal coupled to the first terminal of the first FET.
Regarding claim 8, fig. 3 of Vulih discloses wherein the first terminal of the first FET is a drain terminal, wherein the first terminal of the second FET is a drain terminal, wherein the second terminal of the first FET is a source terminal, wherein the second terminal of the second FET is a source terminal.
Regarding claim 9, fig. 3 of Vulih discloses wherein the first and second FET are both a first-type FET, wherein the first-type is n-type or p-type.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vulih in view of Jordan (US 2014/0225673).
Regarding claims 2 and 5, Vulih discloses the device as indicated above except wherein the first buffer is: a unity gain buffer, UGB; a voltage follower; or a cascade complementary source follower. However, par. 31 of Jordan describes implementing an amplifier, such as BA2 of Vulih, as a unity gain buffer. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the amplifier implementation as taught in Jordan for the purpose of utilizing a suitable and well-known type of amplifier design.
Claim(s) 6, 7, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vulih in view of Agam (US 2021/0125879).
Regarding claim 6, Vulih discloses the device as indicated above except wherein the first FET is a low voltage FET, and the second FET is a low voltage FET. However, par. 89 of Agam describes implementing a transistor as a low voltage one. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the low voltage transistor as taught in Agam for the purpose of utilizing a suitable and well-known type of transistor design.
Regarding claim 7, Vulih discloses the device as indicated above except wherein the first FET is an isolated FET, and the second FET is an isolated FET. However, par. 89 of Agam describes implementing a transistor as an isolated one. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the low voltage transistor as taught in Agam for the purpose of utilizing a suitable and well-known type of transistor design.
Regarding claims 18 and 19, Vulih discloses the device as indicated above except wherein the first and second FET is a JFET or a Silicon Carbide FET, SiC. However, par. 89 of Agam describes implementing a transistor as a JFET. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the JFET as taught in Agam for the purpose of utilizing a suitable and well-known type of transistor design.
Allowable Subject Matter
Claims 3, 4, and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Paladugu describes a bidirectional power switch circuit. Herrera describes a low capacitance analog switch.
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/SIBIN CHEN/Primary Examiner, Art Unit 2836
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