CTNF 19/007,345 CTNF 100691 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on April 17, 2025; September 9, 2025; and April 14, 2026 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. An applicant’s duty of disclosure of material information is not satisfied by presenting a patent examiner with “a mountain of largely irrelevant data from which he is presumed to have been able, with his expertise and with adequate time, to have found the critical data. It ignores the real world conditions under which examiners work.” Rohm & Haas Co. v. Crystal Chemical Co., 722 F.2d 1556, 1573, 220 U.S.P.Q. 289 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984). An applicant has a duty to not just disclose pertinent prior art references but to make a disclosure in such way as not to “bury” it within other disclosures of less relevant prior art. See Golden Valley Microwave Foods Inc. v. Weaver Popcorn Co. Inc., 24 U.S.P.Q.2d 1801 (N.D. Ind. 1992); Molins PLC v. Textron Inc., 26 U.S.P.Q.2d 1889, 1899 (D. Del. 1992); Penn Yan Boats, Inc. v. Sea Lark Boats, Inc. et al., 175 U.S.P.Q. 260, 272 (S.D. Fl. 1972). It is unreasonable for Examiner to review all of the cited references thoroughly. By signing the accompanying 1449 form(s), Examiner is merely acknowledging the submission of the cited references and indicating that only a cursory review has been made. Examiner notes that Therasense, Inc. v. Becton, Dickinson and Co., 649 F.3d 1276 (Ct. App. 2011) (en banc) has significantly restricted the infringement defense of inequitable conduct. A defendant must show that the patent in question would not have been issued but for undisclosed information, and that the patentee had the intent to deceive. Examiner suggests that future Information Disclosure Statements cite only the most relevant/inclusive references or portions thereof. Claim Objections The claims are objected to because they include reference characters which are not enclosed within parentheses: Claim 1 (line 2) recites "a switch component comprising a field-effect transistor, FET, comprising a drain terminal". It is unclear if "FET" is an abbreviation for the field-effect-transistor, or there are two transistors noted in the claim language. If the FET is used as an acronym, then replace the commas with parentheses, e.g. (FET). Claim 3 (lines 1-2) recites "a Gallium Nitride FET, GaN". It is unclear if "GaN" is an abbreviation for Gallium Nitride FET, or if the “GaN” is only referring to the type of FET. In view the use in claim 4, it is recommended that the claim be written as: The solid state switch device of claim 1, wherein the FET is a “Gallium Nitride FET” (GaN). This would be interpreted that “GaN” would substitute for the full quoted term rather than only the chemical designation of Gallium Nitride. Claim 5 (lines 1-2) recites "a Silicon Carbide FET, SiC". It is unclear if "SiC" is an abbreviation for Silicon Carbide FET, or there are two transistors noted in the claim language. Similar concern as discussed in claim 3 above. Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m). 07-29-01 AIA Claim s 1 and 17 are objected to because of the following informalities: Claim 1 (line 6) recites "a sense device for compensating current leakage of the switch component". It appears "the" is missing in front of "current leakage of the switch component". The reference "(i2)" on line 11 of claim 1 should appear after "a sense device leakage current" on line 7 of claim 1. The reference "(i2)" on line 7 of claim 17 should appear after "a sense device leakage current" on line 4 of claim 17 . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 10-11 and 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 (lines 4-5) recites "wherein the second transistor device has a first scale greater than a second scale of the first transistor device". It is unclear what "a first scale" and "a second scale" refers to in the context and how they are being compared such that one can be considered greater than the other. Examiner will interpret this "scale" to be channel width to length ratio. Claim 11 inherits the defects of the associated parent claim and/or any intervening claims. Claim 11 recites the limitation "the second transistor device comprises more transistors than the first transistor device" in lines 1-2 . There is insufficient antecedent basis for this limitation in the claim. A first transistor and a second transistor were not shown in claim 8, nor in claim 1. It is unclear how the structure of claim 11 is connected to the structure of claim 8, as there is no claim language for a first transistor. It appears this claim is dependent on claim 10. Claim 11 (lines 1-2) recites "the second transistor device comprises more transistors than the first transistor device". It is unclear how a transistor can include more transistors within. Claim 13 (lines 6-7) recites "wherein the first FET has a first scale greater than a second scale of the second FET". It is unclear what "a first scale" and "a second scale" refers to in the context and how they are being compared such that one can be considered greater than the other. Examiner will interpret this "scale" to be channel width to length ratio. 07-34-05 AIA Claim 14 recites the limitation " the voltage source supply (Vss) " in lines 2-3 . There is insufficient antecedent basis for this limitation in the claim. 07-34-05 AIA Claim 15 recites the limitation " the voltage source supply (Vss) " in lines 1-2 . There is insufficient antecedent basis for this limitation in the claim. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer . 08-35 Claim s 1-2 and 6-18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1 and 4-16 of copending Application No. 18/524,777 (reference application) . Although the claims at issue are not identical, they are not patentably distinct from each other because of the anticipating limitations in bold and underlined , as shown in Table 1 below . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Instant Application 19/007,345 Instant Application 18/524,777 Claim 1: A solid state switch device, comprising: a switch component comprising a field-effect transistor, FET, comprising a drain terminal, a source terminal, a gate terminal, and configured to generate a switch component leakage current based on non-idealities of the FET; a compensation circuit comprising: a sense device for compensating current leakage of the switch component, and configured to generate a sense device leakage current that is correlated with the switch component leakage current; and a current amplifier configured to: generate an estimated switch component leakage current ( ~i 1 ) based on the sense device leakage current ( i 2 ) ; output the estimated switch component leakage current to the drain terminal of the FET in order to compensate for the switch component leakage current. Claim 2: The solid state switch device of claim 1, wherein the compensation circuit is configured to: detect a voltage level at the drain terminal of the FET; and apply the voltage level to the sense device in order to generate the sense device leakage current correlated with the switch component leakage current . Claim 1: A solid state switch device, comprising: a switch component comprising a metal-oxide-semiconductor field-effect transistor, FET, comprising a drain terminal, a source terminal, a gate terminal, and configured to generate a switch component leakage current based on non-idealities of the FET; a compensation circuit comprising: a sense device for compensating current leakage of the switch component, and configured to generate a sense device leakage current that is correlated with the switch component leakage current, including to: detect a voltage level at the drain terminal of the FET; and apply the voltage level to the sense device in order to generate the sense device leakage current correlated with the switch component leakage current; and a current amplifier configured to: generate an estimated switch component leakage current based on the sense device leakage current; output the estimated switch component leakage current to the drain terminal of the FET in order to compensate for the switch component leakage current. Claim 6: The solid state switch device of claim 1, wherein the estimated switch component leakage current is a multiple of the sense device leakage current. Claim 4: The solid state switch device of claim 1, wherein the estimated switch component leakage current is a multiple of the sense device leakage current. Claim 7: The solid state switch device of claim 1, wherein the sense device leakage current is correlated with the switch component leakage current such that the sense device leakage current is N times less than the switch component leakage current. Claim 5: The solid state switch device of claim 1, wherein the sense device leakage current is correlated with the switch component leakage current such that the sense device leakage current is N times less than the switch component leakage current. Claim 8: The solid state switch device of claim 1, wherein the estimated switch component leakage current is a multiple of the sense device leakage current, wherein the sense device leakage current is correlated with the switch component leakage current such that the sense device leakage current is N times less than the switch component leakage current, wherein the multiple is N. Claim 6: The solid state switch device of claim 1, wherein the estimated switch component leakage current is a multiple of the sense device leakage current, wherein the sense device leakage current is correlated with the switch component leakage current such that the sense device leakage current is N times less than the switch component leakage current, wherein the multiple is N. Claim 9: The solid state switch device of claim 1, wherein the FET is a buried oxide isolated device, and the switch component further comprises an electrostatic discharge (ESD) diode, wherein the switch component leakage current is further based on non-idealities of the ESD diode. Claim 7: The solid state switch device of claim 1, wherein the FET is a buried oxide isolated device, and the switch component further comprises an electrostatic discharge (ESD) diode, wherein the switch component leakage current is further based on non-idealities of the ESD diode. Claim 10: The solid state switch device of claim 1, wherein the current amplifier is a current mirror comprising: a first transistor device coupled to the sense device; and a second transistor device coupled to the drain terminal of the FET of the switch component, wherein the second transistor device has a first scale greater than a second scale of the first transistor device. Claim 8: The solid state switch device of claim 1, wherein the current amplifier is a current mirror comprising: a first transistor device coupled to the sense device; and a second transistor device coupled to the drain terminal of the FET of the switch component, wherein the second transistor device has a first scale greater than a second scale of the first transistor device. Claim 11: The solid state switch device of claim 8, wherein the second transistor device comprises more transistors than the first transistor device. Claim 9: The solid state switch device of claim 8, wherein the second transistor device comprises more transistors than the first transistor device. Claim 12: The solid state switch device of claim 1, wherein the current amplifier comprises an operational amplifier comprising a first output and a second output, wherein the first output sources a first current, wherein the second output sources a second current, wherein the second current is a multiple of the first current, wherein the first output is coupled to the sense device, wherein the second output is coupled to the drain terminal of the FET of the switch component. Claim 10: The solid state switch device of claim 1, wherein the current amplifier comprises an operational amplifier comprising a first output and a second output, wherein the first output sources a first current, wherein the second output sources a second current, wherein the second current is a multiple of the first current, wherein the first output is coupled to the sense device, wherein the second output is coupled to the drain terminal of the FET of the switch component. Claim 13: The solid state switch device of claim 1, wherein the switch component is a first switch component, the FET is a first FET, and the sense device is a second switch component, wherein the second switch component comprises a second FET comprising: a drain terminal, a source terminal, a gate terminal, wherein the sense device leakage current is based on non-idealities of the second FET, wherein the first FET has a first scale greater than a second scale of the second FET. Claim 11: The solid state switch device of claim 1, wherein the switch component is a first switch component, the FET is a first FET, and the sense device is a second switch component, wherein the second switch component comprises a second FET comprising: a drain terminal, a source terminal, a gate terminal, wherein the sense device leakage current is based on non-idealities of the second FET, wherein the first FET has a first scale greater than a second scale of the second FET. Claim 14: The solid state switch device of claim 1, wherein the sense device comprises a cathode coupled to the current amplifier and an anode coupled to the voltage source supply (Vss). Claim 12: The solid state switch device of claim 1, wherein the sense device comprises a cathode coupled to the current amplifier and an anode coupled to a voltage source supply (Vss). Claim 15: The solid state switch device of claim 1 , wherein the sense device is coupled to the voltage source supply (Vss) via a switch, wherein the switch is configured to be open when the switch component is closed. Claim 13: The solid state switch device of claim 12 , wherein the sense device is coupled to the voltage source supply, Vss, via a switch, wherein the switch is configured to be open when the switch component is closed. Claim 16: The solid state switch device of claim 1, further comprising a temperature sensor configured to activate the compensation circuit upon sensing a temperature above a temperature threshold. Claim 14: The solid state switch device of claim 1, further comprising a temperature sensor configured to activate the compensation circuit upon sensing a temperature above a temperature threshold. Claim 17: A compensation circuit comprising: a sense device for leakage compensation of a switch component leakage current of a switch component, and configured to generate a sense device leakage current; and a current amplifier configured to: generate an estimated switch component leakage current ( ~i 1 ) based on the sense device leakage current ( i 2 ) ; output the estimated switch component leakage current to the switch component in order to compensate for the switch component leakage current. Claim 2: The solid state switch device of claim 1, wherein the compensation circuit is configured to: detect a voltage level at the drain terminal of the FET ; and apply the voltage level to the sense device in order to generate the sense device leakage current correlated with the switch component leakage current . Claim 15: A compensation circuit comprising: a sense device for leakage compensation of a switch component leakage current of a switch component, and configured to generate a sense device leakage current, including to: detect a voltage level at an output of a switch component ; and apply the voltage level to the sense device in order to generate the sense device leakage current; and a current amplifier configured to: generate an estimated switch component leakage current based on the sense device leakage current; output the estimated switch component leakage current to the switch component in order to compensate for the switch component leakage current. Claim 18: The compensation circuit of claim 17 , wherein the estimated switch component leakage current is a multiple of the sense device leakage current. Claim 16: The compensation circuit of claim 15 , wherein the estimated switch component leakage current is a multiple of the sense device leakage current. Table 1 08-30 AIA A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co. , 151 U.S. 186 (1894); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert , 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. 08-32 Claim s 19-20 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claim s 17-18 of copending Application No. 18/524,777 (reference application) . This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 5-8, 15 and 17-20 are rejected under 35 U.S.C. 102( a)(1) and 102(a)(2 ) as being anticipated by Englekirk (US 20230037837 A1); hereinafter Englekirk . Regarding Claim 1 , Englekirk discloses [Fig. 1/2/3/4] a solid state switch device, comprising: a switch component comprising a field-effect transistor [M], FET, comprising a drain terminal [M-drain], a source terminal [M-source], a gate terminal [M-gate], and configured to generate a switch component leakage current [Leakage Current] based on non-idealities of the FET; a compensation circuit [108/106] comprising: a sense device [108; resistive divider (paragraph 0003)] for compensating current leakage of the switch component, and configured to generate a sense device leakage current [output of 108 to input of 106] that is correlated with the switch component leakage current [paragraphs 0002-0005, 0021-0034]; and a current amplifier [106] configured to: generate an estimated switch component leakage current [output of 106] based on the sense device leakage current; output the estimated switch component leakage current to the drain terminal of the FET [thru the gate of M] in order to compensate for the switch component leakage current. Regarding Claim 2 , Englekirk discloses the solid state switch device of claim 1, wherein the compensation circuit is configured to: detect a voltage level at the drain terminal of the FET [voltage at M-drain (Vout)]; and apply the voltage level to the sense device in order to generate the sense device leakage current correlated with the switch component leakage current [paragraphs 0002-0005, 0021-0034]. Regarding Claim 3 , Englekirk discloses the solid state switch device of claim 1, wherein the FET is a Gallium Nitride FET, GaN [paragraphs 0050-0052]. Regarding Claim 5 , Englekirk discloses the solid state switch device of claim 1, wherein the FET is a JFET or a Silicon Carbide FET, SiC [paragraph 0050-0052]. Regarding Claim 6 , Englekirk discloses the solid state switch device of claim 1, wherein the estimated switch component leakage current is a multiple [bracketed 'N' at switch component M] of the sense device leakage current. Regarding Claim 7 , Englekirk discloses the solid state switch device of claim 1, wherein the sense device leakage current is correlated with the switch component leakage current such that the sense device leakage current is N times less than the switch component leakage current [paragraph 0003; resistive divider network that provides a scaled version of Vout]. Regarding Claim 8 , Englekirk discloses the solid state switch device of claim 1, wherein the estimated switch component leakage current is a multiple of the sense device leakage current [output of 108 to the input of 106, compared to the reference voltage, and the difference is amplified making it a multiple of the sense device leakage current], wherein the sense device leakage current is correlated with the switch component leakage current such that the sense device leakage current is N times less than the switch component leakage current, wherein the multiple is N [paragraph 0003; resistive divider network that provides a scaled version of Vout]. Regarding Claim 15 , as best understood, Englekirk discloses the solid state switch device of claim 1, wherein the sense device is coupled to the voltage source supply via a switch [108 to VDD thru M], wherein the switch is configured to be open when the switch component is closed. Regarding Claim 17 , Englekirk discloses [Fig. 1/2/3/4] a compensation circuit [108/106] comprising: a sense device [108; resistive divider (paragraph 0003)] for leakage compensation of a switch component leakage current [Leakage Current] of a switch component [M], and configured to generate a sense device leakage current [output of 108 to input of 106]; and a current amplifier [106] configured to: generate an estimated switch component leakage current [output of 106] based on the sense device leakage current; output the estimated switch component leakage current to the switch component in order to compensate for the switch component leakage current. Regarding Claim 18 , Englekirk discloses the compensation circuit of claim 17, wherein the estimated switch component leakage current is a multiple [bracketed 'N' at switch component M] of the sense device leakage current. Regarding Claim 19 , Englekirk discloses a method of compensating [Fig. 1/2/3/4] for a switch component leakage current [Leakage Current] of a switch component [M], the method comprising: determining a voltage level [Vout] at an output of the switch component [M-drain]; applying the voltage level to a sense device [108; resistive divider (paragraph 0003)]; determining a sense device leakage current [output of 108 to input of 106] of the sense device that is correlated with the switch component leakage current [paragraphs 0002-0005, 0021-0034]; generating an estimated switch component leakage current [output of 106] based on the sense device leakage current; outputting the estimated switch component leakage current to the output of the switch component in order to compensate for the switch component leakage current. Regarding Claim 20 , Englekirk discloses the method of claim 19, wherein the estimated switch component leakage current is a multiple [bracketed 'N' at switch component M] of the sense device leakage current . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Englekirk, in view of Kinzer et al. (US 20170222644 A1); hereinafter Englekirk, in view of Kinzer . Regarding Claim 4 , Englekirk discloses the solid state switch device of claim 3, wherein the FET is a first GaN [paragraphs 0050-0052]. Englekirk does not explicitly disclose the switch component further comprises a second GaN comprising: a drain terminal, a source terminal, a gate terminal, wherein the source terminal of the second GaN is coupled to the source terminal of the first GaN. However, Kinzer discloses [Fig. 3A/3B/4A/4B] wherein the FET is a first GaN [Q5; paragraph 0002] and the switch component further comprises a second GaN [Q6; paragraph 0002] comprising: a drain terminal [Q6-D], a source terminal [Q6-S], a gate terminal [arrow pointing into Q6], wherein the source terminal of the second GaN is coupled to the source terminal of the first GaN [Q5-S directly coupled to Q6-S]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Kinzer in the invention of Englekirk, with the expected benefit of conducting current in both directions to improve efficiency. This method of improving Englekirk using Kinzer was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Kinzer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk and Kinzer to obtain the invention: incorporating the bidirectional switch in place of the M transistor switch . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Englekirk, in view of Cai et al. (US 9305916 B1); hereinafter Englekirk, in view of Cai . Regarding Claim 9 , Englekirk does not explicitly disclose the solid state switch device of claim 1, wherein the FET is a buried oxide isolated device, and the switch component further comprises an electrostatic discharge (ESD) diode, wherein the switch component leakage current is further based on non-idealities of the ESD diode. However, Cai discloses wherein the FET is a buried oxide isolated device [column 2, lines 30-40], and the switch component further comprises an electrostatic discharge (ESD) diode [Abstract; Fig. 1], wherein the switch component leakage current is further based on non-idealities of the ESD diode. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Cai in the invention of Englekirk, with the expected benefit of achieving much higher operating speeds. This method of improving Englekirk using Cai was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Cai. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk and Cai to obtain the invention: incorporating the FET ESD protection device in place of the M transistor switch . 07-21-aia AIA Claim s 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Englekirk, in view of Yan et al. (WO 2022205764 A1); hereinafter Englekirk, in view of Yan . Regarding Claim 10 , as best understood, Englekirk does not explicitly disclose the solid state switch device of claim 1, wherein the current amplifier is a current mirror comprising: a first transistor device coupled to the sense device; and a second transistor device coupled to the drain terminal of the FET of the switch component, wherein the second transistor device has a first scale greater than a second scale of the first transistor device. However, Yan discloses wherein the current amplifier [Fig. 3/4, 22] is a current mirror [Fig. 3/4, 22] comprising: a first transistor device [M221] coupled to the sense device [Fig. 3/4, 21]; and a second transistor device [M222] coupled to the drain terminal of the FET [Fig. 3, M10-drain; Fig. 4, M11-drain] of the switch component, wherein the second transistor device has a first scale greater than a second scale of the first transistor device [paragraphs referring to Fig. 4 Description (pages 24-26 of merged file attached)]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Yan in the invention of Englekirk, with the expected benefit of scaling capabilities. This method of improving Englekirk using Yan was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Yan. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk and Yan to obtain the invention: incorporating the current mirror in place of the amplifier. Regarding Claim 13 , as best understood, Englekirk does not explicitly disclose the solid state switch device of claim 1, wherein the switch component is a first switch component, the FET is a first FET, and the sense device is a second switch component, wherein the second switch component comprises a second FET comprising: a drain terminal, a source terminal, a gate terminal, wherein the sense device leakage current is based on non-idealities of the second FET, wherein the first FET has a first scale greater than a second scale of the second FET. However, Yan discloses wherein the switch component is a first switch component [Fig. 3, M10], the FET is a first FET [M10], and the sense device [Fig. 3, 21] is a second switch component [21], wherein the second switch component comprises a second FET [Fig. 3, M21] comprising: a drain terminal [M21-drain], a source terminal [M21-source], a gate terminal [M21-gate], wherein the sense device leakage current is based on non-idealities of the second FET, wherein the first FET has a first scale greater than a second scale of the second FET [paragraphs referring to Fig. 4 Description (pages 24-26 of merged file attached)]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Yan in the invention of Englekirk, with the expected benefit of scaling capabilities. This method of improving Englekirk using Yan was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Yan. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk and Yan to obtain the invention: incorporating the current mirror in place of the amplifier . 07-21-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Englekirk, in view of Yan; further in view of Hasegawa (US 20060097774 A1); hereinafter Englekirk, in view of Yan; further in view of Hasegawa . Regarding Claim 11 , as best understood, Englekirk, in view of Yan, does not explicitly disclose the solid state switch device of claim 8, wherein the second transistor device comprises more transistors than the first transistor device. However, Hasegawa discloses wherein the second transistor device comprises more transistors than the first transistor device [Abstract; Fig. 2, 2]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Hasegawa in the invention of Englekirk, in view of Yan, with the expected benefit of controlling the currents. This method of improving Englekirk, in view of Yan, using Hasegawa was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Hasegawa. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk, in view of Yan, and Hasegawa to obtain the invention: incorporating the current mirror in place of the amplifier . 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Englekirk, in view of Rooran (JP H077400 A); hereinafter Englekirk, in view of Rooran . Regarding Claim 12 , Englekirk does not explicitly disclose the solid state switch device of claim 1, wherein the current amplifier comprises an operational amplifier comprising a first output and a second output, wherein the first output sources a first current, wherein the second output sources a second current, wherein the second current is a multiple of the first current, wherein the first output is coupled to the sense device, wherein the second output is coupled to the drain terminal of the FET of the switch component. However, Yan does not explicitly disclose, wherein the second current is a multiple of the first current, these are just different quantities and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute the N factor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art. However, Rooran discloses the solid state switch device [Fig. 1], wherein the current amplifier comprises an operational amplifier [45] comprising a first output and a second output [output of 45], wherein the first output sources a first current [current to 2], wherein the second output sources a second current [current to 50], wherein the first output is coupled to the sense device, wherein the second output is coupled to the drain terminal of the MOSFET of the switch component. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Rooran in the invention of Englekirk, with the expected benefit of providing amplification to the current signals. This method of improving Englekirk using Rooran was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Rooran. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk and Rooran to obtain the invention: incorporating the amplifier with two outputs . 07-21-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Englekirk, in view of Gammie et al. (US 6667650 B2); hereinafter Englekirk, in view of Gammie . Regarding Claim 14 , as best understood, Englekirk does not explicitly disclose the solid state switch device of claim 1, wherein the sense device comprises a cathode coupled to the current amplifier and an anode coupled to the voltage source supply. However, Gammie discloses wherein the sense device [Fig. 4, 402] comprises a cathode coupled to the current amplifier [404; column 4, lines 25-38] and an anode coupled to the voltage source supply [negative supply voltage; column 4, lines 25-38]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Gammie in the invention of Englekirk, with the expected benefit of determining the amount of leakage current loss. This method of improving Englekirk using Gammie was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Gammie. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk and Gammie to obtain the invention: incorporating a diode to be coupled to the sense device and the voltage source supply . 07-21-aia AIA Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Englekirk, in view of Namuduri et al. (US 20210143811 A1); hereinafter Englekirk, in view of Namuduri . Regarding Claim 16 , Englekirk does not explicitly disclose the solid state switch device of claim 1, further comprising a temperature sensor configured to activate the compensation circuit upon sensing a temperature above a temperature threshold. However, Namuduri discloses wherein the solid state switch device [Fig. 1, 102], further comprising a temperature sensor [thermistor 134] configured to activate the compensation circuit upon sensing a temperature above a temperature threshold [paragraphs 0003-0018]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Namuduri in the invention of Englekirk, with the expected benefit of preventing overheating. This method of improving Englekirk using Namuduri was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Namuduri. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Englekirk and Namuduri to obtain the invention: incorporating a temperature sensor for the compensation circuit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Amit R Bhatia/Examiner, Art Unit 2836 /REGIS J BETSCH/SPE, Art Unit 2836 Application/Control Number: 19/007,345 Page 2 Art Unit: 2836 Application/Control Number: 19/007,345 Page 3 Art Unit: 2836 Application/Control Number: 19/007,345 Page 4 Art Unit: 2836 Application/Control Number: 19/007,345 Page 5 Art Unit: 2836 Application/Control Number: 19/007,345 Page 6 Art Unit: 2836 Application/Control Number: 19/007,345 Page 7 Art Unit: 2836 Application/Control Number: 19/007,345 Page 8 Art Unit: 2836 Application/Control Number: 19/007,345 Page 9 Art Unit: 2836 Application/Control Number: 19/007,345 Page 10 Art Unit: 2836 Application/Control Number: 19/007,345 Page 11 Art Unit: 2836 Application/Control Number: 19/007,345 Page 12 Art Unit: 2836 Application/Control Number: 19/007,345 Page 13 Art Unit: 2836 Application/Control Number: 19/007,345 Page 14 Art Unit: 2836 Application/Control Number: 19/007,345 Page 15 Art Unit: 2836 Application/Control Number: 19/007,345 Page 16 Art Unit: 2836 Application/Control Number: 19/007,345 Page 17 Art Unit: 2836 Application/Control Number: 19/007,345 Page 18 Art Unit: 2836 Application/Control Number: 19/007,345 Page 19 Art Unit: 2836 Application/Control Number: 19/007,345 Page 20 Art Unit: 2836 Application/Control Number: 19/007,345 Page 21 Art Unit: 2836 Application/Control Number: 19/007,345 Page 22 Art Unit: 2836 Application/Control Number: 19/007,345 Page 23 Art Unit: 2836 Application/Control Number: 19/007,345 Page 24 Art Unit: 2836 Application/Control Number: 19/007,345 Page 25 Art Unit: 2836 Application/Control Number: 19/007,345 Page 26 Art Unit: 2836 Application/Control Number: 19/007,345 Page 27 Art Unit: 2836 Application/Control Number: 19/007,345 Page 28 Art Unit: 2836 Application/Control Number: 19/007,345 Page 29 Art Unit: 2836 Application/Control Number: 19/007,345 Page 30 Art Unit: 2836 Application/Control Number: 19/007,345 Page 31 Art Unit: 2836 Application/Control Number: 19/007,345 Page 32 Art Unit: 2836 Application/Control Number: 19/007,345 Page 33 Art Unit: 2836 Application/Control Number: 19/007,345 Page 34 Art Unit: 2836 Application/Control Number: 19/007,345 Page 35 Art Unit: 2836 Application/Control Number: 19/007,345 Page 36 Art Unit: 2836 Application/Control Number: 19/007,345 Page 37 Art Unit: 2836 Application/Control Number: 19/007,345 Page 38 Art Unit: 2836 Application/Control Number: 19/007,345 Page 39 Art Unit: 2836 Application/Control Number: 19/007,345 Page 40 Art Unit: 2836 Application/Control Number: 19/007,345 Page 41 Art Unit: 2836
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